Design for Testability (DFT) Basic Concepts

 DFT is a technique that makes test generation and test application easier
and cost effective.
 In testing of sequential circuits it is difficult to control and observe the
internal flops.
 DFT techniques help in making the internal flip-flop easily controllable
and observable.

Overview of DFT Techniques

Ad-hoc techniques hoc techniques
These are a collection of techniques or set of rules (do’s and don’ts) in the chip
design process learned from design experience to make design testability more
comfortable to accomplish.

The method of ad hoc mainly uses some experience of guide line and practice to
replace bad design. The main techniques are:
1) Insert test point;
2) Avoid a sync set/reset for storage elements;
3) avoid combinational feedback;
4) avoid redundant logic;
5) avoid async logic;
6) Partition a large circuit into small blocks;

Test point insertion (TPI): First, internal nodes are obtained through testability
analysis.
Observation point insert: SE=0, capture result; SE=1, shift result;
control point insert: TM=0; destination = source; TM=1; destination = CP_input

scan point: consists of a control point and an observation point.

Adding test point will increase the delay of logic path.
Test points can be shared by multiple internal nodes, thereby reducing the area.

 
Structured techniques
In this technique, extra logic and signals are added to the circuit to allow the test
according to some predefined procedure.
A few examples of structured DFT which we will cover extensively in future
lessons:
 Scan Path
 Partial Scan
 Level Sensitive Scan
 BIST
 Boundary Scan

• Defect: unintended difference between the implemented HW and its intended

design – May or may not cause a system failure
Fault: representation of a defect at the abstracted function level
• Error: Manifestation of a fault that results in incorrect circuit (system) outputs
or states – Caused by faults
A Fault Model is an engineering representation of something that could go
wrong in the production, development, or operation of a piece of equipment or
product.
Advantages of fault models:
 Drastically reduces the number of faults to be considered.
 Makes test generation and fault simulation possible.
 We can evaluate fault coverage and compare test sets.

Why Model Faults ?

A fault model identifies targets for testing
Fault model limits the scope of test generation
A fault model makes analysis possible
 Effectiveness measurable by experiments

What is stuck-at fault in DFT?

When a signal, or gate output, is stuck at a 0 or 1 value, independent of
the inputs to the circuit, the signal is said to be “stuck at” and the fault
model used to describe this type error is called a “stuck at fault model”.

Three properties define a single stuck-at fault

• Only one line is faulty
• The faulty line is permanently set to 0 or 1
• The fault can be at an input or output of a gate

 2.  At-speed Faults

It models the manufacturing defects that behave as gross delays on gate input-
output ports. So each port is tested for logic 0-to-1 transition delay (slow-to-rise
fault) or logic 1-to-0 transition delay (slow-to-fall fault).

Bridging Faults

A bridging fault is said to have occurred when two or more signal lines in
a circuit are accidentally connected together. It is quite possible due to
imperfection during layout fabrication.

Delay Faults

Delay faults are those in which a pin of a gate responds to the transition
too slowly on a particular set of stimuli, plus a specific transition.
Path delay fault model
Let’s say due to some faults in gates propagation delay of each gate is
increased by some amount. 
No. of path delay faults in a circuit = 2 x No. of paths
 Transition delay fault model
In this model, faults are assumed to be lumped in a single node, as shown
by a red cross. Each node has two transition delay faults: slow-to-rise
and slow-to-fall (STF).
No. of path delay faults in a circuit = 1-STR + 1-STF = 2

Switch Level Fault Model

Here, the circuit is specified at the transistor level. For example, a

Netlist of CMOS gates. MOS transistors are considered as ideal switches in
this model. Two types of switch level fault models are common:

 Stuck-Open Fault
 Stuck-Short Fault

IDDQ Testing

The above experiment is also known as IDDQ testing (Quiescent Drain

Current testing).

Advantage: Apart from stuck-short faults, this testing has high defect

coverage for other faults too (including stuck-open as well as bridging
faults).

Disadvantage: IDDQ testing is losing relevance in deep sub-micron CMOS

technology, as the transistor leakage currents become comparable with the
IDDQ current. Moreover, there is a design constraint that the circuit must
be designed with low IDDQ.

No. of possible stuck-open/short faults in a circuit = No. of transistors in

Switch level abstraction

Test Generation or Fault Detection

The aim of test generation at the gate level is to verify that each logic gate in
the circuit is functioning correctly, and the interconnections are good. If only a
single stuck-at fault is assumed to be present in the circuit under test, then the
problem is to construct a test set that will detect the fault by utilizing only the
inputs and the outputs of the circuit.

Assuming a single stuck-at fault model, we apply a specific set of signals to

the circuit input as a test. This is known as the Test Vector. A single test
vector will only detect a particular stuck-at fault at a specific location. To
detect all the stuck-at faults, we need to apply a series of test vectors
sequentially. This series is also known as the Test Pattern.

Fault equivalent :

while creating fault site list, tool identifies fault which are dependent to each
other and consider them as equivalent faults.

Fault collapsing :

If 4 faults are equivalent, then tool mark one of them as a real fault and rest
three of them are marked as collapsed to the real fault. This concept is
called fault collapsing. With this tool need to work on only one fault instead of
four faults.

Fault simulation :

After we generate all the test patterns, we need to validate those test patterns.
So, we can trust those test patterns as golden test patterns. Thus we run
simulation those test patterns with fault. This process is called fault simulation.

What is fault dominance in DFT?

Fault Dominance. ❖If all tests of some fault F1 detect another fault F2, then
F2 is said to dominate F1.

For any “n” input gate, the number of faults remaining after equivalent and
dominant collapsing is “n+1”.

Test pattern generation (TPG) is the process of generating test patterns

for a given fault model. Automatic Test Pattern Generation, or ATPG, is
a process used in semiconductor electronic device testing wherein the test
patterns required to check a device for faults are automatically generated
by a program.

Stages of ATPG

ATPG algorithm is a two-stage process.

Random Test Pattern Generation: In this method, we randomly generate test
patterns and select those patterns that detect undetected faults. There is no target
fault. Since test patterns are generated by trial and error method, this is a
pretty fast and inexpensive process

Deterministic Test Pattern Generation: In this method, we select a specific

target fault and apply various algorithms like D, PODEM, or FAN. This is
a time-consuming algorithmic method and relatively expensive than Random
TPG.
Benefits of ATPG

The following are the benefits of ATPG that made it popular in the EDA
industry.

 Generates high-coverage test patterns

 Lowers test time and cost
 Reduce Human efforts
 Ensures easy, risk-free deployment into design and test flows

DFT in Sequential Circuits

Earlier in this DFT course, we learnt a few test generation techniques in

combinational circuits. But their major drawback was, they weren’t suitable for
sequential circuits. From this article onwards, we will discuss the industry-grade
techniques employed in Design for Testability.

Controllability and Observability Issues

The flip-flops are the main culprits that make sequential circuit testing difficult.
The idea is to separate the flip-flops from the rest of the circuit so that the
combinational part can be tested easily using ATPG. Now, if we can control and
observe these pseudo inputs and outputs to the combinational circuit, we can
easily test this circuit with previously discussed ATPG methods. Hence, we
don’t need to worry about flip-flops. This is the essence of Internal Scan
Design.

Scan Flip-Flop

Here’s a typical implementation of the Scan Flip-Flop (SFF) using a normal

Flip-Flop. Muxed-D Scan Flip Flop, as the name suggests, this is a
conventional flip-flop with a 2:1 MUX before it. This additional feature allows
the flip-flop to be initialized with any value by setting the Scan Enable Pin.
Scan Flip-Flop has four main pins:

 Scan Chain: Scan In (SI), Scan Out (SO)

 Logic: Data In (DI), Data Out (DO)

DO and SO pins are shared, as shown in the diagram. The Scan Enable pin is

the select line to the multiplexer, which selects between the Data In and
the Scan In input. The DFF captures the value, which is decided by the Scan
Enable pin. Scan Flip-Flop has two functions:

 Shift data from SI pin to SO pin (when SE = 1)

 Capture data from the combinational circuit (when SE = 0)

Scan Chain

Let’s incorporate this new flip-flop into our design.

In the modified design, the scan flip-flops are stitched together one after another
in a Scan Chain. In the previous circuit, the outputs of the combinational circuit
were directly connected to the flip-flop inputs. But, in the newer design, we
have disconnected the line using a multiplexer. Now, we have the choice to
either connect the combinational circuit output to the flip flop inputs (Normal
Mode) or to connect it to Scan In pin (Test Mode). Hence the circuit now has
two operation modes: Normal mode and Test mode.

The idea of the Internal Scan is to connect internal Flip-Flops and latches so that
we can observe them in test mode. Scan remains one of the most popular
structured techniques for digital circuits. This above process is known as Scan
chain Insertion. In the VLSI industry, it is also known as DFT
Insertion or DFT synthesis.

The steps involved in DFT synthesis are:

 Replace FF/latch
 Stitch FF/latch into a chain

Modes of operation in Scan Chain

As previously discussed, Scan Chain operates in two modes.

Normal Mode

 In normal mode, Scan Flip-Flops are configured to

perform capture operation.
 They capture the response from the logic and then apply the response to
the logic in the next clock cycle.
 The Normal Mode is activated when Scan Enable is logic-o.
 The flip-flops capture the data from pseudo-primary outputs of the
combinational logic.
 This mode is exactly similar to the original mode, and the Scan flip-flops
can be simply ignored in this case in lieu of normal flip-flops.

Test Mode

 In test mode, the scan flip-flops are first configured to

perform shift operation so we can shift-in our test pattern.
 And then the scan flip-flops are configured to capture the response from
the logic.
 Finally, we configure the flip-flops to perform the shift-out operation so
that we can observe the values in the Scan flip-flops.
 The following steps are involved in test mode:

Step 1: Shift In
Step 2: Capture
Step 3: Shift Out
By converting sequential design to scan design, there are three working modes:

1) In normal mode, all test signals are turned off;

2) In shift mode and capture mode, the test mode signal is always valid;

Design Flow:

1) Convert the selected storage elements into scan cells;

2) Stitching these cells into a scan chains;

Implementation process:

1) Switch to shift mode, input the stimulus into the scan cell;

2) Switch to capture mode, input clock, capture value;

3) switch to shift mode, move out of response;

The scan cell has two different inputs:

1) Data input: driven by the combined logic of the circuit;

2) scan input: driven by another scan cell to form a scan chain;

In normal/capture mode, data input drives output;

In shift mode, scan input drives output;

Several scan_cells: muxed-D scan, clocked-scan, level-sensitive scan design

(LSSD);

muxed-D Scan cell: multi-fingered edge_triggered muxed-D scan cell,

consisting of a D flip-flop and a multiplexer,

scan enable (SE) is used to select the input of data input and scan input.

A level-sensitive muxed-D scan cell consists of a multiplexer, a D Latch, and a

D FF.

to replace an ordinary latch

Clocked-scan cell:
It is also mainly used to replace D-FF, but it is selected by two independent
clks.
A data clock DCK; a shift clock SCK;
The main advantage is that it will not affect the timing of the data path, but
requires one more clock routing.

LSSD scan cell:

Mainly used in level_sensitive, latch-based design.

The cell contains two latches, a master latch and a slave latch.

Among them, A/B/D are all clocks, D is data input, and I is scan input.

The advantage is that race-free can be guaranteed, but it will also increase the
routing of the clock.
Scan architecture
1) full-scan design: all storage elements are transformed into scan cell,
combinational ATPG to generate test;
The main advantage is to convert sequential ATPG into simple combinational
ATPG;
Almost full-scan design: do not add scan on some critical paths and
insignificant paths.
Muxed-D Full-Scan Design:

Clocked Full-Scan Design: Similar to Muxed-D, except that SE is no longer

used, and two clocks are used respectively.

LSSD Full-Scan Design: Two clocks C1/C2, A/B to control shift and capture
modes.
In the logic of full-scan, the input consists of two types:

primary input(PI), the external input of the circuit;

pseudo primary input (PPI), output of scan cell

Two outputs:

primary output (PO), the external output of the circuit;

pseudo primary output (PPO), input of scan cell;

2) partial-scan design: Part of the storage element is converted into scan cell,
combination and sequential ATPG to generate test;

In the test generation process, the sequential ATPG must contain the non-scan
FF control and observe, which will increase the test generation

Complexity, so the logic is generally separated, which can be based on

functional partition, pipeline/feed_forward partial design.

Full-scan and partial-scan are both defined as serial scan design. The advantage
is that the cost of routing will be relatively low. The disadvantage is that each
individual scan-cell cannot

On the premise of not affecting other cells in this scan chain, complete the shift
mode, resulting in high switching the power consumption.

Random-access scan completes the shift mode of a cell through RAM-like

address addressing.
3) random-access scan design: use random addressing instead of serial scan
chain;

The Q terminal of the Scan cell is directly connected to the SI terminal of the
next-level Scan cell. At the same time another load into the combinational logic.

During the capture process, the number of clocks must be controlled to ensure
that the response generated by ATPG is correct.

The positions of the stimulus and response Registers in each scan chain are not
corresponding. The one generated by ATPG shall prevail.

A typical scan implementation flow:

Clock mux and some resets are bypassed in Scan and cannot be detected. So the
test coverage of DFT is generally at 97% or 98%.

scan design rule checking and repair:

It can be done on pre-synthesis RTL design or post-synthesis gate-level design,

The design after scan repair is called testable design.

Scan synthesis converts a testable design into a scan design. Currently, the
design contains several scan chains.

Scan extraction is to extract the structure of the final scan chain for use by
ATPG.

Scan verification performs response verification for shift and capture

operations.

Scan Design Rule Checking and Repair

Check the scan design rule, and some clock control structures need to be
modified to increase the at-speed test.

The check of the scan design rule can also be done after the scan synthesis to
ensure that no new violations appear.

In the shift operation, all clocks can be controlled by external pins, between two
adjacent scan cells

Clock skew must be guaranteed not to cause shift failures.

In the capture operation, the originate/terminate clock of the data path may be
different, which needs to be considered

Timing to ensure the correct operation of capture.

Scan Synthesis

Scan synthesis transforms a testable design into a scan design.

In 1990, the operation of scan synthesis was some scattered tools, and the
Gate_level after logic synthesis

Netlist for processing.

Recently, the operation of scan synthesis has been integrated in logic synthesis,
such processing is called one-pass

Synthesis or single-pass synthesis.

It mainly includes four parts:

1)Scan configuration;

2)Scan replacement;

3)Scan reordering;

4) Scan stitching;

Scan chain mainly includes:

1) The number of scan chain;

2) The type of scan cells to implement these scan chains;

3) Storage element to be excluded from scan synthesis;

4) The way of scan cell arranged in scan chain; 

The scan chain number is mainly determined by the number of input and output
of the circuit, and the high-speed IO pad cannot

Used for scan IO multiplexing.

The type of scan cell is mainly determined by lib. Generally, each storage
element used will have a corresponding scan cell type.
To ensure that functionality and timing are minimally affected under normal
operation.

The storage element of exclude is mainly due to critical path or security reason.

The arrangement of the storage element is mainly determined by the number of

clock domains on these scan chains.

In general, a scan chain consists of scan cells belonging to the same clock
domain (because in the DC process, the entire scan chain is a data path

The asynchronous logic at this time will also be processed synchronously in

DFT. )

When a clock domain contains a lot of scan cells, some scan chains will be
structured and the scan-chain operation is used to reduce the length of the scan-
chain.

When a scan-chain contains both negative-edge scan cell and positive-edge scan
cell, the negative scan cell

Should be placed in front of the positive scan-cell. (only move one bit per cycle
for the clock)

The length of the scan-chain should be as balanced as possible to facilitate

parallelization.

If the positive scan-cell is placed in front, then the two cells will shift data
within one clock cycle.
When a scan-chain scan cell comes from a different clock domain, a lock-up
latch needs to be inserted.

In this way, it can be guaranteed that the operation of shift is correct regardless
of whether CK2 prioritizes CK1 or CK1 prioritizes CK2.

But it must be ensured that the skew between CK1 and CK2 is less than one
duty cycle.

When the clock structure of the scan chain is determined, the stitching of the
scan cell is carried out to the scan chain and these scan cells

place, stitch aims to minimize scan routing.

Scan Replacement:

After scan configuration, scan replacement replaces storage element with

functionally equivalent scan cell

The design at this time is called scan-ready design.

The inputs of these scan cells are usually connected to the outputs of the same
scan cell to avoid floating. These connections are removed at the stitch stage.

Currently, partial scan replacement can also be implemented in the RTL stage.

Scan Reordering

Reacts the reorder of scan cells in the scan chain. Before physical

implementation, a random scan order is used by design.

When performing physical implementation, scan order can use intra_scan_chain

reordering (scan cell is only in this scan

reorder within the chain) and inter_scan_chain reordering (scan cell reorder
between different scan chains)

 
scan stitching

Stitch all scan cells together to form a scan chain. Connect the output of each
scan cell to the input of the next level.

Connect the input of the first scan cell to the primary input, and the output of
the last scan cell to the primary output.

In the process of stitching, some lock_up latches and lock_up FFs need to be
inserted to ensure that the shift operation is correct.

After scan stitch, scan synthesis has been completed,

Scan extraction is mainly used to extract all instances from scan design to
ensure the integrity of the scan chain.

And ensure that all design changes are integrated into scan design.

Scan Verificaiton

1) Hold time violation in shift operate, if two scan cells are at the same clock,
CTS is required to ensure that there is a clock skew

The value of minimum. If the clock is an asynchronous clock, the lock_up latch
needs to be inserted.

2) Wrong scan initialization sequence, cannot enter test mode.

3) Check and repair of incomplete scan design rule, set/reset of reg and
enable/gate of clock, etc.

4) The error of scan synthesis, put the positive before the negative, etc.

The scan capture operation may have a mismatch between zero_delay and
full_timing.

Verifying the scan shift operate:

Use a flush test test case and use the full_timing simulator to ensure that the
number of clocks from scan input to scan output is the same.

In order to ensure that the clock skew also meets the requirements, the use case
uses a value such as "01100", including all scenarios of 0-0, 0-1, 1-0, and 1-1.

In order to quickly locate the position of the wrong scan cell, the flush testbench
needs to have a process that can observe the internal scan cell.

1) Scan hold time violation in different clock, Lock-up latch inserted.

   If there are multiple clocks in a scan chain, the latency between each clock is
different, and the design requires it to be kept within half a cycle.

   So adding a negative latch can solve this problem.

2) scan hold time and setup time in same clock, CTS redone or insert buffer.

3) Ensure that all negative-edges are in front of positive-edges, or add lock-up

FF.

Verify the scan Capture operate:

1) Usually apply a broadside-load testbench, directly move the entire test

pattern to the scan cell, including only one clock

shift cycle and a clock capture cycle.

At present, the verification of scan shift and scan capture can also be performed
by STA.

Scan Design Costs:

1) area overhead cost, including two parts, the replacement of scan cell and FF,
and the part of scan routing.

2) I/O pin cost, including a dedicated test mode pin (can be avoided by an initial
sequence)
And the shared with function of I/O.

3) Performance degradation cost, increasing the delay of functional path.

4) Design effort cost, in addition to the normal flow, design rule checking and
repair, scan synthesis,

scan extraction, scan verification.

Other purposes of scan design:

In summary, there are enhanced scan, snapshot scan, error_resilient scan,

system debug, soft error protection.

1) enhanced design, increased delay fault detection. A Latch is added to one of

the structures, and two bits of data are latched each time.

When doing STA at the same time, many false paths will also be added.

2) Snapshot Scan can capture internal states of element without interrupting the
functional operation of logic.

The design is realized by adding a scan cell to the required storage element (not
replacing it). This design is called a scan set.

 
RTL DESIGN FOR TESTABILITY:

Due to the time-to-market relationship, more and more testability issues hope to
be fixed in the RTL stage.

By performing testability repair on the Netlist , a loop is formed, and the DC

needs to be reset every time testability repair is performed.

Clock analysis in Prime Time includes:

1) Multiple clocks, clock from port/pin, virtual clock.

2) Clock network delay and skew, clock latency----delay of the clock network
relative to the source.

                                                 clock skew-----variation of arrival time of clock

at destination point.

3) Gated clock, perform both setup and hold check on the gating signal.

4) Generated clocks, such as clock divider or PLL.

5) Clock transition times, specify the transition times of clock signals.

 
create_clock -period 10 -waveform {2 4} [get_ports A]

The source of the clock can be port A, net N or pin Q of FF. When no source is
specified, it means virtual clock.

-name The name of the clock. If not added, it will be replaced by the source
name of the clock.

-add define two clocks on the same source, create_clock -period 20 -waveform
{1 3} [get_ports A] -add.

-waveform [a1 a2] The first value represents the first rising edge, and the first
value represents the first falling edge.

-source generally adds get_pins/get_ports, etc., indicating a port or gate circuit

interface.

-master_clock is generally a clock name, from commands such as create_clock

or create_generate_clock.

                     It can also be the get_ports command, which can be consistent

with the -source variable.

get_clocks -filter "period <= 5.0" PHI*

-filter performs conditional filtering.

get_clocks * means all clocks.

remove_clock [get_clocks CLKB*] Remove clock definitions. .

Specifying clock characteristics:

Latency includes clock source latency and clock network latency. The middle
point clock definition point.

The uncertainty represents the maximum difference in the clock arrival signals
of the register. Also called skew.
Use set_clock_latency -source to model the source latency, and divide the
model of network latency into different stages:

After post_layout, use set_propagated_clock to model, and in pre_layout, use

set_clock_latency to model.

set_clock_latency 1.5 -source -early [get_clocks CLK]

-rise/fall to specify latency in rising/falling edg.

-min/max specifies a range.

-late/early specifies longest path as late path, shortest path as early path.
               When doing setup check, the source clock is used as late version, and
the destination clock is used as early version.

               When doing hold check, the source clock is the early version, and the
destination clock is the late version.

-source specifies source latency, if not defined, it means network latency.

The value of clock jitter can be specified by -dynamic

Intraclock Uncertainty:

To define skew and jitter on single clock, you need to specify a clock, port, pin,

If you specify a clock, it means that all sequential elements of this clockdrive
will use this uncertainty,

If you specify a port, pin, it means that all fanout will use this uncertainty.

For the check of setup and hold, the value of uncertainty can be set differently, -
setup/-hold

setup check is affected by jitter and skew, and hold is only affected by skew.

set_clock_uncertainty -setup 0.5 [get_clocks C2] 

Interclock uncertainty:

-from means start clock (launch reg), -to means destination clock (capture reg)

Both setup check and hold check will be affected by jitter and skew.

set_clock_uncertainty -from C1 -to C2 -setup

set_clock_uncertainty -rise_from C1 -fall_to C2 0.5

The properties of -from and -to will be strictly enforced. If there is a situation
where -from models capture reg, it needs to be defined.

If both interclock uncertainty and intraclock uncertainty are defined, inter has a
higher priority.

 
set_clock_transition 0.64 -fall [get_clocks CLK1]

-fall/-rise, specify transition time respectively.

-min/max, respectively formulate the range.

For the analysis of multiple clock:

The relationship between two clocks can be: synchronous, asynchronous,

exclusive.
In the absence of other settings, if there is a path, launched by one clock,
captured by other clock, PT will think

The relationship between these two clocks is sync, the time zero defined by
create_clock is the sync point, expands to the two clock clocks

least common multiple, for synchronization and analysis.

Async clock, for two clock domains, clock edges can occur at any time of the
clock.

For such an async clock, launched by one clock, captured by other, PrimeTime
will not check the timing path,

After setting by the set_clock_groups -usync command, the effect is equivalent

to setting false path.

 Exclusive clock, no interact clock, only one clock is enabled at any given time.

set_clock_groups -logically_exclusive -group {CK1} -group {CK2}

When two groups are defined, it means that the two groups are exclusive, and
there is no such setting between the third group. (CK1 and CK2 exclusive)

set_clock_groups -logically_exclusive -group {CK1}

When only one group is defined, it means that the group and all remaining
clocks are set in this way. (CK1 and all remaining clocks are exclusive)

There is also a physically_exclusive setting, which is mainly used when PT SI

analyzes crosstalk.
Test Compress

EDT: Embedded Deterministic Test.

Included logic: Decompressor and Compactor

                 Masking logic

                 Addictional shift cycle(initialization, masking, lower-power bits)

                 Lockup cells and pipeline stages

Compression that can be done in the ATPG part

1) Standard techniques

      Static compression-----------Remove some redundant patterns

      Dynamic compression--------In the same pattern, test several faults targets

EDT is processed by parallelizing the Deterministic pattern generated by

ATPG.

EDT recommends a shorter scan chain and fewer shift cycles

Operation waveform:

Insertion of Lock_up cell:

1) Guarantee the correctness of the shift operation, one data per cycle

2) In other operations, a clock cycle can be saved because it uses the falling
edge.

ATPG

 Automatic Test Pattern Generation has several purposes:

 It can generate test patterns (obviously)
 It can find redundant circuit logic.
 It can prove one implementation matches another.

 Why is ATPG necessary?

 o Complete functional test is impractical.
o Designer generated functional patterns typically provide only 70-
75% SA coverage.
o ATPG supplements to get coverage to >98%.

 Scan is used to make testing of sequential circuits tractable.

 Penalties include:
 Scan hardware occupies between 5-20% of silicon area.
 Performance impact.
 Additional pins, e.g., scan_in and scan_out.
 Slower to apply.
 Allows combinational ATPG to be applied to test sequential logic.

ATPG stand for Automatic Test Pattern Generation. It takes a gate level netlist,
along with some input and output constraints, clock definitions, scan chain
definitions, and generates a test pattern that can be used to find manufacturing
defects in the real silicon. It also produces a fault coverage report that tells you
how good your test it, and which nets are and are not covered by the test pattern.

A Testbench is basically a simulation model used to simulate a design. The

design can be a block, or the full chip, and the model can be behavioral, rtl, or
gate. A Testbench can be used for many reasons. The most common usage is a
verification Testbench, used to verify the correctness of the functionality of the
design before Taping out a chip.
A verification Testbench will normally include a model of the block or chip
under test, other modules or chips that drive stimulus to the chip under test, and
some checker module to indicate whether the outputs behave according to
specification.
You can also have a Testbench that verifies the pattern produces by the ATPG
tool. This Testbench will normally mimic how a semiconductor tester (ATE)
will sequence the test pattern into the chip under test, and check whether the
outputs of the chip is identical to the expected values in the test pattern.

Input and Output constraints is defining some inputs to certain logic value to
enable ATPG to run correctly. For example, scan enable or and test mode
signals.
The number of pins usually does not matter in ATPG, but it does matter on the
ATE. But that is different issue

ATPG basic Flow

At_speed_test

Logic BIST reduces test costs by placing a lot of tester functionality in CUT,
but the more important aspect is at-speed testing.

The At-speed test consists of two parts:

1) intra-clock-domain fault: originates at one clock domain, terminates at the

same clock domain

2) inter-clock-domain fault: originates at one clock domain, terminates at

another clock domain

There are three basic capture-clocking schemes for multiple clock domain test:

1) single-capture;

2) skewed-load;

3) double-capture;

Two fault models:

1) structural faults, such as stuck-at faults and bridging faults;

2) delay faults, path-delay faults and transition faults;

With STUMPS-based architecture

Single-capture is a slow-speed test technology that only needs one capture pulse
to test the structural faults of intra-clock-domain and inter-clock-domain.

Two approaches to test.

1) One-Hot Single-Capture

Only one capture pulse is needed under one capture window, so don't worry
about the clock skew between different clock domains, but this method can only
test the structure faults, synchronous and asynchronous clock domains of intra-
clock-domain and inter-clock-domain It will be all right.

Synchronous clock here refers to the clock that is exactly the same as edge, and
asynchronous means that edge does not complete the same clock.

Advantages of doing this:

A single, slow-speed global scan enable (GSE) can be used to drive both clock
domains, so it is convenient for physical implementation.

The disadvantages of doing this are:

Test time will be longer.

Staggered Single-Capture

Capture pulses C1 C2 can test intra-clock-domain and inter-clock-domain

structural faults in the capture window through sequential and staggered order.

In synchronous clock, adjusting d2 can test inter-clock-domain delay.

Advantages: a single slow-speed GSE signal is convenient for physical

implementation.

Disadvantages: The order sequence of some capture clocks may lead to

coverage loss of some structural faults.

Skewed-Load

Skewed-Load is an at-speed delay test, a last shift pulse followed by a capture

pulse.

The values of last shift pulse and next-to-last-shift pulse are different to ensure
the generation of transition, and use this capture pulse to capture output
response

The Scan enable signal must transition from shift mode to capture mode in one
clock cycle.

This method is mainly to solve intra-clock-domain delay fault detection

It is also mainly divided into three approaches to achieve:

1) one-hot skewed-load
2) aligned skewed-load

3) staggered skewed-load

One-hot Skewed-load

The main differences from single-capture:

1) apply shift-followed-by-capture pulses to detect intra-clock-domain delay

faults,

2) Each scan enables signal switch operations from shift to capture within one
clock cycle.

Disadvantages: cannot be used to detect inter-clock-domain delay faults; very

long test time; incompatible with single, slow-speed GSE signal (incompatible)

Aligned skewed-load

Mainly divided into capture aligned skewed-load and launch aligned skewed-
load,

All intra-clock-domain and inter-clock-domain faults can be tested, but all

clocks must have a reference clock, and the frequency of this clock is very high.

And there will be no such a refer clock in the design

Staggered skewed-load

Similar to single-capture, a delay d3 will be inserted between two capture cycles

to eliminate the clock skew between two clock domains.

This design can also test all intra-clock-domain and inter-clock-domain

structural faults

The disadvantage is also that the physical implementation of the scan enable
signal is too difficult.

Double-capture technology is another at-speed test technology. It is a true at-

speed test that can test all intra-clock-domain and inter-clock-domain structural
faults and delay faults, whether in synchronous Or asynchronous design. And
scan enable is relatively easy for physical implementation, and scan/ATPG is
also easy to implement.
Also divided into three implementations

1) one-hot double-capture

Only one clock is tested at a time, which can realize the delay fault of the intra-
clock-domain of the synchronous/asynchronous clock domain.

The main differences:

    1) Two capture clocks to test intra-clock-domain delay faults;

    2) A single, slow-speed GSE signal is convenient for physical

implementation;

shortcoming:

Inter-clock-domain delay faults cannot be tested, and there must be a long test
time.

2) Aligned Double-Capture

Can test all intra-clock-domain and inter-clock-domain faults,

The main differences are:

   1) Two capture clock cycles instead of one shift-followed-by-capture pulse

   2) A single, slow-speed GSE is required for physical implementation

shortcoming:

Precise control of the capture pulse is still required.

3) Staggered Double-Capture

All intra-clock-domain and inter-clock-domain faults can be tested, and physical

implementation of SCAN_ENABLE is facilitated.

Scan design and logic bist are two of the most important structure offline test
techniques to improve production quality.

However, with the complexity of the process, 100% single-stuck fault coverage
can also guarantee perfect production quality.
The remaining faults include: timing-independent (due to increasing resistance
on the connection) and non-single-stuck-at faults, non-feedback bridging faults.

Relatively speaking, intra-clock-domain faults are easy to detect, and inter-

clock-domain delay fault testing is more complicated.

D must be set more accurately to detect inter-clock-domain faults

For the three major parts of the chip, our DFT engineers have three magic
weapons

BSCAN technology -- test IO pad, the main implementation tools are Mentor-
BSDArchit, sysnopsy-BSD Compiler

MBIST technology--test mem, the main implementation tools are Mentor's

MBISTArchitect and Tessent mbist

ATPG technology -- testing std-logic, the main implementation tools are:

TestKompress and synopsys TetraMAX of Mentor to generate ATPG;

                  Inserting scan chain mainly uses RTL Compiler of DFT

compiler/cadence of synopsys

Mentor's tools updated to the Tessent platform, including tools: Tessent Fast
Scan Tessent MemoryBIST Tessent test Kompress Tessent Scan Tessent
Diagnosis

                                                             
 

Insert scan:

1. Although textbooks will introduce many kinds of DFT DRC, in actual design,
95% of the work is to fix the DRC violation of scan_clk and scan_reset

2. The method of repairing clk/reset violation is mainly to use DC to insert mux,

the purpose is to make clk and reset controlled by chip scan_clk and scan_reset
pad in scan_mode.

            At the same time, scan_clk and scan_reset pad will be used for ATE to
apply excitation to the chip

3. When inserting scan, DFT Compiler must fix DRC violations category
D1/D2/D3/D9

4. When doing full-chip DFT design, you need to insert mux at the
OEN/IE/REN end of the IO pad of scan_in, scan_out, scan_reset, scan_clk to
control the input and output directions of the pad

Atpg patterns generation and simulation

1. All analog modules, such as PLL, POR, etc., are generally set as black-box,
and cannot be tested with ATPG

2. The control registers of the chip clk, power and reset are generally not placed
on the scan_chain, so as not to change the working state of the chip due to the
action of the registers during the test

3. Considering the switch of the power domain, it is generally necessary to

ensure that all power domains are turned on during the scan test, and each
digital standard unit can be tested.

4. If there are analog IO pads, they must be masked off when the pattern is
generated, because they are not digital, and the ATPG tool cannot control them

5. The industry generally uses DC to insert OCC (on chip clocking) module to
realize at-speed scan test circuit

The flow of scan operation:

1) Enable scan mode;

2) Turn on the scan clock and input stimulus;

3) Compare the output, and then turn off the scan clock to input the next
stimulus.

The scan operation can be divided into full scan and partial scan. Full scan has
the highest coverage and ATPG is easy to generate, but it is not friendly to area
and timing.

Partition Scan: For large-scale designs, scan design is performed from the block
level, adding scan input/output/enable

Test Points: For some points that are difficult to observe and control, additional
mux is added for control.

  For example, the output of the OR gate has a 1 input, and the other input is
difficult to observe, and the subsequent logic is difficult to control.

   At this point, a mux, an input and an output can be added after the OR gate to
ensure coverage. (See the album for the routine)

ATPG (Automatic Test Pattern Generation), Test patterns is also called test
vector.

There are two kinds of random pattern and Deterministic pattern, but most of
them use random, which consists of two parts:

1) Generation patterns;

2) Complete the fault simulation;

Test Type: divided into three categories:

1) Functional test, mainly for static defects, (open, short, stuck-on, stuck-open)

2) IDDQ, test static power consumption current. The analysis was performed

with the Pseudo stuck-at model.

For a Full static CMOS circuit, IDDQ is close to zero, pull-up and pull-down,
the IDDQ of the tri-state bus is higher,
High IDDQ is also generated in dynamic memory such as RAM.

3) At-Speed test: mainly analyzes transaction, path delay. Such as slow-to-rise,

slow-to-fall.

All of the above are single fault models, and fault collapsing may also occur.

Terminology in scan:

Scan Cells: A scan cell contains at least one memory element (FF or latch) in a
scan chain.

Master Element: The scan cell that gets the data directly from the previous scan
cell and is directly connected to the scan input.

Slave Element: The scan cell of the same clock in the scan chain.

Shadow Element: FF or latch outside the scan chain.

Copy Element: A scan cell that has the same or opposite data as the upper and
lower scan cells.

Extra Element: Any element between the master element and the slave element.

Scan chain: A series of connected scan cells, including an input, output,

enable. The scan cell number 0 near the output.

Scan Groups: A series of scan chains (with their own input and output) that can
be processed in parallel.

Scan Clocks: Clock signals for scan operations, including reset and set signals.