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Project Sims

This document contains summaries of issues that can occur during timing simulations and recommendations on how to address them. It discusses how testers only have access to scan inputs and outputs, so any functional pads need to be specified. It also explains how clock delays can cause pattern misalignment and recommends editing the test procedure file to account for the delays. The document then provides recommendations to avoid false paths by checking the SDC file, set the sequential depth correctly to avoid coverage issues, manually insert a MUX if an uncontrollable clock is detected, and add input constraints to prevent a clock signal from reaching both the clock and D input of a flop.

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Naga Nithesh
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156 views2 pages

Project Sims

This document contains summaries of issues that can occur during timing simulations and recommendations on how to address them. It discusses how testers only have access to scan inputs and outputs, so any functional pads need to be specified. It also explains how clock delays can cause pattern misalignment and recommends editing the test procedure file to account for the delays. The document then provides recommendations to avoid false paths by checking the SDC file, set the sequential depth correctly to avoid coverage issues, manually insert a MUX if an uncontrollable clock is detected, and add input constraints to prevent a clock signal from reaching both the clock and D input of a flop.

Uploaded by

Naga Nithesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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No Timing Simulations:

• Tester has access to only scan inputs and scan outputs…. Not functional
pads. So if you did not mention functional pad with
add_input_constraints -cz command…..while doing ATPG.. patterns
would be generated by considering this functional pad as well. But at the
tester testing, it gets failed because tester has no access to this func pad. So
you have give that above command in advance.
• Clock is defined at that top level generally. During parallel patterns, data
is forced on SI pin.. In our test proc file, under time plate, 1 period = 20ns
[ at 10ns---pos edge and at 20 ns neg edge]. But due to clock delay of 4ns
the pos edge instead of coming at 10ns moved to 14ns and neg edge moved
to 24ns.. So, we edited the test proc file, we brought that to some 4ns before
for correct shifting and capture operations.

DRCS:

• Try to avoid false paths--- to do that Read SDC file and check for false
paths and delete them and again run the design
• Sequential depth ---- if Seq depth is not given correctly we may face
coverage issues… so give the command analyse-→
optimal_sequential_depth and set_pattern_cycle 4/5/6….required no.
of non-scan flop cells count.
• Uncontrollable clock---- manually insert the MUX and give the clock to
one of the pins… so that clock would be propagated to all the flops which
are gated earlier.
• Clk signal goes to both clk and D input of the flop… because of this race
conditions would come..so, prevent this by add_input_constraints C0
SC_EN

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