HETT406: Design of

Digital & VLSI Systems

Unit 2: CMOS Logic, fabrication and layout

Prof E Mashonjowa
Unit 2

§ 2.1 Introduction
§ 2.2 MOS Principle
§ 2.3 MOSFET operation
§ 2.4 MOSFET as Switch
§ 2.5 CMOS Technology
§ 2.6 CMOS Inverter
§ 2.7 CMOS NAND Gate
§ 2.8 CMOS NOR Gate
§ 2.9 Compound Gates
§ 2.10 CMOS Fabrication and layout
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2.1: Introduction (1)
n Metal-Oxide-Semiconductor (MOS) structure is created
by superimposing several layers of conducting and
insulating materials to form a sandwich- like structure.
n These structures are manufactured using a series of
chemical processing steps involving oxidation of the
silicon, selective introduction of dopants, and deposition
and etching of metal wires and contacts.
n CMOS technology provides two types of transistors:
q an n-type transistor (nMOS) and
q a p-type transistor (pMOS).

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 2.1 Introduction (2)

An nMOS transistor is built with a p- A pMOS consists of an n-type

type body and has regions of n-type body and p-type source and
semiconductor adjacent to the gate drain regions.
called the source and drain

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2.1 Introduction (3)

n Each transistor consists of a stack of the conducting

gate, an insulating layer of silicon dioxide (SiO2), and
the silicon wafer, also called the substrate (or body, or
bulk).
n In a CMOS technology, the substrate is either n-type
or p-type.
n Transistor operation is controlled by electric fields so
the devices are also called Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs)

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2.1 Introduction (4)

nMOS & pMOS transistor symbols used in CMOS circuits

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 2.2 MOS Principle

n The gate is a control input: It affects the flow of electrical

current between the source and drain.

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 2.3 MOSFET operation (1)
n Consider an nMOS transistor.

n The body is generally

grounded so that the p–n
junctions of the source and
drain to body are reverse-
biased.
n If the gate is also grounded, no
current flows through the
reverse-biased junctions.
n Hence, we say the transistor is
OFF.

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 2.3 MOSFET operation (2)
n Now consider the Bulk, the Source and
the Drain grounded, while a positive VGS
is applied to the Gate, as
n The Gate and the substrate form a
capacitor with the silicon dioxide as
dielectric.
n Positive charges are accumulated on the
Gate, while negative charges are
attracted in the substrate.
n Initially, negative charges accumulated in
the substrate are manifested by the
creation of a depletion region under the
channel, that excludes holes under the
Gate.
n However, in this conditions, current (a) nMOS transistor with 0 < VGS< VTH
cannot flows between Source and Drain,
and the device is still in cut‐ off region.

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 2.3 MOSFET operation (3)
n If the gate voltage is raised so that
VGS reaches a critical value called
threshold voltage, VTH, it creates
an electric field that starts to attract
free electrons to the underside of
the Si – SiO2 interface.
n If the voltage is raised enough, the
electrons outnumber the holes and
a thin region under the gate called
the channel is inverted to act as an
n- type semiconductor.
n Hence, a conducting path of
electron carriers is formed from (b) nMOS transistor with VGS > VTH & VDS>0
source to drain and current can
flow.
n We say the transistor is ON.

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2.3 MOSFET operation (4)

The IDS‐ VGS input characteristic of the NMOS

transistor in saturation region. The IDS‐ VGS curve fits
the square law, and it meets the VGS axis at VTH.

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 2.3 MOSFET operation (5)

The ideal IDS‐ VDS output

characteristics with VGS as
parameter

L and W are the channel length and width, respectively, Cox is the Gate
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capacitance per unit area and μn is the electron mobility in the channel.
 2.3 MOSFET operation (6):
P-channel MOSFET (1)
n For a pMOS transistor, the body is held at a positive voltage.

n When the gate is also at a positive voltage, the source and

drain junctions are reverse-biased and no current flows, so
the transistor is OFF.
n When the gate voltage is lowered, positive charges are
attracted to the underside of the Si – SiO2 interface.
n A sufficiently low gate voltage inverts the channel and a
conducting path of positive carriers is formed from source to
drain, so the transistor is ON.

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2.3 MOSFET operation (7):
P-channel MOSFET (2)

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2.3 MOSFET operation (8):
Power Supply Voltage

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 2.4 MOSFET as Switch (1)

n The gate of an MOS transistor controls the flow of current

between the source and drain
n Simplifying this to the extreme allows the MOS transistors
to be viewed as simple ON/OFF switches.
n When the gate of an nMOS transistor is 1, the transistor is
ON and there is a conducting path from source to drain.
n When the gate is low, the nMOS transistor is OFF and
almost zero current flows from source to drain.
n A pMOS transistor is just the opposite, being ON when the
gate is low and OFF when the gate is high.

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2.4 MOSFET as Switch (2)

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 2.5 CMOS Technology
n Complementary Metal Oxide Semiconductor (or CMOS) is a
combination of NMOS and PMOS transistors.
n The importance of CMOS in semiconductor technology is its
low power dissipation and low operating currents.
n Compared with Transistor-Transistor Logic (TTL) technology,
CMOS technology has the advantages of temperature stability,
stronger anti-noise ability and lower power consumption.
q TTL logic IC’s use NPN and PNP type BJTs while CMOS logic
IC’s use complementary MOSFET or JFET for both their input
and output circuitry.
n CMOS is more conducive to large-scale integration.
n CMOS technology has a huge advantage in cost compared
with Emitter Coupled Logic (ECL) technology.

(In ECL ICs each gate continuously draws current,

which means that it requires much more power). 18
 2.6 CMOS Inverter

When the input A is 1, the nMOS When the input A is 0, the nMOS transistor
transistor is ON, the pMOS transistor is is OFF and the pMOS transistor is ON.
OFF. Thus the output Y is pulled down to Thus, the output Y is pulled up to 1
‘0’ because it is connected to GND but because it is connected to VDD but not to
not to VDD. GND.

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2.7 CMOS NAND Gate (1)

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2.7 CMOS NAND Gate (2)

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 2.7 CMOS NAND Gate (3): Logic Structure
§ In general, a static CMOS gate has:
• an nMOS pull-down network to connect the
output to 0 (GND)
• a pMOS pull-up network to connect the
output to 1 (VDD)
§ When we join a pull-up network to a puu-down
network to form a logic gate, they both will
attempt to exert a logic level at the output
§ The networks are arranged such that one is
ON & the other OFF for any input combination

CMOS NAND Gate

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2.7 CMOS NAND Gate (4):
3 input NAND Gate?

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2.8 CMOS NOR Gate (1)

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2.8 CMOS NOR Gate (2):

3 input NOR Gate?

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2.9 Compound Gates (1)

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2.9 Compound Gates (2)

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2.9 Compound Gates (3)

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Assignment 1
Draw the minimum CMOS transistor network that
implements the functionality of the following Boolean
equations
a) F= ((A+B) C + D)'
b) F= (A (B C + D))'
c) F= (A +(B' + CD)')'
d) F= (A' + B'C)
You can assume both the original and complemented versions
of each literal are available as gate inputs. Show working

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2. 10 CMOS Fabrication and Layout

pMOS
nMOS
 The Fabrication Process
§ The fabrication process § The first processing step is
consists of a series of steps that of oxidation (allows for
in which layers of the chip protection of regions that need
are defined through the not be doped).
photolithography process. § Form an n-well using a Group
§ Inverter can be described V element (this changes
as having six masks substrate from p-type to n-type
namely: to accommodate the pMOS).
n-well
q
§ Region devoid of the SiO2 get
Polysilicon
q
doped.
q n+ diffusion
§ Dopants can be introduced
q p+ diffusion
into the wafer by diffusion or
q Contacts and metal
ion implantation.
 Layout Design Rules
§ Layout design rules describe § Lambda (l) is generally half of
device dimensions and how the minimum drawn transistor
close different and like layers channel length.
can be brought to close
§ The channel length describes
proximity without creating
the distance between the
shorts.
inside edges of the source and
§ The lambda based design drain.
rules made popular by Mead
§ It is set by the minimum poly
and Conway are based on the
width.
single parameter l and permit
for ease of scaling. § We are begin to refer to the
gate channel length in
§ Industry used micron as a unit
nanometers (nm) whereas for
of measure and this makes
technologies 0.18 mm and
scaling difficult since not all
above we used the micron.
dimensions do not scale
uniformly.
 Layout Design Rules
§ Lambda rules allow for ease § These rules cover a wide range
of migrating designs from of manufacturing processes.
one technology node to § The rules define minimum wire
another. widths to avoid breaks,
§ Our Cad Tools in the Lab minimum spacing to avoid
shorts between neighboring
measure in micron.
wires and minimum overlap to
§ Academia relies on MOSIS minimize parasitic capacitance.
(fabrication house (foundry)) § Contacts have traditionally been
to fabricate their designs. kept at 2l × 2l for different
§ MOSIS provides a technology generations.
comprehensive summary of § Polysilicon has a minimum
scalable CMOS (SCMOS) width of 2l and must overlap
rules at http://www.mosis.org diffusion by 2l and must be 1l
away from the next poly wire.
 Gate Layout
VDD
§ To lesson the possibility
of having layers of the
same material creating
short circuits, it is best
to have same layers
oriented in the same
direction (metal1 placed
horizontally while poly
runs vertically). GND