2014 IEEE 32nd VLSI Test Symposium (VTS)

!
Fault
!
Modeling andd Test Algorithm Creatio
on Strategy
for FinnFET-Based Memories
G. Harutyunnyan, G. Tshagharyan, V. Vardanian, Y. Zorian
Synopsys
{gurgen.harutyunyan, grigor.tshagharyan, valery.vardanian, yervant.zorian}@
@synopsys.com

Abstract—FinFET transistors are playing an iimportant role in Due to their spatial structure, FinFETs have plenty of other
modern technology that is rapidly growing. Em mbedded memories advantages, besides the mentioned d ones, over conventional
based on FinFET transistors lead to new defectss that can require transistors like controlled Fin body thickness, low threshold
new embedded test and repair solution. To invvestigate FinFET- voltage variation with scaling, red duced variability caused by
specific faults the existing models and detectioon techniques are random dopant fluctuations and lower operating voltage.
not enough due to a special structure of FinFETT transistors. This However, the design of layout and manufacturing
m of such kind
paper presents a new strategy for investigaation of FinFET- of 3D transistors is related to varietty of challenges as existing
specific faults. In addition to fault modeling, a new method is techniques for conventional transisttors may not work and fresh
proposed for test algorithm synthesis. The propoosed methodology
approaches may be required [10]. In spite of the fact that
is validated on several real FinFET-based em mbedded memory
technologies. Moreover, new faults are identified
d that are specific
FinFET technology has not been yet completely studied, a
only to FinFETs. number of leading IC manufacturiing companies has already
announced the production of devicees with FinFET transistors,
Keywords- FinFET, defect, fault model, test alggorithm, embedded e.g. Samsung has started with pro oduction of 14nm FinFET
memory memories, Intel with 22nm and TC CMS with 16nm memories
[11]-[13].
I. INTRODUCTION
With production of FinFET-baased memories (memories
Due to growing leakage and short-channnel problems of using FinFET transistors), the problem of test and repair of
conventional planar MOSFET transistors, it iis not possible to such kind of memories is included in the agenda as the same
continue with Moore’s Law by further sccaling down the
feature sizes of these planar transistors. FinnFET transistors
have been introduced as an alternative sollution to further
shrink the technology. The term FinFET wass first mentioned
as early as in 1999 in [1] to describe the noon-planar double-
gate transistor, which was demonstrated as a possible
replacement for conventional planar tecchnology. Later
FinFETs were used in many publicatioons to describe
transistors built with new non-planar multi-gate architecture
(see [2]-[7]). The distinguishing characteriistic of FinFET
transistor is that conducting channel consistss of thin vertical
silicon “Fins” that are wrapped around by gatee electrodes. This
leads to better control of channel and beetter electrostatic
properties as leakage current is diminished in the off state and
short channel effects are reduced.
Depending on the structure of the gate, twwo main types of
FinFETs can be distinguished: tied-gate (TG)) or, as it is also
called, shorted-gate (SG) and independent-ggate (IG) [8]-[9].
For TG FinFETs, there is only one gate whichh covers the Fins
from 3 sides (see Fig. 1a). For IG FinFETs, thhere are two gates
on front and back sides of the Fins whichh are controlled
separately (see Fig. 1b). The most im mportant FinFET
parameters are its height (HFin), its width orr body thickness
(TFin) and its channel length (Lg). The efffective electrical
width of a FinFET is TFin+2HFin, whereTFin hass a fixed size and
in order to increase Fin width, the only way iis to use multiple
Fins.
Figure 1. FinFET structures

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fault models and test algorithms used ffor conventional memories from different foundries, and several new faults are
memories may not cover the whole aspect off possible defects identified that are specific only to FinFETs.
!
in FinFET-based memories. Despite the im mportance of the
This paper is organized as folllows. Section II gives an
problem, relatively few number of research studies have been
overview on types of defects in FinFETs. In Section III, a new
conducted in this area during the recent yeears. In [14] and
strategy for FinFET-specific fault modeling
m and test algorithm
[15], the authors have investigated different tyypes of open and synthesis is presented. Experimeental results obtained by
short defects in FinFET logic circuits. They sshowed that even SPICE simulations are presented d in Section IV. Finally,
though most of the opens and shorts have theeir corresponding Section V presents the conclusions.
fault models in planar technology, an open deefect on the back
gate for IG FinFET causes delay and leakage problems unique
to FinFETs. The same problem arises whenn TG FinFET is
accidentally etched into IG structures. II. N FINFETS
DEFECTS IN
We investigate both TG and IG FinFETs while our SPICE
In [16], the authors examined stuck-open faults (SOF) for
simulations are done only on TG FinFETs.
F The reason is that
small nanometer technologies, including FinF FET, and showed
most of the leading IC manufactturing companies produce
that the hold time for SOFs decreases signnificantly due to
mainly TG FinFETs (e.g., [11], [122]) and that can be a reason
increased sub-threshold leakage and gate leakkage making the
of the fact that current set of FinFET-based memories
fault detection more difficult. To improve the SOF detection, a
available to us are all TG-based. Anyway,
A the same class of
test vector strategy was proposed trying too produce lower
defects can be considered also for IG FinFETs, but for us at
values at the transistor drain-source voltagees of the fan-out
the moment there is no IG-based d memory to simulate the
gates. The problem of testing SOF faults in small nanometer
mentioned defects. Fig. 2 show ws the defects which are
technologies is also discussed in [17] and two new vector
considered for TG FinFET. These defects
d are:
strategies were proposed to increase thee possibility of
detection of SOF defects. (a) Fin Open – Full and resistivee open defects on Fin;
In [8], the authors examine stuck-open, sttuck-on and gate (b) Gate Open – Full and resistiv
ve open defects on Gate;
oxide short defects on different number of Fins within one
FinFET transistor. According to the results, w when the number (c) Fin Stuck-On – Full and resistive short defects between
of defective Fins is relatively small in propportion, then the Source and Drain;
transistor can be treated as fault-free. Otherwiise, if the number
is large enough, the defect can be modeled wiith stuck-open or
delay faults. The authors also have investigateed the case when
a single defect, such as a back gate open or Fin stuck-on,
affects multiple gates in IG FinFETs. Thiss type of defect
brings to a delay fault, which cannot bee detected with
traditional delay tests and new test mechanism ms are necessary.
In [9], the authors investigate Gate Oxide S Shorts (GOS) in
FinFETs. According to the authors, GOS defects in FinFET-
based memories lead to a more complex fault behavior than in (a) (b)
the case of planar-based memories (memorries using planar
transistors), so traditional test algorithms faill to detect them.
For this purpose, two new test techniques werre introduced for
each of IG and TG types of FinFETs in ordeer to detect GOS
defects.
Most of the discussed papers show that tthe existing fault
models are not sufficient to model all possiblee types of defects
in FinFETs. Each of them concentrates on a specific class of
defects considering possible testing solutionss but, to the best (c) (d))
of our knowledge, there is no any comprehhensive study of
FinFET-specific defects and generic test soolution for their
detection. (aa) – Fin Open
(b
b) – Gate Open
In this paper, a new strategy for investigaation of FinFET-
specific faults is proposed. According to thaat, an automated (cc) – Fin Stuck-On
flow is developed for SPICE simulation of FinFET-specific (d
d) – Gate-Fin Short
defects that are injected into memory layouut or in memory (ee) – Process Variation
spice net-list. Based on simulation results, ffault models and
their corresponding detection test sequences aare identified. At (e)
the final step, a test algorithm is constructed for selected (one
or multiple) FinFET-specific defects. The proposed Figure 2. Defects in FinFETs
methodology is validated on real FinFET-bbased embedded

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 !

(d) Gate-Fin Short – Full and resistive short defects Start

between Gate and Fin; Defect
! Defect-free Defect injected
(e) Process Variation – Variations in FinFET parameter branch Memory branch LIB
values. Layout Defect

In addition to the defects described in Fig. 2, other types of Defect Injection

defects that are typical to planar-based memories should be into GDS
considered in FinFET-based memories as well. The most
important classes of such defects are resistive/full shorts and SPICE Net-list SPICE Net-list
opens placed on/between memory bit-lines, word-lines and Extraction Extraction
memory cell internal nodes, as well as defects of the
surrounding blocks of memory array, such as address decoder,
SPICE Simulation SPICE
write driver and sense amplifier.
Simulation Setup Simulation

Update
Setup
III. FAULT MODELING AND TEST ALGORITHM SYNTHESIS
Since FinFET-based memories may contain new faults that Compare
are specific only to FinFETs, the existing test solutions Waveforms
(consisting of various types of test operations, addressing
methods, background patterns and other stressing conditions)
may be insufficient for investigation of those faults. Thus, the Test Sequence
known techniques, such as running SPICE simulations with Fault Model
predefined set of test algorithms may fail to detect FinFET-
specific faults. This is the main reason that we created a new Figure 3. Test Sequence Identification
methodology for investigation of FinFET-specific faults and and Fault Modeling Flow
that helped us to model new faults which were not detected by
the existing known techniques. Figure 3 shows an automated
Table [18] that helps us to find appropriate Test Sequences
flow for finding appropriate test sequences for detection of
using a systematic approach instead of guessing Test
defects, as well as for constructing the corresponding fault
Sequences which, in some sense, can lead to multiple useless
models. The flow consists of the following steps:
and endless iterations.
1. A defect can be injected either in GDS or in SPICE Net-
4. The iteration mentioned in Step 3 should be repeated
list. In some cases it is worthy or convenient to inject a defect
until finding a satisfactory Test Sequence. If a Test Sequence
into GDS and for other cases SPICE Net-list is more
is found, then the corresponding Fault Model is automatically
preferable. Thus, two choices are provided for defect injection.
extracted from the Test Sequence. For example, if detecting
The defects are injected from Defect LIB which is enriched
Test Sequence = {W0, R0, R0} and only the second R0
periodically based on new technological structures, such as
detects the fault then DRDF0 = <0R0/1/0> fault [19] is
FinFETs. At the moment, it includes all defect models
extracted.
described in Fig. 2.
When fault models and the corresponding test sequences
2. Two SPICE Simulations (defect-free and defect
are identified the next step is to construct a test algorithm for
injected) are run with specific Simulation Setup which can
detection of a given set of faults. There are several tools for
contain a set of different test sequences, different PVT
test algorithm generation (e.g., [20]-[21]) that take as an input
(frequency, voltage, temperature) conditions, if a resistive
a set of faults and generate a satisfactory test algorithm. In
defect is injected then the range of resistance magnitude, etc.
most of the cases they require to be enhanced each time when
Based on the setup if multiple simulations are needed, then all
new types of faults appear (such as FinFET-specific faults). It
simulations are performed automatically and for each
means that test algorithm generation tool strongly depends on
simulation PASS/FAIL information and Waveforms of applied
the set of faults that currently are known by the tool. In order
test operations are provided.
to make the tool independent of the fault type, it is decided to
3. If FAIL is obtained for defective SPICE Net-list then it take as an input not a set of faults, but a set of Test Sequences.
means that current Simulation Setup and therefore at least one The advantage of this is that the flow becomes more generic
of the used Test Sequences is satisfactory to detect the injected since there is no dependency on fault types. Also, since per the
defect. Otherwise, if PASS is obtained for all simulations flow described in Fig. 3, Test Sequence is identified by the
meaning that the defect is not detected then comparison of simulation while Fault Model is obtained based on Test
Waveforms for defect-free and defect injected cases should be Sequence it is more efficient to use the direct output (Test
done. Based on comparisons new test sequences should be Sequence) in Test Algorithm Synthesis Flow (see Fig. 4)
provided which can be candidates to detect the defect. This instead of using Fault Model that is derived from Test
part is done by the user (test engineer or someone else) Sequence. In Fig. 4, Test Algorithm Generator synthesizes
following some special rules to construct new Test Sequences. optimal Test Algorithms. Moreover, our experiments show
For example, for this purpose we frequently use Fault Periodic that if the given Test Sequences have minimal lengths in terms

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 !

of detecting the given defects/fault models, then Test dDRDF0-7 = <0R07/1/0>. This fault is observed for resistance
Algorithm Generator will synthesize minimal test algorithms. values 10-25MΩ. Since there is no Fin in planar-based
! memories and therefore Fin Open defect cannot be injected, in
planar-based memories Channel open defect is examined to
Test Test Test
... have closer behavior to Fin Open defect. A simulation showed
Sequence 1 Sequence 2 Sequence K
that in this case only static fault behavior is observed for all
resistance values from [0;∞] range.

Test Algorithm Flip

Generator

Test Algorithm

Figure 4. Test Algorithm Synthesis Flow

IV. EXPERIMENTAL RESULTS W0 R0 R0 R0 R0 R0 R0 R0 R0

Based on the defects described in Section II and using fault
modeling and test algorithm synthesis flows described in Figure 5. Resistive Fin Open defect in PD transistor
Section III we have performed a massive run of SPICE results in dDRDF fault
simulations on several FinFET-based memories from different
foundries. Each defect is injected into pass-gate (PG), pull- Fig. 6 shows the result of the case when a resistive Gate
down (PD) and pull-up (PU) transistors one at a time and also Open defect is injected into a pass-gate transistor of a FinFET-
multiple defects are injected simultaneously in the same based memory cell. It results in a well-known transition fault
memory cell. In parallel to this activity the same defects were i.e., Test Sequence = {W1, W0, R0} or {W1, W0, W0, R0}
injected into planar 28nm and 45nm memories to compare the and the corresponding fault model is transition fault TF0 =
obtained results. The experiments showed that: <1W0/1/->. This fault is observed for resistance values ≥5MΩ.
The same results are obtained when the defect is injected into
1. FinFET-based memories are more prone to dynamic planar-based memories. Similar results are obtained also for
faults than planar-based memories. Dynamic faults the cases when Gate Open defect is injected into pull-down
are observed when special types of defects are and pull-up transistors, thus we can consider that Gate Open
injected into FinFET-based memories while for the defects do not lead to FinFET-specific faults.
same defects in planar-based memories only static
fault behavior is observed.
2. FinFET-based memories are more stable to process
variation faults. Changes in transistor parameter sizes
(up to 50%) do not lead to any fault in FinFET-based
memories while 20%-40% parameter size change in
planar-based memories led to different types of faults Fail to Write 0
[22].
3. Static single-cell and coupling faults are typical for
both FinFET- and planar-based memories. Some
defects resulting in static faults (either single-cell or
coupling) are injected and similar behavior is
observed in bothFinFET- and planar-based memories. W0 W1 W0 R0 W1 W0 W0 R0
The below figures show some of the results obtained by
running SPICE simulations done on FinFET-based memories. Figure 6. Gate Open defect in PG transistor
There are different types of defects injected in different places results in TF fault
in the memories using different PVT corners.
Fig. 7 shows the result in the case when a resistive Fin
Fig. 5 shows the simulation output for the case when a Stuck-On defect is injected into a pull-down transistor of a
resistive Fin Open defect is injected into a pull-down transistor FinFET-based memory cell. It results in four-operation
of a FinFET-based memory cell. It results in seven-operation dynamic Deceptive Read Destructive Fault dDRDF1-4 where
dynamic Deceptive Read Destructive Fault dDRDF0 [23] the 4th R1 operation is flipping the content of the cell without
where the 7th R0 operation is flipping the content of the cell reporting a mismatch while the 5th R1 operation detects the
without reporting a mismatch while the 8th R0 operation fault. So the optimized Test Sequence = {W1, R1, R1, R1, R1,
detects the fault. So Test Sequence = {W0, R0, R0, R0, R0, R1} and the corresponding fault model is dDRDF1-4 =
R0, R0, R0, R0} and the corresponding fault model is <1R14/0/1>. This fault is observed for resistance values 120-

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 !

130KΩ. Here it is shown that in some cases the satisfactory The above mentioned cases are just some examples of a
Test Sequence can contain redundant test operations and those huge number (more than 1000) of SPICE simulations done on
should! be eliminated while reporting Test Sequence or different types of FinFET- and plannar-based memories from
extracting the corresponding Fault Model. In this case first two different foundries. In addition to FinFET-specific defects, the
operations (W0 and first W1) can be removed. Again, since other types of defects that are typical to planar-based
there are no Fins in planar-based memories for comparison of memories are injected into FinFET-based memories and in
the results Channel Stuck-On defect is injected into planar- most cases the same/similar results are obtained as in the case
based memories. As a result, only static fault behavior is when the defect is injected into planar-based memory. Most of
observed for all resistance values from [0;∞] range. those defects led to static single-cell and static coupling faults.
At the beginning of this section we have already stated
three major conlusions that are based on the simulation results.
In addition to that some intersting facts are outlined below:
Flip
• Defects injected in pull-up transistors of FinFET- and
planar-based memories in most of the cases give the
same results.
• dDRDF is observed mainly in pull-down and linked
fault TF*IRF in pass-gate transistors of a FinFET-
based memory. These faults are not watched in planar-
based memories. Though papers [25]-[26] state that
W0 W1 W1 R1 R1 R1 R1 R1 dDRDF faults were obtained for 0.13um memories, it
was not observed in 28nm and 45nm memories.
Figure 7. Fin Stuck-On defect in PD transistor • Gate open defects in FinFET-based memories do not
results in dDRDF fault lead to FinFET-specific faults.
• PVT conditions (frequency, voltage, temperature) are
Fig. 8 shows the result in the case when a resistive Gate- playing important role for defect detection since for a
Fin Short defect is injected into a pass-gate transistor of a given range of a resistive defect nominal PVT
memory cell. It results in linked fault TF1 = <0W1/0/-> * IRF condition may not reveal the defect while running the
= <xRx/0/1>, x ∈ {0, 1}, where IRF stands for Incorrect Read same Test Sequence with corner PVT (e.g., high
Fault (see [19], [24]). It means that W1 operation fails to write frequency, low voltage, high temperature) will result
value 1 to a faulty cell when the initial value of the cell is 0. in detecting the defect.
Next, R1 operation returns correct value due to an IRF fault
which means that fault is masked at this point. Then by
applying R0 operation the fault is detected. So here more than V. CONCLUSIONS
one Test Sequences are used in order to extract a correct fault In this paper a new strategy is proposed for modeling
model though for detection only one Test Sequence is enough. FinFET-specific faults and synthesizing test algorithms for
For such cases, if there is a doubt that a fault is linked or some their detection. The proposed solution is applied for various
other complex fault, additional module in the flow is enabled types of real FinFET-based embedded memories from
to consider more than one Test Sequences for fault model different foundries and several new fault types are identified
extraction. This fault is observed for resistance values ≤ that are specific to FinFETs.
17KΩ. In planar-based memories Gate-Channel Short defect is
Our experiments showed that FinFET-based memories
injected and only TF1 = <0W1/0/-> fault is observed for all
compared with planar-based memories are more prone to
resistance values from [0;∞] range.
dynamic faults and are more stable to process variation faults.
Also it is shown that static single-cell faults and static
Returns 1 Returns 1 coupling faults are typical for both FinFET- and planar-based
Fail to memories.
due to IRF due to IRF
Write 1
In coming works, we are going to summarize and classify
FinFET-specific faults, as well as to develop efficient test
algorithms for their detection.

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