Kintex UltraScale+ FPGAs Data Sheet:

DC and AC Switching Characteristics

DS922 (v1.13) August 1, 2018 Product Specification

Summary
The Xilinx® Kintex® UltraScale+™ FPGAs are available in -3, -2, -1 speed grades, with -3E devices having the
highest performance. The -2LE and -1LI devices can operate at a VCCINT voltage at 0.85V or 0.72V and provide
lower maximum static power. When operated at VCCINT = 0.85V, using -2LE and -1LI devices, the speed
specification for the L devices is the same as the -2I or -1I speed grades. When operated at VCCINT = 0.72V, the
-2LE and -1LI performance and static and dynamic power is reduced.

DC and AC characteristics are specified in extended (E) and industrial (I) temperature ranges. Except the
operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same
for a particular speed grade (that is, the timing characteristics of a -1 speed grade extended device are the same
as for a -1 speed grade industrial device). However, only selected speed grades and/or devices are available in
each temperature range.

All supply voltage and junction temperature specifications are representative of worst-case conditions. The
parameters included are common to popular designs and typical applications.

This data sheet, part of an overall set of documentation on the Kintex UltraScale+ FPGAs, is available on the
Xilinx website at www.xilinx.com/documentation.

DC Characteristics
Absolute Maximum Ratings
Table 1: Absolute Maximum Ratings

Symbol Description1 Min Max Units

FPGA Logic
VCCINT Internal supply voltage –0.500 1.000 V
VCCINT_IO2 Internal supply voltage for the I/O banks –0.500 1.000 V
VCCAUX Auxiliary supply voltage –0.500 2.000 V
VCCBRAM Supply voltage for the block RAM memories –0.500 1.000 V
VCCO Output drivers supply voltage for HD I/O banks –0.500 3.400 V
Output drivers supply voltage for HP I/O banks –0.500 2.000 V

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 1: Absolute Maximum Ratings (cont'd)

Symbol Description1 Min Max Units

VCCAUX_IO3 Auxiliary supply voltage for the I/O banks –0.500 2.000 V
VREF Input reference voltage –0.500 2.000 V
VIN4, 5, 6 I/O input voltage for HD I/O banks –0.550 VCCO + 0.550 V
I/O input voltage for HP I/O banks –0.550 VCCO + 0.550 V
VBATT Key memory battery backup supply –0.500 2.000 V
IDC Available output current at the pad –20 20 mA
IRMS Available RMS output current at the pad –20 20 mA
GTH or GTY Transceiver7
VMGTAVCC Analog supply voltage for transceiver circuits –0.500 1.000 V
VMGTAVTT Analog supply voltage for transceiver termination circuits –0.500 1.300 V
VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for transceivers –0.500 1.900 V
VMGTREFCLK Transceiver reference clock absolute input voltage –0.500 1.300 V
VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the –0.500 1.300 V
transceiver column
VIN Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input –0.500 1.200 V
voltage
IDCIN-FLOAT DC input current for receiver input pins DC coupled RX – 10 mA
termination = floating8
IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX – 10 mA
termination = VMGTAVTT
IDCIN-GND DC input current for receiver input pins DC coupled RX – 0 mA
termination = GND9
IDCIN-PROG DC input current for receiver input pins DC coupled RX – 0 mA
termination = programmable10
IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX – 6 mA
termination = floating
IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX – 6 mA
termination = VMGTAVTT
System Monitor
VCCADC System Monitor supply relative to GNDADC –0.500 2.000 V
VREFP System Monitor reference input relative to GNDADC –0.500 2.000 V
Temperature11
TSTG Storage temperature (ambient) –65 150 °C
TSOL Maximum dry rework soldering temperature – 260 °C
Maximum reflow soldering temperature for SFVB784, FFVA676, and – 250 °C
FFVB676 packages
Maximum reflow soldering temperature for FFVD900, FFVE900, – 245 °C
FFVA1156, FFVE1517, FFVA1760, and FFVE1760 packages

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 1: Absolute Maximum Ratings (cont'd)

Symbol Description1 Min Max Units

Tj Maximum junction temperature – 125 °C
Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not
implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. VCCINT_IO must be connected to VCCBRAM.
3. VCCAUX_IO must be connected to VCCAUX.
4. The lower absolute voltage specification always applies.
5. For I/O operation, see the UltraScale Architecture SelectIO Resources User Guide (UG571)
6. When operating outside of the recommended operating conditions, refer to Table 4 and Table 5 for maximum overshoot and
undershoot specifications.
7. For more information on supported GTH or GTY transceiver terminations see the UltraScale Architecture GTH Transceivers User Guide
(UG576) or UltraScale Architecture GTY Transceivers User Guide (UG578).
8. AC coupled operation is not supported for RX termination = floating.
9. For GTY transceivers, DC coupled operation is not supported for RX termination = GND.
10. DC coupled operation is not supported for RX termination = programmable.
11. For soldering guidelines and thermal considerations, see the UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification
(UG575).

Recommended Operating Conditions

Table 2: Recommended Operating Conditions

Symbol Description1, 2 Min Typ Max Units

FPGA Logic
VCCINT Internal supply voltage 0.825 0.850 0.876 V
For -1LI and -2LE (VCCINT = 0.72V) devices: internal supply voltage 0.698 0.720 0.742 V
For -3E devices: internal supply voltage 0.873 0.900 0.927 V
VCCINT_IO3 Internal supply voltage for the I/O banks 0.825 0.850 0.876 V
For -1LI and -2LE (VCCINT = 0.72V) devices: internal supply voltage 0.825 0.850 0.876 V
for the I/O banks
For -3E devices: internal supply voltage for the I/O banks 0.873 0.900 0.927 V
VCCBRAM Block RAM supply voltage 0.825 0.850 0.876 V
For -3E devices: block RAM supply voltage 0.873 0.900 0.927 V
VCCAUX Auxiliary supply voltage 1.746 1.800 1.854 V
VCCO4, 5 Supply voltage for HD I/O banks 1.140 – 3.400 V
Supply voltage for HP I/O banks 0.950 – 1.900 V
VCCAUX_IO6 Auxiliary I/O supply voltage 1.746 1.800 1.854 V
VIN7 I/O input voltage –0.200 – VCCO + 0.200 V
IIN8 Maximum current through any pin in a powered or unpowered – – 10 mA
bank when forward biasing the clamp diode
VBATT9 Battery voltage 1.000 – 1.890 V
GTH or GTY Transceiver
VMGTAVCC10 Analog supply voltage for the GTH or GTY transceiver 0.873 0.900 0.927 V
VMGTAVTT 10 Analog supply voltage for the GTH or GTY transmitter and 1.164 1.200 1.236 V
receiver termination circuits

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 2: Recommended Operating Conditions (cont'd)

Symbol Description1, 2 Min Typ Max Units

VMGTVCCAUX10 Auxiliary analog QPLL voltage supply for the transceivers 1.746 1.800 1.854 V
VMGTAVTTRCAL 10 Analog supply voltage for the resistor calibration circuit of the 1.164 1.200 1.236 V
GTH or GTY transceiver column
System Monitor
VCCADC System Monitor supply relative to GNDADC 1.746 1.800 1.854 V
VREFP System Monitor externally supplied reference voltage relative to 1.200 1.250 1.300 V
GNDADC
Temperature
Tj11 Junction temperature operating range for extended (E) 0 – 100 °C
temperature devices12
Junction temperature operating range for industrial (I) –40 – 100 °C
temperature devices
Junction temperature operating range for eFUSE programming13 –40 – 125 °C
Notes:

1. All voltages are relative to GND.

2. For the design of the power distribution system consult the UltraScale Architecture PCB Design User Guide (UG583).
3. VCCINT_IO must be connected to VCCBRAM.
4. For VCCO_0, the minimum recommended operating voltage for power on and during configuration is 1.425V. After configuration, data is
retained even if VCCO drops to 0V.
5. Includes VCCO of 1.0V (HP I/O only), 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HD I/O only) at ±5%, and 3.3V (HD I/O only) at +3/–5%.
6. VCCAUX_IO must be connected to VCCAUX.
7. The lower absolute voltage specification always applies.
8. A total of 200 mA per bank should not be exceeded.
9. If battery is not used, connect VBATT to either GND or VCCAUX.
10. Each voltage listed requires filtering as described in the UltraScale Architecture GTH Transceivers User Guide (UG576) or the UltraScale
Architecture GTY Transceivers User Guide (UG578).
11. Xilinx recommends measuring the Tj of a device using the system monitor as described in the UltraScale Architecture System Monitor User
Guide (UG580). The system monitor temperature measurement errors (that are described in Table 78) must be accounted for in your
design. For example, when using the system monitor with an external reference of 1.25V, and when the system monitor reports 97°C,
there is a measurement error ±3°C. A reading of 97°C is considered the maximum adjusted Tj (100°C – 3°C = 97°C).
12. Devices labeled with the speed/temperature grade of -2LE can operate for a limited time at a junction temperature between 100°C and
110°C. Timing parameters adhere to the same speed file at 110°C as they do below 110°C, regardless of operating voltage (nominal
voltage of 0.85V or a low-voltage of 0.72V). Operation up to Tj = 110°C is limited to 1% of the device lifetime and can occur sequentially or
at regular intervals as long as the total time does not exceed 1% of the device lifetime.
13. Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is
active).

DC Characteristics Over Recommended Operating Conditions

Table 3: DC Characteristics Over Recommended Operating Conditions

Symbol Description Min Typ1 Max Units

VDRINT Data retention VCCINT voltage (below which configuration data 0.68 – – V
might be lost)
VDRAUX Data retention VCCAUX voltage (below which configuration data 1.5 – – V
might be lost)
IREF VREF leakage current per pin – – 15 µA
IL Input or output leakage current per pin (sample-tested)2 – – 15 µA

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 3: DC Characteristics Over Recommended Operating Conditions (cont'd)

Symbol Description Min Typ1 Max Units

CIN3 Die input capacitance at the pad (HP I/O) – – 3.1 pF
Die input capacitance at the pad (HD I/O) – – 4.75 pF
IRPU Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V 75 – 190 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 2.5V 50 – 169 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V 60 – 120 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V 30 – 120 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V 10 – 100 µA
IRPD Pad pull-down (when selected) at VIN = 3.3V 60 – 200 µA
Pad pull-down (when selected) at VIN = 1.8V 29 – 120 µA
ICCADCON Analog supply current for the SYSMON circuits in the power-up – – 8 mA
state
ICCADCOFF Analog supply current for the SYSMON circuits in the power-down – – 1.5 mA
state
IBATT4, 5 Battery supply current at VBATT = 1.89V – – 650 nA
Battery supply current at VBATT = 1.20V – – 150 nA
IPFS6 VCCAUX additional supply current during eFUSE programming – – 115 mA
Calibrated programmable on-die termination (DCI) in HP I/O banks7 (measured per JEDEC specification)
R9 Thevenin equivalent resistance of programmable input –10%8 40 +10%8 Ω
termination to VCCO/2 where ODT = RTT_40
Thevenin equivalent resistance of programmable input –10%8 48 +10%8 Ω
termination to VCCO/2 where ODT = RTT_48
Thevenin equivalent resistance of programmable input –10%8 60 +10%8 Ω
termination to VCCO/2 where ODT = RTT_60
Programmable input termination to VCCO where ODT = RTT_40 –10%8 40 +10%8 Ω
Programmable input termination to VCCO where ODT = RTT_48 –10%8 48 +10%8 Ω
Programmable input termination to VCCO where ODT = RTT_60 –10%8 60 +10%8 Ω
Programmable input termination to VCCO where ODT = RTT_120 –10%8 120 +10%8 Ω
Programmable input termination to VCCOwhere ODT = RTT_240 –10%8 240 +10%8 Ω
Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification)
R9 Thevenin equivalent resistance of programmable input –50% 40 +50% Ω
termination to VCCO/2 where ODT = RTT_40
Thevenin equivalent resistance of programmable input –50% 48 +50% Ω
termination to VCCO/2 where ODT = RTT_48
Thevenin equivalent resistance of programmable input –50% 60 +50% Ω
termination to VCCO/2 where ODT = RTT_60
Programmable input termination to VCCO where ODT = RTT_40 –50% 40 +50% Ω
Programmable input termination to VCCO where ODT = RTT_48 –50% 48 +50% Ω
Programmable input termination to VCCO where ODT = RTT_60 –50% 60 +50% Ω
Programmable input termination to VCCO where ODT = RTT_120 –50% 120 +50% Ω
Programmable input termination to VCCO where ODT = RTT_240 –50% 240 +50% Ω
Uncalibrated programmable on-die termination in HD I/O banks (measured per JEDEC specification)
R9 Thevenin equivalent resistance of programmable input –50% 48 +50% Ω
termination to VCCO/2 where ODT = RTT_48
Internal VREF 50% VCCO VCCO x 0.49 VCCO x 0.50 VCCO x 0.51 V
70% VCCO VCCO x 0.69 VCCO x 0.70 VCCO x 0.71 V

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 3: DC Characteristics Over Recommended Operating Conditions (cont'd)

Symbol Description Min Typ1 Max Units

Differential termination Programmable differential termination (TERM_100) for HP I/O –35% 100 +35% Ω
banks
n Temperature diode ideality factor – 1.026 – –
r Temperature diode series resistance – 2 – Ω
Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. For the HP I/O banks with a VCCO of 1.8V and separated VCCO and VCCAUX_IO power supplies, the IL maximum current is 70 µA.
3. This measurement represents the die capacitance at the pad, not including the package.
4. Maximum value specified for worst case process at 25°C.
5. IBATT is measured when the battery-backed RAM (BBRAM) is enabled.
6. Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is
active).
7. VRP resistor tolerance is (240Ω ±1%)
8. If VRP resides at a different bank (DCI cascade), the range increases to ±15%.
9. On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide (UG571).

VIN Maximum Allowed AC Voltage Overshoot and Undershoot

Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HD I/O Banks

AC Voltage Overshoot1 % of UI2 at –40°C to 100°C AC Voltage Undershoot1 % of UI2 at –40°C to 100°C
VCCO + 0.30 100% –0.30 100%
VCCO + 0.35 100% –0.35 90%
VCCO + 0.40 100% –0.40 78%
VCCO + 0.45 100% –0.45 40%
VCCO + 0.50 100% –0.50 24%
VCCO + 0.55 100% –0.55 18.0%
VCCO + 0.60 100% –0.60 13.0%
VCCO + 0.65 100% –0.65 10.8%
VCCO + 0.70 92% –0.70 9.0%
VCCO + 0.75 92% –0.75 7.0%
VCCO + 0.80 92% –0.80 6.0%
VCCO + 0.85 92% –0.85 5.0%
VCCO + 0.90 92% –0.90 4.0%
VCCO + 0.95 92% –0.95 2.5%
Notes:

1. A total of 200 mA per bank should not be exceeded.

2. For UI smaller than 20 µs.

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks

AC Voltage Overshoot1 % of UI2 at –40°C to 100°C AC Voltage Undershoot1 % of UI2 at –40°C to 100°C
VCCO + 0.30 100% –0.30 100%
VCCO + 0.35 100% –0.35 100%
VCCO + 0.40 92% –0.40 92%
VCCO + 0.45 50% –0.45 50%
VCCO + 0.50 20% –0.50 20%
VCCO + 0.55 10% –0.55 10%
VCCO + 0.60 6% –0.60 6%
VCCO + 0.65 2% –0.65 2%
VCCO + 0.70 2% –0.70 2%
Notes:

1. A total of 200 mA per bank should not be exceeded.

2. For UI smaller than 20 µs.

Quiescent Supply Current

Table 6: Typical Quiescent Supply Current

Speed Grade and VCCINT Operating Voltages

Symbol Description1, 2, 3 Device 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
ICCINTQ Quiescent VCCINT supply current XCKU3P 1242 1181 1181 1037 1037 mA
XCKU5P 1242 1181 1181 1037 1037 mA
XCKU9P 1592 1523 1523 1356 1356 mA
XCKU11P 1780 1693 1693 1486 1486 mA
XCKU13P 1950 1864 1864 1658 1658 mA
XCKU15P 2677 2559 2559 2275 2275 mA
ICCINT_IOQ Quiescent VCCINT_IO supply current XCKU3P 61 59 59 59 59 mA
XCKU5P 61 59 59 59 59 mA
XCKU9P 61 59 59 59 59 mA
XCKU11P 120 115 115 115 115 mA
XCKU13P 61 59 59 59 59 mA
XCKU15P 164 158 158 158 158 mA
ICCOQ Quiescent VCCO supply current All devices 1 1 1 1 1 mA
ICCAUXQ Quiescent VCCAUX supply current XCKU3P 153 153 153 153 153 mA
XCKU5P 153 153 153 153 153 mA
XCKU9P 227 227 227 227 227 mA
XCKU11P 255 255 255 255 255 mA
XCKU13P 266 266 266 266 266 mA
XCKU15P 396 396 396 396 396 mA

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 6: Typical Quiescent Supply Current (cont'd)

Speed Grade and VCCINT Operating Voltages

Symbol Description1, 2, 3 Device 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
ICCAUX_IOQ Quiescent VCCAUX_IO supply current XCKU3P 32 32 32 32 32 mA
XCKU5P 32 32 32 32 32 mA
XCKU9P 33 33 33 33 33 mA
XCKU11P 56 56 56 56 56 mA
XCKU13P 33 33 33 33 33 mA
XCKU15P 74 74 74 74 74 mA
ICCBRAMQ Quiescent VCCBRAM supply current XCKU3P 18 17 17 17 17 mA
XCKU5P 18 17 17 17 17 mA
XCKU9P 25 24 24 24 24 mA
XCKU11P 23 22 22 22 22 mA
XCKU13P 29 28 28 28 28 mA
XCKU15P 37 35 35 35 35 mA
Notes:

1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO™ resources.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for
conditions or supplies other than those specified.

Power Supply Sequencing

Power-On/Off Power Supply Sequencing
The recommended power-on sequence is VCCINT, VCCINT_IO/VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to achieve
minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off
sequence is the reverse of the power-on sequence. If VCCINT and VCCINT_IO/VCCBRAM have the same
recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCINT_IO
must be connected to VCCBRAM. If VCCAUX/VCCAUX_IO and VCCO have the same recommended voltage levels,
they can be powered by the same supply and ramped simultaneously. VCCAUX and VCCAUX_IO must be connected
together. VCCADC and VREF can be powered at any time and have no power-up sequencing requirements.

The recommended power-on sequence to achieve minimum current draw for the GTH or GTY transceivers is
VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for
VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence
is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences
are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down.

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Power Supply Requirements

Table 7 shows the minimum current, in addition to ICCQ maximum, required by each Kintex UltraScale+ FPGA for
proper power-on and configuration. If these current minimums are met, the device powers on after all supplies
have passed through their power-on reset threshold voltages. The device must not be configured until after
VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current
drain on these supplies. The XPE spreadsheet tool (download at http://www.xilinx.com/power) is also used to
estimate power-on current for all supplies.

Table 7: Power-on Current by Device

Device ICCINTMIN ICCINT_IOMIN + ICCBRAMMIN ICCOMIN ICCAUXMIN + ICCAUX_IOMIN Units

XCKU3P ICCINTQ + 770 ICCBRAMQ + ICCINT_IOQ + 229 ICCOQ + 50 ICCAUXQ + ICCAUX_IOQ + 386 mA
XCKU5P ICCINTQ + 770 ICCBRAMQ + ICCINT_IOQ + 305 ICCOQ + 50 ICCAUXQ + ICCAUX_IOQ + 515 mA
XCKU9P ICCINTQ + 1800 ICCBRAMQ + ICCINT_IOQ + 600 ICCOQ + 50 ICCAUXQ + ICCAUX_IOQ + 650 mA
XCKU11P ICCINTQ + 1961 ICCBRAMQ + ICCINT_IOQ + 654 ICCOQ + 55 ICCAUXQ + ICCAUX_IOQ + 709 mA
XCKU13P ICCINTQ + 2242 ICCBRAMQ + ICCINT_IOQ + 748 ICCOQ + 63 ICCAUXQ + ICCAUX_IOQ + 810 mA
XCKU15P ICCINTQ + 3433 ICCBRAMQ + ICCINT_IOQ + 1145 ICCOQ + 96 ICCAUXQ + ICCAUX_IOQ + 1240 mA

Table 8: Power Supply Ramp Time

Symbol Description Min Max Units

TVCCINT Ramp time from GND to 95% of VCCINT 0.2 40 ms
TVCCINT_IO Ramp time from GND to 95% of VCCINT_IO 0.2 40 ms
TVCCO Ramp time from GND to 95% of VCCO 0.2 40 ms
TVCCAUX Ramp time from GND to 95% of VCCAUX 0.2 40 ms
TVCCBRAM Ramp time from GND to 95% of VCCBRAM 0.2 40 ms
TMGTAVCC Ramp time from GND to 95% of VMGTAVCC 0.2 40 ms
TMGTAVTT Ramp time from GND to 95% of VMGTAVTT 0.2 40 ms
TMGTVCCAUX Ramp time from GND to 95% of VMGTVCCAUX 0.2 40 ms

DC Input and Output Levels

Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the
recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These
are chosen to ensure that all standards meet their specifications. The selected standards are tested at a
minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

I/O Levels
Table 9: SelectIO DC Input and Output Levels For HD I/O Banks

VIL VIH VOL VOH IOL IOH

I/O Standard1, 2
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.0 –8.0
HSTL_I_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.0 –8.0
HSUL_12 –0.300 VREF – 0.130 VREF + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.1 –0.1
LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO – 0.400 Note 3 Note 3
LVCMOS15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 4 Note 4
LVCMOS18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 4 Note 4
LVCMOS25 –0.300 0.700 1.700 VCCO + 0.300 0.400 VCCO – 0.400 Note 4 Note 4
LVCMOS33 –0.300 0.800 2.000 3.400 0.400 VCCO – 0.400 Note 4 Note 4
LVTTL –0.300 0.800 2.000 3.400 0.400 2.400 Note 4 Note 4
SSTL12 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 14.25 –14.25
SSTL135 –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 8.9 –8.9
SSTL135_II –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 13.0 –13.0
SSTL15 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 8.9 –8.9
SSTL15_II –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 13.0 –13.0
SSTL18_I –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470 8.0 –8.0
SSTL18_II –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.600 VCCO/2 + 0.600 13.4 –13.4
Notes:

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide
(UG571).
3. Supported drive strengths of 4, 8, or 12 mA in HD I/O banks.
4. Supported drive strengths of 4, 8, 12, or 16 mA in HD I/O banks.

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Product Specification 10
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 10: SelectIO DC Input and Output Levels for HP I/O Banks

VIL VIH VOL VOH IOL IOH

I/O Standard1, 2, 3
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 5.8 –5.8
HSTL_I_12 –0.300 VREF – 0.080 VREF + 0.080 VCCO + 0.300 25% VCCO 75% VCCO 4.1 –4.1
HSTL_I_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 6.2 –6.2
HSUL_12 –0.300 VREF – 0.130 VREF + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.1 –0.1
LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO – 0.400 Note 4 Note 4
LVCMOS15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 5 Note 5
LVCMOS18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 5 Note 5
LVDCI_15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 7.0 –7.0
LVDCI_18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 7.0 –7.0
SSTL12 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 8.0 –8.0
SSTL135 –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 9.0 –9.0
SSTL15 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 10.0 –10.0
SSTL18_I –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470 7.0 –7.0
MIPI_DPHY_ DCI_LP6 –0.300 0.550 0.880 VCCO + 0.300 0.050 1.100 0.01 –0.01
Notes:

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide
(UG571).
3. POD10 and POD12 DC input and output levels are shown in Table 11, Table 16, and Table 17.
4. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks.
5. Supported drive strengths of 2, 4, 6, 8, or 12 mA in HP I/O banks.
6. Low-power option for MIPI_DPHY_DCI.

Table 11: DC Input Levels for Single-ended POD10 and POD12 I/O Standards

VIL VIH
I/O Standard1, 2
V, Min V, Max V, Min V, Max
POD10 –0.300 VREF – 0.068 VREF + 0.068 VCCO + 0.300
POD12 –0.300 VREF – 0.068 VREF + 0.068 VCCO + 0.300
Notes:

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide
(UG571).

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Product Specification 11
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 12: Differential SelectIO DC Input and Output Levels

VICM (V)1 VID (V)2 VILHS3 VIHHS3 VOCM (V)4 VOD (V)5
I/O Standard
Min Typ Max Min Typ Max Min Max Min Typ Max Min Typ Max
SUB_LVDS8 0.500 0.900 1.300 0.070 – – – – 0.700 0.900 1.100 0.100 0.150 0.200
LVPECL 0.300 1.200 1.425 0.100 0.350 0.600 – – – – – – – –
SLVS_400_18 0.070 0.200 0.330 0.140 – 0.450 – – – – – – – –
SLVS_400_25 0.070 0.200 0.330 0.140 – 0.450 – – – – – – – –
MIPI_DPHY_ 0.070 – 0.330 0.070 – – –0.040 0.460 0.150 0.200 0.250 0.140 0.200 0.270
DCI_HS9
Notes:

1. VICM is the input common mode voltage.

2. VID is the input differential voltage (Q – Q).
3. VIHHS and VILHS are the single-ended input high and low voltages, respectively.
4. VOCM is the output common mode voltage.
5. VOD is the output differential voltage (Q – Q).
6. LVDS_25 is specified in Table 18.
7. LVDS is specified in Table 19.
8. Only the SUB_LVDS receiver is supported in HD I/O banks.
9. High-speed option for MIPI_DPHY_DCI. The VID maximum is aligned with the standard’s specification. A higher VID is acceptable as long
as the VIN specification is also met.

Table 13: Complementary Differential SelectIO DC Input and Output Levels for HD I/O Banks

VICM (V)1 VID (V)2 VOL (V)3 VOH (V)4 IOL IOH
I/O Standard
Min Typ Max Min Max Max Min mA mA
DIFF_HSTL_I 0.300 0.750 1.125 0.100 – 0.400 VCCO – 0.400 8.0 –8.0
DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 – 0.400 VCCO – 0.400 8.0 –8.0
DIFF_HSUL_12 0.300 0.600 0.850 0.100 – 20% VCCO 80% VCCO 0.1 –0.1
DIFF_SSTL12 0.300 0.600 0.850 0.100 – (VCCO/2) – 0.150 (VCCO/2) + 0.150 14.25 –14.25
DIFF_SSTL135 0.300 0.675 1.000 0.100 – (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.9 –8.9
DIFF_SSTL135_II 0.300 0.675 1.000 0.100 – (VCCO/2) – 0.150 (VCCO/2) + 0.150 13.0 –13.0
DIFF_SSTL15 0.300 0.750 1.125 0.100 – (VCCO/2) – 0.175 (VCCO/2) + 0.175 8.9 –8.9
DIFF_SSTL15_II 0.300 0.750 1.125 0.100 – (VCCO/2) – 0.175 (VCCO/2) + 0.175 13.0 –13.0
DIFF_SSTL18_I 0.300 0.900 1.425 0.100 – (VCCO/2) – 0.470 (VCCO/2) + 0.470 8.0 –8.0
DIFF_SSTL18_II 0.300 0.900 1.425 0.100 – (VCCO/2) – 0.600 (VCCO/2) + 0.600 13.4 –13.4
Notes:

1. VICM is the input common mode voltage.

2. VID is the input differential voltage.
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.

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Product Specification 12
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 14: Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks

VICM (V)2 VID (V)3 VOL (V)4 VOH (V)5 IOL IOH
I/O Standard1
Min Typ Max Min Max Max Min mA mA
DIFF_HSTL_I 0.680 VCCO/2 (VCCO/2) + 0.150 0.100 – 0.400 VCCO – 0.400 5.8 –5.8
DIFF_HSTL_I_12 0.400 x VCCO VCCO/2 0.600 x VCCO 0.100 – 0.250 x VCCO 0.750 x VCCO 4.1 –4.1
DIFF_HSTL_I_18 (VCCO/2) – 0.175 VCCO/2 (VCCO/2) + 0.175 0.100 – 0.400 VCCO – 0.400 6.2 –6.2
DIFF_HSUL_12 (VCCO/2) – 0.120 VCCO/2 (VCCO/2) + 0.120 0.100 – 20% VCCO 80% VCCO 0.1 –0.1
DIFF_SSTL12 (VCCO/2) – 0.150 VCCO/2 (VCCO/2) + 0.150 0.100 – (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.0 –8.0
DIFF_SSTL135 (VCCO/2) – 0.150 VCCO/2 (VCCO/2) + 0.150 0.100 – (VCCO/2) – 0.150 (VCCO/2) + 0.150 9.0 –9.0
DIFF_SSTL15 (VCCO/2) – 0.175 VCCO/2 (VCCO/2) + 0.175 0.100 – (VCCO/2) – 0.175 (VCCO/2) + 0.175 10.0 –10.0
DIFF_SSTL18_I (VCCO/2) – 0.175 VCCO/2 (VCCO/2) + 0.175 0.100 – (VCCO/2) – 0.470 (VCCO/2) + 0.470 7.0 –7.0
Notes:

1. DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown in Table 15, Table 16, Table 17.
2. VICM is the input common mode voltage.
3. VID is the input differential voltage.
4. VOL is the single-ended low-output voltage.
5. VOH is the single-ended high-output voltage.

Table 15: DC Input Levels for Differential POD10 and POD12 I/O Standards

VICM (V) VID (V)

I/O Standard1, 2
Min Typ Max Min Max
DIFF_POD10 0.63 0.70 0.77 0.14 –
DIFF_POD12 0.76 0.84 0.92 0.16 –
Notes:

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide
(UG571).

Table 16: DC Output Levels for Single-ended and Differential POD10 and POD12 Standards

Symbol Description1, 2 VOUT Min Typ Max Units

ROL Pull-down resistance VOM_DC (as described in Table 17) 36 40 44 Ω
ROH Pull-up resistance VOM_DC (as described in Table 17) 36 40 44 Ω
Notes:

1. Tested according to relevant specifications.

2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide
(UG571).

Table 17: Definitions for DC Output Levels for Single-ended and Differential POD10 and POD12
Standards

Symbol Description All Speed Grades Units

VOM_DC DC output Mid measurement level (for IV curve linearity) 0.8 x VCCO V

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Product Specification 13
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

LVDS DC Specifications (LVDS_25)

The LVDS_25 standard is available in the HD I/O banks. See the UltraScale Architecture SelectIO Resources User
Guide (UG571) for more information.

Table 18: LVDS_25 DC Specifications

Symbol DC Parameter Min Typ Max Units

VCCO1 Supply voltage 2.375 2.500 2.625 V
VIDIFF Differential input voltage: 100 350 6002 mV
(Q – Q), Q = High
(Q – Q), Q = High
VICM Input common-mode voltage 0.300 1.200 1.425 V
Notes:

1. LVDS_25 in HD I/O banks supports inputs only. LVDS_25 inputs without internal termination have no VCCO requirements. Any VCCO can be
chosen as long as the input voltage levels do not violate the Recommended Operating Condition (Table 2) specification for the VIN I/O pin
voltage.
2. Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the
recommended operating conditions and overshoot/undershoot VIN specifications are maintained.

LVDS DC Specifications (LVDS)

The LVDS standard is available in the HP I/O banks. See the UltraScale Architecture SelectIO Resources User Guide
(UG571) for more information.

Table 19: LVDS DC Specifications

Symbol DC Parameter Conditions Min Typ Max Units

VCCO1 Supply voltage 1.710 1.800 1.890 V
VODIFF 2 Differential output voltage: RT = 100Ω across Q and Q signals 247 350 454 mV
(Q – Q), Q = High
(Q – Q), Q = High
VOCM 2 Output common-mode voltage RT = 100Ω across Q and Q signals 1.000 1.250 1.425 V
VIDIFF 3 Differential output voltage: 100 350 6003 mV
(Q – Q), Q = High
(Q – Q), Q = High
VICM_DC4 Input common-mode voltage (DC coupling) 0.300 1.200 1.425 V
VICM_AC 5 Input common-mode voltage (AC coupling) 0.600 – 1.100 V
Notes:

1. In HP I/O banks, when LVDS is used with input-only functionality, it can be placed in a bank where the VCCO levels are different from the
specified level only if internal differential termination is not used. In this scenario, VCCO must be chosen to ensure the input pin voltage
levels do not violate the Recommended Operating Condition (Table 2) specification for the VIN I/O pin voltage.
2. VOCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE.
3. Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the
recommended operating conditions and overshoot/undershoot VIN specifications are maintained.
4. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).
5. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2,
EQ_LEVEL3, EQ_LEVEL4.

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Product Specification 14
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite as
outlined in the following table.

Table 20: Speed Specification Version By Device

2018.2.1 Device
1.21 XCKU3P, XCKU5P, XCKU9P, XCKU11P, XCKU13P, and XCKU15P

Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as follows:

• Advance Product Specification: These specifications are based on simulations only and are typically available
soon after device design specifications are frozen. Although speed grades with this designation are
considered relatively stable and conservative, some under-reporting might still occur.
• Preliminary Product Specification: These specifications are based on complete ES (engineering sample)
silicon characterization. Devices and speed grades with this designation are intended to give a better
indication of the expected performance of production silicon. The probability of under-reporting delays is
greatly reduced as compared to Advance data.
• Product Specification: These specifications are released once enough production silicon of a particular
device family member has been characterized to provide full correlation between specifications and devices
over numerous production lots. There is no under-reporting of delays, and customers receive formal
notification of any subsequent changes. Typically, the slowest speed grades transition to production before
faster speed grades.

Testing of AC Switching Characteristics

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics
are representative of worst-case supply voltage and junction temperature conditions.

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing
analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all
Kintex UltraScale+ FPGAs.

Speed Grade Designations

Since individual family members are produced at different times, the migration from one category to another
depends completely on the status of the fabrication process for each device. Table 21 correlates the current
status of the Kintex UltraScale+ FPGAs on a per speed grade basis.

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Product Specification 15
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 21: Speed Grade Designations by Device

Speed Grade, Temperature Ranges, and VCCINT Operating Voltages

Device
Advance Preliminary Production
XCKU3P -3E (VCCINT = 0.90V)
-2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V)
-1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V)
-2LE (VCCINT = 0.85V), -1LI (VCCINT = 0.85V)
-2LE (VCCINT = 0.72V)1, -1LI (VCCINT = 0.72V)1
XCKU5P -3E (VCCINT = 0.90V)
-2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V)
-1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V)
-2LE (VCCINT = 0.85V), -1LI (VCCINT = 0.85V)
-2LE (VCCINT = 0.72V)1, -1LI (VCCINT = 0.72V)1
XCKU9P -3E (VCCINT = 0.90V)
-2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V)
-1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V)
-2LE (VCCINT = 0.85V), -1LI (VCCINT = 0.85V)
-2LE (VCCINT = 0.72V)1, -1LI (VCCINT = 0.72V)1
XCKU11P -3E (VCCINT = 0.90V)
-2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V)
-1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V)
-2LE (VCCINT = 0.85V), -1LI (VCCINT = 0.85V)
-2LE (VCCINT = 0.72V)1, -1LI (VCCINT = 0.72V)1
XCKU13P -3E (VCCINT = 0.90V)
-2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V)
-1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V)
-2LE (VCCINT = 0.85V), -1LI (VCCINT = 0.85V)
-2LE (VCCINT = 0.72V)1, -1LI (VCCINT = 0.72V)1
XCKU15P -3E (VCCINT = 0.90V)
-2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V)
-1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V)
-2LE (VCCINT = 0.85V), -1LI (VCCINT = 0.85V)
-2LE (VCCINT = 0.72V)1, -1LI (VCCINT = 0.72V)1
Notes:

1. The lowest power -1L and -2L devices, where VCCINT = 0.72V, are listed in the Vivado Design Suite as -1LV and -2LV respectively.

Production Silicon and Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed
specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are
corrected in subsequent speed specification releases.

Table 22 lists the production released Kintex UltraScale+ FPGA, speed grade, and the minimum corresponding
supported speed specification version and Vivado software revisions. The Vivado software and speed
specifications listed are the minimum releases required for production. All subsequent releases of software and
speed specifications are valid.

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Product Specification 16
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 22: Kintex UltraScale+ FPGA Device Production Software and Speed Specification Release

Speed Grade and VCCINT Operating Voltages

Device 0.90V 0.85V 0.72V
-3 -2 -1 -2L -1L -2L -1L
XCKU3P Vivado tools 2018.1 v1.19 Vivado tools 2017.1 v1.10 Vivado tools 2017.4 v1.17
XCKU5P Vivado tools 2018.1 v1.19 Vivado tools 2017.1 v1.10 Vivado tools 2017.4 v1.17
XCKU9P Vivado tools 2018.2.1 v1.21 Vivado tools 2017.1 v1.10 Vivado tools 2017.3.1 v1.16
XCKU11P Vivado tools 2018.1 v1.19 Vivado tools 2017.3 v1.14 Vivado tools 2017.4.1 v1.18
XCKU13P Vivado tools 2018.1 v1.19 Vivado tools 2017.2 v1.12 Vivado tools 2017.3.1 v1.16
XCKU15P Vivado tools 2018.1 v1.19 Vivado tools 2017.2.1 v1.13 Vivado tools 2017.4 v1.17

FPGA Logic Performance Characteristics

This section provides the performance characteristics of some common functions and designs implemented in
the Kintex UltraScale+ FPGAs. These values are subject to the same guidelines as the AC Switching
Characteristics section.

In each of the following LVDS performance tables, the I/O bank type is either high performance (HP) or high
density (HD).

Table 23: LVDS Component Mode Performance

Speed Grade and VCCINT Operating Voltages

I/O 0.90V 0.85V 0.72V
Description Bank Units
Type -3 -2 -1 -2 -1
Min Max Min Max Min Max Min Max Min Max
LVDS TX DDR (OSERDES 4:1, 8:1) HP 0 1250 0 1250 0 1250 0 1250 0 1250 Mb/s
LVDS TX SDR (OSERDES 2:1, 4:1) HP 0 625 0 625 0 625 0 625 0 625 Mb/s
LVDS RX DDR (ISERDES 1:4, 1:8)1 HP 0 1250 0 1250 0 1250 0 1250 0 1250 Mb/s
LVDS RX DDR HD 0 250 0 250 0 250 0 250 0 250 Mb/s
LVDS RX SDR (ISERDES 1:2, 1:4)1 HP 0 625 0 625 0 625 0 625 0 625 Mb/s
LVDS RX SDR HD 0 125 0 125 0 125 0 125 0 125 Mb/s
Notes:

1. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and
should be removed through PCB routing.

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 24: LVDS Native Mode Performance

Speed Grade and VCCINT Operating Voltages

I/O 0.90V 0.85V 0.72V
Description1, 2 DATA_WIDTH Bank Units
Type -3 -2 -1 -2 -1
Min Max Min Max Min Max Min Max Min Max
LVDS TX DDR 4 HP 375 1600 375 1600 375 1260 375 1400 375 1260 Mb/s
(TX_BITSLICE)
8 375 1600 375 1600 375 1260 375 1600 375 1260 Mb/s
LVDS TX SDR 4 HP 187.5 800 187.5 800 187.5 630 187.5 700 187.5 630 Mb/s
(TX_BITSLICE)
8 187.5 800 187.5 800 187.5 630 187.5 800 187.5 630 Mb/s
LVDS RX DDR 4 HP 375 16004 375 16004 375 12604 375 14004 375 12604 Mb/s
(RX_BITSLICE)3
8 375 16004 375 16004 375 12604 375 16004 375 12604 Mb/s
LVDS RX SDR 4 HP 187.5 800 187.5 800 187.5 630 187.5 700 187.5 630 Mb/s
(RX_BITSLICE)3
8 187.5 800 187.5 800 187.5 630 187.5 800 187.5 630 Mb/s
Notes:

1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite. The performance
values assume a source-synchronous interface.
2. PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the
minimum frequency is PLL_FVCOMIN/2.
3. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and
should be removed through PCB routing.
4. Asynchronous receiver performance is limited to 1300 Mb/s for -3/-2 speed grades and to 1250 Mb/s for -1 speed grades.

Table 25: MIPI D-PHY Performance

Speed Grade and VCCINT Operating Voltages

I/O
Description Bank 0.90V 0.85V 0.72V Units
Type
-3 -2 -1 -2 -1
MIPI D-PHY transmitter or receiver HP 1500 1500 1260 1260 1260 Mb/s

Table 26: LVDS Native-Mode 1000BASE-X Support

Speed Grade and VCCINT Operating Voltages

Description1 I/O Bank Type 0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
1000BASE-X HP Yes
Notes:

1. 1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE Std 802.3-2008).

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Product Specification 18
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

The following table provides the maximum data rates for applicable memory standards using the
Kintex UltraScale+ FPGA memory PHY. Refer to Memory Interfaces for the complete list of memory interface
standards supported and detailed specifications. The final performance of the memory interface is determined
through a complete design implemented in the Vivado Design Suite, following guidelines in the UltraScale
Architecture PCB Design User Guide (UG583), electrical analysis, and characterization of the system.

Table 27: Maximum Physical Interface (PHY) Rate for Memory Interfaces

Speed Grade and VCCINT Operating Voltages

Memory
Package DRAM Type 0.90V 0.85V 0.72V Units
Standard
-3 -2 -1 -2 -1
DDR4 All FFV packages Single rank component 2666 2666 2400 2400 2133 Mb/s
1 rank DIMM1, 2, 3 2400 2400 2133 2133 1866 Mb/s
2 rank DIMM1, 4 2133 2133 1866 1866 1600 Mb/s
4 rank DIMM1, 5 1600 1600 1333 1333 N/A Mb/s
SFVB784 Single rank component 2400 2400 2133 2133 1866 Mb/s
1 rank DIMM1, 2 2133 2133 1866 1866 1600 Mb/s
2 rank DIMM1, 4 1866 1866 1600 1600 1600 Mb/s
DDR3 All FFV packages Single rank component 2133 2133 2133 2133 1866 Mb/s
1 rank DIMM1, 2 1866 1866 1866 1866 1600 Mb/s
2 rank DIMM1, 4 1600 1600 1600 1600 1333 Mb/s
4 rank DIMM1, 5 1066 1066 1066 1066 800 Mb/s
SFVB784 Single rank component 1866 1866 1866 1866 1600 Mb/s
1 rank DIMM1, 2 1600 1600 1600 1600 1600 Mb/s
2 rank DIMM1, 4 1600 1600 1600 1600 1333 Mb/s
4 rank DIMM1, 5 1066 1066 1066 1066 800 Mb/s
DDR3L All FFV packages Single rank component 1866 1866 1866 1866 1600 Mb/s
1 rank DIMM1, 2 1600 1600 1600 1600 1333 Mb/s
2 rank DIMM1, 4 1333 1333 1333 1333 1066 Mb/s
4 rank DIMM1, 5 800 800 800 800 606 Mb/s
SFVB784 Single rank component 1600 1600 1600 1600 1600 Mb/s
1 rank DIMM1, 2 1600 1600 1600 1600 1333 Mb/s
2 rank DIMM1, 4 1333 1333 1333 1333 1066 Mb/s
4 rank DIMM1, 5 800 800 800 800 606 Mb/s
QDR II+ All Single rank component6 633 633 600 600 550 MHz
RLDRAM 3 All FFV packages Single rank component 1200 1200 1066 1066 933 MHz
SFVB784 Single rank component 1066 1066 933 933 800 MHz
QDR IV XP All Single rank component 1066 1066 1066 933 933 MHz

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 27: Maximum Physical Interface (PHY) Rate for Memory Interfaces (cont'd)

Speed Grade and VCCINT Operating Voltages

Memory
Package DRAM Type 0.90V 0.85V 0.72V Units
Standard
-3 -2 -1 -2 -1
LPDDR3 All Single rank component 1600 1600 1600 1600 1600 Mb/s
Notes:

1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.
2. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.
3. For the DDR4 DDP components at -3 and -2 (VCCINT = 0.85V) speed grades, the maximum data rate is 2133 Mb/s for six or more DDP
devices. For five or less DDP devices, use the single rank DIMM data rates for the -3 and -2 (VCCINT = 0.85V) speed grades.
4. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.
5. Includes: 2 rank 2 slot, 4 rank 1 slot.
6. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.

FPGA Logic Switching Characteristics

The following IOB high-density (HD) and IOB high-performance (HP) tables summarize the values of standard-
specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.

• TINBUF_DELAY_PAD_I is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay
varies depending on the capability of the SelectIO input buffer.
• TOUTBUF_DELAY_O_PAD is the delay from the O pin to the IOB pad through the output buffer of an IOB pad.
The delay varies depending on the capability of the SelectIO output buffer.
• TOUTBUF_DELAY_TD_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad,
when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP
I/O banks, the internal DCI termination turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the
DCITERMDISABLE pin is used. In HD I/O banks, the on-die termination turn-on time is always faster than
TOUTBUF_DELAY_TD_PAD when the INTERMDISABLE pin is used.

IOB High Density (HD) Switching Characteristics

Table 28: IOB High Density (HD) Switching Characteristics

TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD

I/O Standards 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
DIFF_HSTL_I_18_F 0.873 0.978 1.058 0.978 1.058 1.510 1.574 1.718 1.966 2.101 1.160 1.160 1.271 1.515 1.544 ns
DIFF_HSTL_I_18_S 0.873 0.978 1.058 0.978 1.058 1.742 1.805 1.950 2.197 2.333 1.748 1.748 1.867 2.103 2.104 ns
DIFF_HSTL_I_F 0.873 0.978 1.058 0.978 1.058 1.563 1.611 1.762 2.003 2.145 1.313 1.313 1.417 1.668 1.668 ns
DIFF_HSTL_I_S 0.873 0.978 1.058 0.978 1.058 1.696 1.798 1.913 2.190 2.296 1.630 1.630 1.780 1.985 1.986 ns
DIFF_HSUL_12_F 0.796 0.911 0.977 0.911 0.977 1.493 1.573 1.703 1.965 2.086 1.222 1.222 1.335 1.577 1.578 ns
DIFF_HSUL_12_S 0.796 0.911 0.977 0.911 0.977 1.653 1.711 1.864 2.103 2.247 1.536 1.536 1.665 1.891 1.891 ns
DIFF_SSTL12_F 0.796 0.906 0.977 0.906 0.977 1.577 1.643 1.792 2.035 2.175 1.285 1.285 1.423 1.640 1.640 ns
DIFF_SSTL12_S 0.796 0.906 0.977 0.906 0.977 1.726 1.784 1.948 2.176 2.331 1.567 1.567 1.706 1.922 1.922 ns

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Product Specification 20
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 28: IOB High Density (HD) Switching Characteristics (cont'd)

TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD

I/O Standards 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
DIFF_SSTL135_F 0.807 0.927 0.995 0.927 0.995 1.558 1.625 1.765 2.017 2.148 1.341 1.341 1.458 1.696 1.696 ns
DIFF_SSTL135_II_F 0.807 0.927 0.995 0.927 0.995 1.560 1.623 1.770 2.015 2.153 1.325 1.325 1.470 1.680 1.689 ns
DIFF_SSTL135_II_S 0.807 0.927 0.995 0.927 0.995 1.694 1.768 1.916 2.160 2.299 1.722 1.722 1.911 2.077 2.078 ns
DIFF_SSTL135_S 0.807 0.927 0.995 0.927 0.995 1.796 1.869 2.025 2.261 2.408 1.814 1.814 1.976 2.169 2.169 ns
DIFF_SSTL15_F 0.840 0.928 1.020 0.928 1.020 1.559 1.628 1.771 2.020 2.154 1.374 1.374 1.483 1.729 1.729 ns
DIFF_SSTL15_II_F 0.840 0.928 1.020 0.928 1.020 1.574 1.622 1.778 2.014 2.161 1.356 1.356 1.442 1.711 1.712 ns
DIFF_SSTL15_II_S 0.840 0.928 1.020 0.928 1.020 1.769 1.821 1.987 2.213 2.370 1.895 1.895 2.047 2.250 2.250 ns
DIFF_SSTL15_S 0.840 0.928 1.020 0.928 1.020 1.752 1.824 1.977 2.216 2.360 1.743 1.743 1.907 2.098 2.098 ns
DIFF_SSTL18_II_F 0.873 0.961 1.038 0.961 1.038 1.672 1.729 1.880 2.121 2.263 1.377 1.377 1.492 1.732 1.732 ns
DIFF_SSTL18_II_S 0.873 0.961 1.038 0.961 1.038 1.748 1.796 1.965 2.188 2.348 1.616 1.616 1.800 1.971 1.972 ns
DIFF_SSTL18_I_F 0.873 0.961 1.038 0.961 1.038 1.539 1.609 1.755 2.001 2.138 1.220 1.220 1.313 1.575 1.575 ns
DIFF_SSTL18_I_S 0.873 0.961 1.038 0.961 1.038 1.728 1.786 1.942 2.178 2.325 1.677 1.677 1.836 2.032 2.033 ns
HSTL_I_18_F 0.854 0.947 1.021 0.947 1.021 1.510 1.574 1.718 1.966 2.101 1.160 1.160 1.271 1.515 1.544 ns
HSTL_I_18_S 0.854 0.947 1.021 0.947 1.021 1.742 1.805 1.950 2.197 2.333 1.748 1.748 1.867 2.103 2.104 ns
HSTL_I_F 0.748 0.856 0.900 0.856 0.900 1.563 1.611 1.762 2.003 2.145 1.313 1.313 1.417 1.668 1.668 ns
HSTL_I_S 0.748 0.856 0.900 0.856 0.900 1.696 1.798 1.913 2.190 2.296 1.630 1.630 1.780 1.985 1.986 ns
HSUL_12_F 0.712 0.780 0.867 0.780 0.867 1.493 1.573 1.703 1.965 2.086 1.222 1.222 1.335 1.577 1.578 ns
HSUL_12_S 0.712 0.780 0.867 0.780 0.867 1.653 1.711 1.864 2.103 2.247 1.536 1.536 1.665 1.891 1.891 ns
LVCMOS12_F_12 0.761 0.918 0.976 0.918 0.976 1.652 1.689 1.856 2.081 2.239 1.202 1.202 1.317 1.557 1.557 ns
LVCMOS12_F_4 0.761 0.918 0.976 0.918 0.976 1.714 1.742 1.922 2.134 2.305 1.353 1.353 1.478 1.708 1.708 ns
LVCMOS12_F_8 0.761 0.918 0.976 0.918 0.976 1.668 1.714 1.879 2.106 2.262 1.292 1.292 1.432 1.647 1.647 ns
LVCMOS12_S_12 0.761 0.918 0.976 0.918 0.976 2.019 2.073 2.247 2.465 2.630 1.581 1.581 1.717 1.936 1.937 ns
LVCMOS12_S_4 0.761 0.918 0.976 0.918 0.976 1.979 1.979 2.182 2.371 2.565 1.633 1.633 1.772 1.988 1.989 ns
LVCMOS12_S_8 0.761 0.918 0.976 0.918 0.976 2.132 2.205 2.406 2.597 2.789 1.767 1.767 1.928 2.122 2.123 ns
LVCMOS15_F_12 0.775 0.905 0.958 0.905 0.958 1.691 1.713 1.892 2.105 2.275 1.275 1.275 1.428 1.630 1.630 ns
LVCMOS15_F_16 0.775 0.905 0.958 0.905 0.958 1.665 1.722 1.881 2.114 2.264 1.260 1.260 1.407 1.615 1.615 ns
LVCMOS15_F_4 0.775 0.905 0.958 0.905 0.958 1.747 1.825 1.959 2.217 2.342 1.453 1.453 1.557 1.808 1.809 ns
LVCMOS15_F_8 0.775 0.905 0.958 0.905 0.958 1.721 1.778 1.930 2.170 2.313 1.378 1.378 1.458 1.733 1.733 ns
LVCMOS15_S_12 0.775 0.905 0.958 0.905 0.958 1.936 1.991 2.139 2.383 2.522 1.516 1.516 1.648 1.871 1.871 ns
LVCMOS15_S_16 0.775 0.905 0.958 0.905 0.958 2.172 2.172 2.389 2.564 2.772 1.707 1.707 1.888 2.062 2.062 ns
LVCMOS15_S_4 0.775 0.905 0.958 0.905 0.958 2.274 2.313 2.483 2.705 2.866 1.952 1.952 2.123 2.307 2.307 ns
LVCMOS15_S_8 0.775 0.905 0.958 0.905 0.958 2.170 2.170 2.400 2.562 2.783 1.817 1.817 1.984 2.172 2.173 ns
LVCMOS18_F_12 0.810 0.915 0.958 0.915 0.958 1.741 1.805 1.962 2.197 2.345 1.383 1.383 1.471 1.738 1.738 ns
LVCMOS18_F_16 0.810 0.915 0.958 0.915 0.958 1.698 1.785 1.917 2.177 2.300 1.338 1.338 1.446 1.693 1.693 ns
LVCMOS18_F_4 0.810 0.915 0.958 0.915 0.958 1.815 1.868 2.013 2.260 2.396 1.472 1.472 1.599 1.827 1.832 ns
LVCMOS18_F_8 0.810 0.915 0.958 0.915 0.958 1.785 1.797 1.979 2.189 2.362 1.384 1.384 1.487 1.739 1.739 ns
LVCMOS18_S_12 0.810 0.915 0.958 0.915 0.958 2.163 2.201 2.408 2.593 2.791 1.762 1.762 1.894 2.117 2.118 ns
LVCMOS18_S_16 0.810 0.915 0.958 0.915 0.958 2.102 2.173 2.362 2.565 2.745 1.702 1.702 1.834 2.057 2.057 ns
LVCMOS18_S_4 0.810 0.915 0.958 0.915 0.958 2.342 2.346 2.567 2.738 2.950 1.951 1.951 2.092 2.306 2.306 ns

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 28: IOB High Density (HD) Switching Characteristics (cont'd)

TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD

I/O Standards 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
LVCMOS18_S_8 0.810 0.915 0.958 0.915 0.958 2.275 2.292 2.511 2.684 2.894 1.848 1.848 2.008 2.203 2.204 ns
LVCMOS25_F_12 0.963 0.988 1.042 0.988 1.042 2.153 2.153 2.453 2.545 2.836 1.692 1.692 1.856 2.047 2.047 ns
LVCMOS25_F_16 0.963 0.988 1.042 0.988 1.042 2.105 2.105 2.406 2.497 2.789 1.623 1.623 1.786 1.978 1.979 ns
LVCMOS25_F_4 0.963 0.988 1.042 0.988 1.042 2.317 2.344 2.554 2.736 2.937 1.842 1.842 2.039 2.197 2.197 ns
LVCMOS25_F_8 0.963 0.988 1.042 0.988 1.042 2.184 2.184 2.516 2.576 2.899 1.726 1.726 1.910 2.081 2.081 ns
LVCMOS25_S_12 0.963 0.988 1.042 0.988 1.042 2.550 2.558 2.840 2.950 3.223 1.971 1.971 2.194 2.326 2.327 ns
LVCMOS25_S_16 0.963 0.988 1.042 0.988 1.042 2.449 2.449 2.740 2.841 3.123 1.852 1.852 2.063 2.207 2.207 ns
LVCMOS25_S_4 0.963 0.988 1.042 0.988 1.042 2.770 2.770 3.066 3.162 3.449 2.224 2.224 2.458 2.579 2.579 ns
LVCMOS25_S_8 0.963 0.988 1.042 0.988 1.042 2.663 2.663 2.963 3.055 3.346 2.091 2.091 2.373 2.446 2.446 ns
LVCMOS33_F_12 1.154 1.154 1.213 1.154 1.213 2.415 2.415 2.651 2.807 3.034 1.754 1.754 1.915 2.109 2.109 ns
LVCMOS33_F_16 1.154 1.154 1.213 1.154 1.213 2.381 2.383 2.603 2.775 2.986 1.734 1.734 1.869 2.089 2.089 ns
LVCMOS33_F_4 1.154 1.154 1.213 1.154 1.213 2.541 2.541 2.765 2.933 3.148 1.932 1.932 2.135 2.287 2.287 ns
LVCMOS33_F_8 1.154 1.154 1.213 1.154 1.213 2.603 2.603 2.822 2.995 3.205 1.937 1.937 2.130 2.292 2.294 ns
LVCMOS33_S_12 1.154 1.154 1.213 1.154 1.213 2.705 2.705 3.047 3.097 3.430 2.049 2.049 2.318 2.404 2.404 ns
LVCMOS33_S_16 1.154 1.154 1.213 1.154 1.213 2.714 2.714 3.024 3.106 3.407 2.028 2.028 2.232 2.383 2.383 ns
LVCMOS33_S_4 1.154 1.154 1.213 1.154 1.213 2.999 2.999 3.340 3.391 3.723 2.320 2.320 2.610 2.675 2.675 ns
LVCMOS33_S_8 1.154 1.154 1.213 1.154 1.213 2.929 2.929 3.260 3.321 3.643 2.260 2.260 2.532 2.615 2.616 ns
LVDS_25 0.980 1.003 1.116 1.003 1.116 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ns
LVPECL 0.980 1.003 1.116 1.003 1.116 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ns
LVTTL_F_12 1.164 1.164 1.223 1.164 1.223 2.415 2.415 2.651 2.807 3.034 1.754 1.754 1.915 2.109 2.109 ns
LVTTL_F_16 1.164 1.164 1.223 1.164 1.223 2.464 2.464 2.732 2.856 3.115 1.750 1.750 1.986 2.105 2.117 ns
LVTTL_F_4 1.164 1.164 1.223 1.164 1.223 2.541 2.541 2.765 2.933 3.148 1.932 1.932 2.135 2.287 2.287 ns
LVTTL_F_8 1.164 1.164 1.223 1.164 1.223 2.582 2.582 2.787 2.974 3.170 1.910 1.910 2.063 2.265 2.265 ns
LVTTL_S_12 1.164 1.164 1.223 1.164 1.223 2.731 2.731 3.075 3.123 3.458 2.072 2.072 2.343 2.427 2.427 ns
LVTTL_S_16 1.164 1.164 1.223 1.164 1.223 2.714 2.714 3.024 3.106 3.407 2.028 2.028 2.232 2.383 2.383 ns
LVTTL_S_4 1.164 1.164 1.223 1.164 1.223 2.999 2.999 3.340 3.391 3.723 2.320 2.320 2.610 2.675 2.675 ns
LVTTL_S_8 1.164 1.164 1.223 1.164 1.223 2.929 2.929 3.260 3.321 3.643 2.260 2.260 2.532 2.615 2.616 ns
SLVS_400_25 0.998 1.020 1.136 1.020 1.136 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ns
SSTL12_F 0.712 0.780 0.867 0.780 0.867 1.577 1.643 1.792 2.035 2.175 1.285 1.285 1.423 1.640 1.640 ns
SSTL12_S 0.712 0.780 0.867 0.780 0.867 1.726 1.784 1.948 2.176 2.331 1.567 1.567 1.706 1.922 1.922 ns
SSTL135_F 0.731 0.798 0.881 0.798 0.881 1.558 1.625 1.765 2.017 2.148 1.341 1.341 1.458 1.696 1.696 ns
SSTL135_II_F 0.731 0.798 0.881 0.798 0.881 1.574 1.623 1.770 2.015 2.153 1.325 1.325 1.470 1.680 1.689 ns
SSTL135_II_S 0.731 0.798 0.881 0.798 0.881 1.694 1.768 1.916 2.160 2.299 1.722 1.722 1.911 2.077 2.078 ns
SSTL135_S 0.731 0.798 0.881 0.798 0.881 1.796 1.869 2.025 2.261 2.408 1.814 1.814 1.976 2.169 2.169 ns
SSTL15_F 0.731 0.838 0.880 0.838 0.880 1.544 1.612 1.754 2.004 2.137 1.357 1.357 1.464 1.712 1.713 ns
SSTL15_II_F 0.731 0.838 0.880 0.838 0.880 1.588 1.622 1.778 2.014 2.161 1.356 1.356 1.442 1.711 1.712 ns
SSTL15_II_S 0.731 0.838 0.880 0.838 0.880 1.769 1.821 1.987 2.213 2.370 1.895 1.895 2.047 2.250 2.250 ns
SSTL15_S 0.731 0.838 0.880 0.838 0.880 1.752 1.824 1.977 2.216 2.360 1.743 1.743 1.907 2.098 2.098 ns
SSTL18_II_F 0.854 0.947 1.021 0.947 1.021 1.699 1.729 1.880 2.121 2.263 1.377 1.377 1.492 1.732 1.732 ns

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Product Specification 22
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 28: IOB High Density (HD) Switching Characteristics (cont'd)

TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD

I/O Standards 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
SSTL18_II_S 0.854 0.947 1.021 0.947 1.021 1.748 1.796 1.965 2.188 2.348 1.616 1.616 1.800 1.971 1.972 ns
SSTL18_I_F 0.854 0.947 1.021 0.947 1.021 1.566 1.609 1.755 2.001 2.138 1.220 1.220 1.313 1.575 1.575 ns
SSTL18_I_S 0.854 0.947 1.021 0.947 1.021 1.745 1.786 1.942 2.178 2.325 1.677 1.677 1.836 2.032 2.033 ns
SUB_LVDS 0.871 1.002 1.036 1.002 1.036 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ns

IOB High Performance (HP) Switching Characteristics

Table 29: IOB High Performance (HP) Switching Characteristics

TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD

I/O Standards 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
DIFF_HSTL_I_12_F 0.288 0.394 0.402 0.394 0.402 0.410 0.423 0.443 0.423 0.443 0.514 0.553 0.582 0.553 0.582 ns
DIFF_HSTL_I_12_M 0.288 0.394 0.402 0.394 0.402 0.552 0.552 0.583 0.552 0.583 0.632 0.641 0.679 0.641 0.679 ns
DIFF_HSTL_I_12_S 0.288 0.394 0.402 0.394 0.402 0.752 0.752 0.800 0.752 0.800 0.813 0.813 0.868 0.813 0.868 ns
DIFF_HSTL_I_18_F 0.259 0.319 0.339 0.319 0.339 0.439 0.456 0.474 0.456 0.474 0.549 0.576 0.606 0.576 0.606 ns
DIFF_HSTL_I_18_M 0.259 0.319 0.339 0.319 0.339 0.563 0.570 0.603 0.570 0.603 0.636 0.653 0.692 0.653 0.692 ns
DIFF_HSTL_I_18_S 0.259 0.319 0.339 0.319 0.339 0.782 0.782 0.834 0.782 0.834 0.816 0.816 0.871 0.816 0.871 ns
DIFF_HSTL_I_DCI_12_F 0.288 0.394 0.402 0.394 0.402 0.393 0.406 0.429 0.406 0.429 0.502 0.534 0.564 0.534 0.564 ns
DIFF_HSTL_I_DCI_12_M 0.288 0.394 0.402 0.394 0.402 0.546 0.557 0.587 0.557 0.587 0.636 0.653 0.694 0.653 0.694 ns
DIFF_HSTL_I_DCI_12_S 0.288 0.394 0.402 0.394 0.402 0.755 0.755 0.806 0.755 0.806 0.842 0.842 0.907 0.842 0.907 ns
DIFF_HSTL_I_DCI_18_F 0.259 0.323 0.339 0.323 0.339 0.422 0.445 0.461 0.445 0.461 0.509 0.566 0.595 0.566 0.595 ns
DIFF_HSTL_I_DCI_18_M 0.259 0.323 0.339 0.323 0.339 0.546 0.555 0.586 0.555 0.586 0.626 0.643 0.684 0.643 0.684 ns
DIFF_HSTL_I_DCI_18_S 0.259 0.323 0.339 0.323 0.339 0.762 0.762 0.818 0.762 0.818 0.836 0.836 0.900 0.836 0.900 ns
DIFF_HSTL_I_DCI_F 0.335 0.397 0.417 0.397 0.417 0.407 0.431 0.445 0.431 0.445 0.517 0.555 0.575 0.555 0.575 ns
DIFF_HSTL_I_DCI_M 0.335 0.397 0.417 0.397 0.417 0.549 0.553 0.583 0.553 0.583 0.634 0.644 0.684 0.644 0.684 ns
DIFF_HSTL_I_DCI_S 0.335 0.397 0.417 0.397 0.417 0.767 0.767 0.823 0.767 0.823 0.848 0.848 0.912 0.848 0.912 ns
DIFF_HSTL_I_F 0.304 0.404 0.417 0.404 0.417 0.409 0.423 0.443 0.423 0.443 0.514 0.549 0.581 0.549 0.581 ns
DIFF_HSTL_I_M 0.304 0.404 0.417 0.404 0.417 0.549 0.555 0.586 0.555 0.586 0.624 0.640 0.677 0.640 0.677 ns
DIFF_HSTL_I_S 0.304 0.404 0.417 0.404 0.417 0.767 0.767 0.818 0.767 0.818 0.811 0.811 0.866 0.811 0.866 ns
DIFF_HSUL_12_DCI_F 0.320 0.381 0.400 0.381 0.400 0.411 0.425 0.443 0.425 0.443 0.520 0.558 0.586 0.558 0.586 ns
DIFF_HSUL_12_DCI_M 0.320 0.381 0.400 0.381 0.400 0.546 0.557 0.587 0.557 0.587 0.636 0.653 0.694 0.653 0.694 ns
DIFF_HSUL_12_DCI_S 0.320 0.381 0.400 0.381 0.400 0.737 0.737 0.787 0.737 0.787 0.822 0.822 0.885 0.822 0.885 ns
DIFF_HSUL_12_F 0.322 0.394 0.402 0.394 0.402 0.394 0.412 0.430 0.412 0.430 0.494 0.538 0.566 0.538 0.566 ns
DIFF_HSUL_12_M 0.322 0.394 0.402 0.394 0.402 0.552 0.552 0.583 0.552 0.583 0.632 0.641 0.679 0.641 0.679 ns
DIFF_HSUL_12_S 0.322 0.394 0.402 0.394 0.402 0.752 0.752 0.800 0.752 0.800 0.813 0.813 0.868 0.813 0.868 ns
DIFF_POD10_DCI_F 0.289 0.411 0.430 0.411 0.430 0.407 0.425 0.444 0.425 0.444 0.512 0.555 0.584 0.555 0.584 ns
DIFF_POD10_DCI_M 0.289 0.411 0.430 0.411 0.430 0.533 0.542 0.571 0.542 0.571 0.618 0.640 0.681 0.640 0.681 ns
DIFF_POD10_DCI_S 0.289 0.411 0.430 0.411 0.430 0.754 0.754 0.815 0.754 0.815 0.850 0.850 0.917 0.850 0.917 ns

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Product Specification 23
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 29: IOB High Performance (HP) Switching Characteristics (cont'd)

TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD

I/O Standards 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
DIFF_POD10_F 0.288 0.411 0.433 0.411 0.433 0.425 0.438 0.459 0.438 0.459 0.531 0.569 0.601 0.569 0.601 ns
DIFF_POD10_M 0.288 0.411 0.433 0.411 0.433 0.519 0.538 0.568 0.538 0.568 0.589 0.630 0.667 0.630 0.667 ns
DIFF_POD10_S 0.288 0.411 0.433 0.411 0.433 0.752 0.766 0.821 0.766 0.821 0.821 0.836 0.894 0.836 0.894 ns
DIFF_POD12_DCI_F 0.320 0.407 0.432 0.407 0.432 0.411 0.425 0.443 0.425 0.443 0.519 0.558 0.586 0.558 0.586 ns
DIFF_POD12_DCI_M 0.320 0.407 0.432 0.407 0.432 0.516 0.543 0.572 0.543 0.572 0.602 0.638 0.678 0.638 0.678 ns
DIFF_POD12_DCI_S 0.320 0.407 0.432 0.407 0.432 0.740 0.772 0.822 0.772 0.822 0.833 0.862 0.929 0.862 0.929 ns
DIFF_POD12_F 0.305 0.409 0.430 0.409 0.430 0.438 0.455 0.476 0.455 0.476 0.549 0.595 0.626 0.595 0.626 ns
DIFF_POD12_M 0.305 0.409 0.430 0.409 0.430 0.551 0.551 0.582 0.551 0.582 0.632 0.641 0.679 0.641 0.679 ns
DIFF_POD12_S 0.305 0.409 0.430 0.409 0.430 0.749 0.767 0.817 0.767 0.817 0.818 0.832 0.889 0.832 0.889 ns
DIFF_SSTL12_DCI_F 0.303 0.381 0.400 0.381 0.400 0.411 0.425 0.443 0.425 0.443 0.520 0.558 0.586 0.558 0.586 ns
DIFF_SSTL12_DCI_M 0.303 0.381 0.400 0.381 0.400 0.549 0.557 0.587 0.557 0.587 0.643 0.654 0.694 0.654 0.694 ns
DIFF_SSTL12_DCI_S 0.303 0.381 0.400 0.381 0.400 0.754 0.754 0.803 0.754 0.803 0.842 0.842 0.908 0.842 0.908 ns
DIFF_SSTL12_F 0.288 0.394 0.402 0.394 0.402 0.394 0.412 0.430 0.412 0.430 0.494 0.538 0.566 0.538 0.566 ns
DIFF_SSTL12_M 0.288 0.394 0.402 0.394 0.402 0.550 0.553 0.584 0.553 0.584 0.630 0.641 0.676 0.641 0.676 ns
DIFF_SSTL12_S 0.288 0.394 0.402 0.394 0.402 0.758 0.758 0.808 0.758 0.808 0.823 0.823 0.879 0.823 0.879 ns
DIFF_SSTL135_DCI_F 0.303 0.371 0.402 0.371 0.402 0.392 0.411 0.428 0.411 0.428 0.494 0.537 0.565 0.537 0.565 ns
DIFF_SSTL135_DCI_M 0.303 0.371 0.402 0.371 0.402 0.551 0.551 0.582 0.551 0.582 0.643 0.645 0.685 0.645 0.685 ns
DIFF_SSTL135_DCI_S 0.303 0.371 0.402 0.371 0.402 0.746 0.746 0.799 0.746 0.799 0.829 0.829 0.893 0.829 0.893 ns
DIFF_SSTL135_F 0.289 0.375 0.402 0.375 0.402 0.393 0.408 0.428 0.408 0.428 0.491 0.528 0.561 0.528 0.561 ns
DIFF_SSTL135_M 0.289 0.375 0.402 0.375 0.402 0.548 0.555 0.585 0.555 0.585 0.621 0.641 0.679 0.641 0.679 ns
DIFF_SSTL135_S 0.289 0.375 0.402 0.375 0.402 0.772 0.772 0.823 0.772 0.823 0.827 0.827 0.878 0.827 0.878 ns
DIFF_SSTL15_DCI_F 0.335 0.397 0.417 0.397 0.417 0.394 0.412 0.429 0.412 0.429 0.497 0.531 0.563 0.531 0.563 ns
DIFF_SSTL15_DCI_M 0.335 0.397 0.417 0.397 0.417 0.549 0.553 0.583 0.553 0.583 0.632 0.645 0.685 0.645 0.685 ns
DIFF_SSTL15_DCI_S 0.335 0.397 0.417 0.397 0.417 0.768 0.768 0.822 0.768 0.822 0.847 0.847 0.912 0.847 0.912 ns
DIFF_SSTL15_F 0.304 0.404 0.417 0.404 0.417 0.409 0.424 0.445 0.424 0.445 0.513 0.551 0.577 0.551 0.577 ns
DIFF_SSTL15_M 0.304 0.404 0.417 0.404 0.417 0.547 0.554 0.585 0.554 0.585 0.624 0.639 0.677 0.639 0.677 ns
DIFF_SSTL15_S 0.304 0.404 0.417 0.404 0.417 0.767 0.767 0.817 0.767 0.817 0.813 0.813 0.867 0.813 0.867 ns
DIFF_SSTL18_I_DCI_F 0.256 0.320 0.336 0.320 0.336 0.422 0.445 0.461 0.445 0.461 0.540 0.566 0.595 0.566 0.595 ns
DIFF_SSTL18_I_DCI_M 0.256 0.320 0.336 0.320 0.336 0.552 0.554 0.585 0.554 0.585 0.629 0.644 0.683 0.644 0.683 ns
DIFF_SSTL18_I_DCI_S 0.256 0.320 0.336 0.320 0.336 0.762 0.762 0.818 0.762 0.818 0.837 0.837 0.899 0.837 0.899 ns
DIFF_SSTL18_I_F 0.256 0.316 0.336 0.316 0.336 0.439 0.454 0.476 0.454 0.476 0.549 0.578 0.608 0.578 0.608 ns
DIFF_SSTL18_I_M 0.256 0.316 0.336 0.316 0.336 0.567 0.571 0.603 0.571 0.603 0.535 0.652 0.692 0.652 0.692 ns
DIFF_SSTL18_I_S 0.256 0.316 0.336 0.316 0.336 0.782 0.782 0.835 0.782 0.835 0.816 0.816 0.870 0.816 0.870 ns
HSLVDCI_15_F 0.336 0.393 0.415 0.393 0.415 0.407 0.425 0.443 0.425 0.443 0.513 0.548 0.579 0.548 0.579 ns
HSLVDCI_15_M 0.336 0.393 0.415 0.393 0.415 0.548 0.552 0.581 0.552 0.581 0.635 0.644 0.684 0.644 0.684 ns
HSLVDCI_15_S 0.336 0.393 0.415 0.393 0.415 0.748 0.748 0.802 0.748 0.802 0.827 0.827 0.890 0.827 0.890 ns
HSLVDCI_18_F 0.367 0.424 0.447 0.424 0.447 0.424 0.445 0.461 0.445 0.461 0.541 0.566 0.595 0.566 0.595 ns
HSLVDCI_18_M 0.367 0.424 0.447 0.424 0.447 0.563 0.567 0.598 0.567 0.598 0.647 0.658 0.699 0.658 0.699 ns
HSLVDCI_18_S 0.367 0.424 0.447 0.424 0.447 0.761 0.761 0.817 0.761 0.817 0.836 0.836 0.900 0.836 0.900 ns

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Product Specification 24
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 29: IOB High Performance (HP) Switching Characteristics (cont'd)

TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD

I/O Standards 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
HSTL_I_12_F 0.322 0.378 0.399 0.378 0.399 0.410 0.423 0.443 0.423 0.443 0.514 0.553 0.582 0.553 0.582 ns
HSTL_I_12_M 0.322 0.378 0.399 0.378 0.399 0.551 0.551 0.582 0.551 0.582 0.632 0.642 0.679 0.642 0.679 ns
HSTL_I_12_S 0.322 0.378 0.399 0.378 0.399 0.750 0.750 0.799 0.750 0.799 0.813 0.813 0.868 0.813 0.868 ns
HSTL_I_18_F 0.258 0.322 0.339 0.322 0.339 0.439 0.456 0.474 0.456 0.474 0.549 0.576 0.606 0.576 0.606 ns
HSTL_I_18_M 0.258 0.322 0.339 0.322 0.339 0.562 0.569 0.602 0.569 0.602 0.637 0.653 0.692 0.653 0.692 ns
HSTL_I_18_S 0.258 0.322 0.339 0.322 0.339 0.781 0.781 0.833 0.781 0.833 0.816 0.816 0.871 0.816 0.871 ns
HSTL_I_DCI_12_F 0.322 0.378 0.399 0.378 0.399 0.393 0.406 0.429 0.406 0.429 0.502 0.534 0.564 0.534 0.564 ns
HSTL_I_DCI_12_M 0.322 0.378 0.399 0.378 0.399 0.551 0.556 0.586 0.556 0.586 0.644 0.654 0.694 0.654 0.694 ns
HSTL_I_DCI_12_S 0.322 0.378 0.399 0.378 0.399 0.754 0.754 0.803 0.754 0.803 0.842 0.842 0.907 0.842 0.907 ns
HSTL_I_DCI_18_F 0.258 0.321 0.339 0.321 0.339 0.422 0.445 0.461 0.445 0.461 0.509 0.566 0.595 0.566 0.595 ns
HSTL_I_DCI_18_M 0.258 0.321 0.339 0.321 0.339 0.551 0.554 0.585 0.554 0.585 0.634 0.643 0.684 0.643 0.684 ns
HSTL_I_DCI_18_S 0.258 0.321 0.339 0.321 0.339 0.761 0.761 0.817 0.761 0.817 0.836 0.836 0.900 0.836 0.900 ns
HSTL_I_DCI_F 0.288 0.393 0.415 0.393 0.415 0.407 0.431 0.445 0.431 0.445 0.517 0.555 0.575 0.555 0.575 ns
HSTL_I_DCI_M 0.288 0.393 0.415 0.393 0.415 0.548 0.552 0.581 0.552 0.581 0.635 0.644 0.684 0.644 0.684 ns
HSTL_I_DCI_S 0.288 0.393 0.415 0.393 0.415 0.766 0.766 0.821 0.766 0.821 0.847 0.847 0.912 0.847 0.912 ns
HSTL_I_F 0.322 0.378 0.399 0.378 0.399 0.409 0.423 0.443 0.423 0.443 0.514 0.549 0.581 0.549 0.581 ns
HSTL_I_M 0.322 0.378 0.399 0.378 0.399 0.548 0.554 0.585 0.554 0.585 0.624 0.640 0.677 0.640 0.677 ns
HSTL_I_S 0.322 0.378 0.399 0.378 0.399 0.766 0.766 0.816 0.766 0.816 0.811 0.811 0.866 0.811 0.866 ns
HSUL_12_DCI_F 0.319 0.378 0.399 0.378 0.399 0.411 0.425 0.443 0.425 0.443 0.520 0.558 0.586 0.558 0.586 ns
HSUL_12_DCI_M 0.319 0.378 0.399 0.378 0.399 0.551 0.556 0.586 0.556 0.586 0.644 0.654 0.694 0.654 0.694 ns
HSUL_12_DCI_S 0.319 0.378 0.399 0.378 0.399 0.736 0.736 0.784 0.736 0.784 0.821 0.821 0.886 0.821 0.886 ns
HSUL_12_F 0.305 0.378 0.399 0.378 0.399 0.394 0.412 0.430 0.412 0.430 0.494 0.538 0.566 0.538 0.566 ns
HSUL_12_M 0.305 0.378 0.399 0.378 0.399 0.551 0.551 0.582 0.551 0.582 0.632 0.642 0.679 0.642 0.679 ns
HSUL_12_S 0.305 0.378 0.399 0.378 0.399 0.750 0.750 0.799 0.750 0.799 0.813 0.813 0.868 0.813 0.868 ns
LVCMOS12_F_2 0.443 0.512 0.555 0.512 0.555 0.657 0.672 0.692 0.672 0.692 0.862 0.898 0.922 0.898 0.922 ns
LVCMOS12_F_4 0.443 0.512 0.555 0.512 0.555 0.486 0.504 0.521 0.504 0.521 0.645 0.664 0.693 0.664 0.693 ns
LVCMOS12_F_6 0.443 0.512 0.555 0.512 0.555 0.469 0.485 0.507 0.485 0.507 0.585 0.634 0.669 0.634 0.669 ns
LVCMOS12_F_8 0.443 0.512 0.555 0.512 0.555 0.457 0.465 0.489 0.465 0.489 0.592 0.611 0.666 0.611 0.666 ns
LVCMOS12_M_2 0.443 0.512 0.555 0.512 0.555 0.687 0.708 0.727 0.708 0.727 0.889 0.916 0.945 0.916 0.945 ns
LVCMOS12_M_4 0.443 0.512 0.555 0.512 0.555 0.533 0.550 0.573 0.550 0.573 0.629 0.664 0.690 0.664 0.690 ns
LVCMOS12_M_6 0.443 0.512 0.555 0.512 0.555 0.520 0.527 0.554 0.527 0.554 0.608 0.622 0.652 0.622 0.652 ns
LVCMOS12_M_8 0.443 0.512 0.555 0.512 0.555 0.532 0.540 0.571 0.540 0.571 0.606 0.614 0.649 0.614 0.649 ns
LVCMOS12_S_2 0.443 0.512 0.555 0.512 0.555 0.767 0.767 0.803 0.767 0.803 0.981 0.990 1.024 0.990 1.024 ns
LVCMOS12_S_4 0.443 0.512 0.555 0.512 0.555 0.666 0.666 0.704 0.666 0.704 0.803 0.803 0.848 0.803 0.848 ns
LVCMOS12_S_6 0.443 0.512 0.555 0.512 0.555 0.657 0.657 0.695 0.657 0.695 0.732 0.732 0.774 0.732 0.774 ns
LVCMOS12_S_8 0.443 0.512 0.555 0.512 0.555 0.708 0.708 0.761 0.708 0.761 0.745 0.745 0.790 0.745 0.790 ns
LVCMOS15_F_12 0.368 0.414 0.445 0.414 0.445 0.485 0.500 0.522 0.500 0.522 0.584 0.647 0.682 0.647 0.682 ns
LVCMOS15_F_2 0.368 0.414 0.445 0.414 0.445 0.686 0.702 0.722 0.702 0.722 0.893 0.919 0.940 0.919 0.940 ns
LVCMOS15_F_4 0.368 0.414 0.445 0.414 0.445 0.567 0.579 0.601 0.579 0.601 0.727 0.755 0.781 0.755 0.781 ns

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Product Specification 25
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 29: IOB High Performance (HP) Switching Characteristics (cont'd)

TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD

I/O Standards 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
LVCMOS15_F_6 0.368 0.414 0.445 0.414 0.445 0.533 0.547 0.569 0.547 0.569 0.684 0.711 0.742 0.711 0.742 ns
LVCMOS15_F_8 0.368 0.414 0.445 0.414 0.445 0.500 0.518 0.538 0.518 0.538 0.635 0.686 0.703 0.686 0.703 ns
LVCMOS15_M_12 0.368 0.414 0.445 0.414 0.445 0.607 0.607 0.644 0.607 0.644 0.637 0.637 0.676 0.637 0.676 ns
LVCMOS15_M_2 0.368 0.414 0.445 0.414 0.445 0.736 0.741 0.770 0.741 0.770 0.929 0.938 0.962 0.938 0.962 ns
LVCMOS15_M_4 0.368 0.414 0.445 0.414 0.445 0.610 0.625 0.651 0.625 0.651 0.733 0.754 0.786 0.754 0.786 ns
LVCMOS15_M_6 0.368 0.414 0.445 0.414 0.445 0.564 0.576 0.604 0.576 0.604 0.655 0.674 0.710 0.674 0.710 ns
LVCMOS15_M_8 0.368 0.414 0.445 0.414 0.445 0.565 0.568 0.601 0.568 0.601 0.634 0.639 0.681 0.639 0.681 ns
LVCMOS15_S_12 0.368 0.414 0.445 0.414 0.445 0.788 0.788 0.855 0.788 0.855 0.695 0.695 0.733 0.695 0.733 ns
LVCMOS15_S_2 0.368 0.414 0.445 0.414 0.445 0.829 0.829 0.864 0.829 0.864 1.038 1.039 1.079 1.039 1.079 ns
LVCMOS15_S_4 0.368 0.414 0.445 0.414 0.445 0.687 0.687 0.725 0.687 0.725 0.813 0.813 0.851 0.813 0.851 ns
LVCMOS15_S_6 0.368 0.414 0.445 0.414 0.445 0.671 0.671 0.710 0.671 0.710 0.726 0.726 0.763 0.726 0.763 ns
LVCMOS15_S_8 0.368 0.414 0.445 0.414 0.445 0.704 0.704 0.755 0.704 0.755 0.721 0.721 0.758 0.721 0.758 ns
LVCMOS18_F_12 0.352 0.418 0.445 0.418 0.445 0.564 0.573 0.601 0.573 0.601 0.696 0.731 0.769 0.731 0.769 ns
LVCMOS18_F_2 0.352 0.418 0.445 0.418 0.445 0.723 0.739 0.760 0.739 0.760 0.918 0.945 0.971 0.945 0.971 ns
LVCMOS18_F_4 0.352 0.418 0.445 0.418 0.445 0.598 0.609 0.630 0.609 0.630 0.749 0.778 0.802 0.778 0.802 ns
LVCMOS18_F_6 0.352 0.418 0.445 0.418 0.445 0.598 0.603 0.633 0.603 0.633 0.781 0.781 0.808 0.781 0.808 ns
LVCMOS18_F_8 0.352 0.418 0.445 0.418 0.445 0.567 0.573 0.600 0.573 0.600 0.712 0.733 0.767 0.733 0.767 ns
LVCMOS18_M_12 0.352 0.418 0.445 0.418 0.445 0.640 0.640 0.678 0.640 0.678 0.670 0.670 0.709 0.670 0.709 ns
LVCMOS18_M_2 0.352 0.418 0.445 0.418 0.445 0.785 0.798 0.822 0.798 0.822 0.986 0.991 1.016 0.991 1.016 ns
LVCMOS18_M_4 0.352 0.418 0.445 0.418 0.445 0.658 0.664 0.693 0.664 0.693 0.786 0.798 0.836 0.798 0.836 ns
LVCMOS18_M_6 0.352 0.418 0.445 0.418 0.445 0.625 0.629 0.663 0.629 0.663 0.727 0.735 0.775 0.735 0.775 ns
LVCMOS18_M_8 0.352 0.418 0.445 0.418 0.445 0.626 0.626 0.661 0.626 0.661 0.705 0.705 0.746 0.705 0.746 ns
LVCMOS18_S_12 0.352 0.418 0.445 0.418 0.445 0.795 0.795 0.861 0.795 0.861 0.683 0.683 0.721 0.683 0.721 ns
LVCMOS18_S_2 0.352 0.418 0.445 0.418 0.445 0.861 0.862 0.897 0.862 0.897 1.061 1.076 1.098 1.076 1.098 ns
LVCMOS18_S_4 0.352 0.418 0.445 0.418 0.445 0.716 0.716 0.758 0.716 0.758 0.829 0.829 0.872 0.829 0.872 ns
LVCMOS18_S_6 0.352 0.418 0.445 0.418 0.445 0.682 0.682 0.724 0.682 0.724 0.724 0.724 0.762 0.724 0.762 ns
LVCMOS18_S_8 0.352 0.418 0.445 0.418 0.445 0.707 0.707 0.760 0.707 0.760 0.709 0.709 0.745 0.709 0.745 ns
LVDCI_15_F 0.369 0.425 0.462 0.425 0.462 0.407 0.426 0.443 0.426 0.443 0.514 0.548 0.581 0.548 0.581 ns
LVDCI_15_M 0.369 0.425 0.462 0.425 0.462 0.549 0.553 0.582 0.553 0.582 0.632 0.645 0.685 0.645 0.685 ns
LVDCI_15_S 0.369 0.425 0.462 0.425 0.462 0.749 0.749 0.803 0.749 0.803 0.821 0.821 0.890 0.821 0.890 ns
LVDCI_18_F 0.367 0.414 0.447 0.414 0.447 0.422 0.441 0.459 0.441 0.459 0.541 0.560 0.589 0.560 0.589 ns
LVDCI_18_M 0.367 0.414 0.447 0.414 0.447 0.546 0.554 0.585 0.554 0.585 0.622 0.644 0.683 0.644 0.683 ns
LVDCI_18_S 0.367 0.414 0.447 0.414 0.447 0.760 0.760 0.818 0.760 0.818 0.837 0.837 0.899 0.837 0.899 ns
LVDS 0.508 0.539 0.620 0.539 0.620 0.626 0.626 0.662 0.626 0.662 960.447 ns
MIPI_DPHY_DCI_HS 0.305 0.386 0.415 0.386 0.415 0.489 0.502 0.522 0.502 0.522 N/A N/A N/A N/A N/A ns
MIPI_DPHY_DCI_LP 8.438 8.438 8.792 8.438 8.792 0.895 0.914 0.937 0.914 0.937 N/A N/A N/A N/A N/A ns
POD10_DCI_F 0.336 0.408 0.430 0.408 0.430 0.407 0.425 0.444 0.425 0.444 0.512 0.555 0.584 0.555 0.584 ns
POD10_DCI_M 0.336 0.408 0.430 0.408 0.430 0.533 0.542 0.571 0.542 0.571 0.618 0.640 0.681 0.640 0.681 ns
POD10_DCI_S 0.336 0.408 0.430 0.408 0.430 0.724 0.754 0.815 0.754 0.815 0.815 0.850 0.917 0.850 0.917 ns

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Product Specification 26
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 29: IOB High Performance (HP) Switching Characteristics (cont'd)

TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD

I/O Standards 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
POD10_F 0.336 0.407 0.430 0.407 0.430 0.425 0.438 0.459 0.438 0.459 0.531 0.569 0.601 0.569 0.601 ns
POD10_M 0.336 0.407 0.430 0.407 0.430 0.519 0.538 0.568 0.538 0.568 0.589 0.630 0.667 0.630 0.667 ns
POD10_S 0.336 0.407 0.430 0.407 0.430 0.752 0.766 0.821 0.766 0.821 0.821 0.836 0.894 0.836 0.894 ns
POD12_DCI_F 0.336 0.409 0.431 0.409 0.431 0.411 0.425 0.443 0.425 0.443 0.519 0.558 0.586 0.558 0.586 ns
POD12_DCI_M 0.336 0.409 0.431 0.409 0.431 0.516 0.543 0.572 0.543 0.572 0.602 0.638 0.678 0.638 0.678 ns
POD12_DCI_S 0.336 0.409 0.431 0.409 0.431 0.740 0.772 0.822 0.772 0.822 0.833 0.862 0.929 0.862 0.929 ns
POD12_F 0.336 0.409 0.431 0.409 0.431 0.438 0.455 0.476 0.455 0.476 0.549 0.595 0.626 0.595 0.626 ns
POD12_M 0.336 0.409 0.431 0.409 0.431 0.551 0.551 0.582 0.551 0.582 0.632 0.641 0.679 0.641 0.679 ns
POD12_S 0.336 0.409 0.431 0.409 0.431 0.749 0.767 0.817 0.767 0.817 0.818 0.832 0.889 0.832 0.889 ns
SLVS_400_18 0.492 0.539 0.620 0.539 0.620 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ns
SSTL12_DCI_F 0.331 0.381 0.399 0.381 0.399 0.411 0.425 0.443 0.425 0.443 0.520 0.558 0.586 0.558 0.586 ns
SSTL12_DCI_M 0.331 0.381 0.399 0.381 0.399 0.549 0.557 0.587 0.557 0.587 0.643 0.654 0.694 0.654 0.694 ns
SSTL12_DCI_S 0.331 0.381 0.399 0.381 0.399 0.754 0.754 0.803 0.754 0.803 0.842 0.842 0.908 0.842 0.908 ns
SSTL12_F 0.320 0.403 0.403 0.403 0.403 0.394 0.412 0.430 0.412 0.430 0.494 0.538 0.566 0.538 0.566 ns
SSTL12_M 0.320 0.403 0.403 0.403 0.403 0.550 0.553 0.584 0.553 0.584 0.630 0.641 0.676 0.641 0.676 ns
SSTL12_S 0.320 0.403 0.403 0.403 0.403 0.758 0.758 0.808 0.758 0.808 0.823 0.823 0.879 0.823 0.879 ns
SSTL135_DCI_F 0.341 0.366 0.399 0.366 0.399 0.392 0.411 0.428 0.411 0.428 0.494 0.537 0.565 0.537 0.565 ns
SSTL135_DCI_M 0.341 0.366 0.399 0.366 0.399 0.551 0.551 0.582 0.551 0.582 0.643 0.645 0.685 0.645 0.685 ns
SSTL135_DCI_S 0.341 0.366 0.399 0.366 0.399 0.746 0.746 0.799 0.746 0.799 0.829 0.829 0.893 0.829 0.893 ns
SSTL135_F 0.321 0.378 0.399 0.378 0.399 0.393 0.408 0.428 0.408 0.428 0.491 0.528 0.561 0.528 0.561 ns
SSTL135_M 0.321 0.378 0.399 0.378 0.399 0.548 0.555 0.585 0.555 0.585 0.621 0.641 0.679 0.641 0.679 ns
SSTL135_S 0.321 0.378 0.399 0.378 0.399 0.772 0.772 0.823 0.772 0.823 0.827 0.827 0.878 0.827 0.878 ns
SSTL15_DCI_F 0.319 0.402 0.417 0.402 0.417 0.394 0.412 0.429 0.412 0.429 0.497 0.531 0.563 0.531 0.563 ns
SSTL15_DCI_M 0.319 0.402 0.417 0.402 0.417 0.549 0.553 0.583 0.553 0.583 0.632 0.645 0.685 0.645 0.685 ns
SSTL15_DCI_S 0.319 0.402 0.417 0.402 0.417 0.768 0.768 0.822 0.768 0.822 0.847 0.847 0.912 0.847 0.912 ns
SSTL15_F 0.320 0.371 0.400 0.371 0.400 0.393 0.408 0.428 0.408 0.428 0.494 0.530 0.556 0.530 0.556 ns
SSTL15_M 0.320 0.371 0.400 0.371 0.400 0.547 0.554 0.585 0.554 0.585 0.624 0.639 0.677 0.639 0.677 ns
SSTL15_S 0.320 0.371 0.400 0.371 0.400 0.767 0.767 0.817 0.767 0.817 0.813 0.813 0.867 0.813 0.867 ns
SSTL18_I_DCI_F 0.256 0.329 0.336 0.329 0.336 0.422 0.445 0.461 0.445 0.461 0.540 0.566 0.595 0.566 0.595 ns
SSTL18_I_DCI_M 0.256 0.329 0.336 0.329 0.336 0.552 0.554 0.585 0.554 0.585 0.629 0.644 0.683 0.644 0.683 ns
SSTL18_I_DCI_S 0.256 0.329 0.336 0.329 0.336 0.762 0.762 0.818 0.762 0.818 0.837 0.837 0.899 0.837 0.899 ns
SSTL18_I_F 0.259 0.316 0.337 0.316 0.337 0.439 0.454 0.476 0.454 0.476 0.549 0.578 0.608 0.578 0.608 ns
SSTL18_I_M 0.259 0.316 0.337 0.316 0.337 0.567 0.571 0.603 0.571 0.603 0.535 0.652 0.692 0.652 0.692 ns
SSTL18_I_S 0.259 0.316 0.337 0.316 0.337 0.782 0.782 0.835 0.782 0.835 0.816 0.816 0.870 0.816 0.870 ns
SUB_LVDS 0.508 0.539 0.620 0.539 0.620 0.658 0.660 0.692 0.660 0.692 907.4 969.863 ns

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Product Specification 27
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

IOB 3-state Output Switching Characteristics

Table 30 specifies the values of TOUTBUF_DELAY_TE_PAD and TINBUF_DELAY_IBUFDIS_O.

• TOUTBUF_DELAY_TE_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad,
when 3-state is enabled (i.e., a high impedance state).
• TINBUF_DELAY_IBUFDIS_O is the IOB delay from IBUFDISABLE to O output.
• In HP I/O banks, the internal DCI termination turn-off time is always faster than TOUTBUF_DELAY_TE_PAD when
the DCITERMDISABLE pin is used.
• In HD I/O banks, the internal IN_TERM termination turn-off time is always faster than TOUTBUF_DELAY_TE_PAD
when the INTERMDISABLE pin is used.

Table 30: IOB 3-state Output Switching Characteristics

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
TOUTBUF_DELAY_TE_PAD T input to pad high-impedance for HD I/O 6.167 6.318 6.369 6.699 6.752 ns
banks
T input to pad high-impedance for HP I/O 5.330 5.330 5.341 5.330 5.341 ns
banks
TINBUF_DELAY_IBUFDIS_O IBUF turn-on time from IBUFDISABLE to O 2.266 2.266 2.430 2.266 2.430 ns
output for HD I/O banks
IBUF turn-on time from IBUFDISABLE to O 0.873 0.936 1.037 0.936 1.037 ns
output for HP I/O banks

Input Delay Measurement Methodology

The following table shows the test setup parameters used for measuring input delay.

Table 31: Input Delay Measurement Methodology

I/O Standard
Description VL1, 2 VH1, 2 VMEAS 1, 4 VREF 1, 3, 5
Attribute
LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 –
LVCMOS, LVDCI, HSLVDCI, 1.5V LVCMOS15, LVDCI_15, 0.1 1.4 0.75 –
HSLVDCI_15
LVCMOS, LVDCI, HSLVDCI, 1.8V LVCMOS18, LVDCI_18, 0.1 1.7 0.9 –
HSLVDCI_18
LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 –
LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 –
LVTTL, 3.3V LVTTL 0.1 3.2 1.65 –
HSTL (high-speed transceiver logic), class I, 1.2V HSTL_I_12 VREF – 0.25 VREF + 0.25 VREF 0.6
HSTL, class I, 1.5V HSTL_I VREF – 0.325 VREF + 0.325 VREF 0.75
HSTL, class I, 1.8V HSTL_I_18 VREF – 0.4 VREF + 0.4 VREF 0.9
HSUL (high-speed unterminated logic), 1.2V HSUL_12 VREF – 0.25 VREF + 0.25 VREF 0.6
SSTL12 (stub series terminated logic), 1.2V SSTL12 VREF – 0.25 VREF + 0.25 VREF 0.6

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Product Specification 28
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 31: Input Delay Measurement Methodology (cont'd)

I/O Standard
Description VL1, 2 VH1, 2 VMEAS 1, 4 VREF 1, 3, 5
Attribute
SSTL135 and SSTL135 class II, 1.35V SSTL135, SSTL135_II VREF – 0.2875 VREF + 0.2875 VREF 0.675
SSTL15 and SSTL15 class II, 1.5V SSTL15, SSTL15_II VREF – 0.325 VREF + 0.325 VREF 0.75
SSTL18, class I and II, 1.8V SSTL18_I, SSTL18_II VREF – 0.4 VREF + 0.4 VREF 0.9
POD10, 1.0V POD10 VREF – 0.2 VREF + 0.2 VREF 0.7
POD12, 1.2V POD12 VREF – 0.24 VREF + 0.24 VREF 0.84
DIFF_HSTL, class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.25 0.6 + 0.25 06 –
DIFF_HSTL, class I, 1.5V DIFF_HSTL_I 0.75 – 0.325 0.75 + 0.325 06 –
DIFF_HSTL, class I, 1.8V DIFF_HSTL_I_18 0.9 – 0.4 0.9 + 0.4 06 –
DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.25 0.6 + 0.25 06 –
DIFF_SSTL, 1.2V DIFF_SSTL12 0.6 – 0.25 0.6 + 0.25 06 –
DIFF_SSTL135 and DIFF_SSTL135 class II, 1.35V DIFF_SSTL135, 0.675 – 0.2875 0.675 + 0.2875 06 –
DIFF_SSTL135_II
DIFF_SSTL15 and DIFF_SSTL15 class II, 1.5V DIFF_SSTL15, 0.75 – 0.325 0.75 + 0.325 06 –
DIFF_SSTL15_II
DIFF_SSTL18_I, DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I, 0.9 – 0.4 0.9 + 0.4 06 –
DIFF_SSTL18_II
DIFF_POD10, 1.0V DIFF_POD10 0.5 – 0.2 0.5 + 0.2 06 –
DIFF_POD12, 1.2V DIFF_POD12 0.6 – 0.25 0.6 + 0.25 06 –
LVDS (low-voltage differential signaling), 1.8V LVDS 0.9 – 0.125 0.9 + 0.125 06 –
LVDS_25, 2.5V LVDS_25 1.25 – 0.125 1.25 + 0.125 06 –
SUB_LVDS, 1.8V SUB_LVDS 0.9 – 0.125 0.9 + 0.125 06 –
SLVS, 1.8V SLVS_400_18 0.9 – 0.125 0.9 + 0.125 06 –
SLVS, 2.5V SLVS_400_25 1.25 – 0.125 1.25 + 0.125 06 –
LVPECL, 2.5V LVPECL 1.25 – 0.125 1.25 + 0.125 06 –
MIPI D-PHY (high speed) 1.2V MIPI_DPHY_DCI_HS 0.2 – 0.125 0.2 + 0.125 06 –
MIPI D-PHY (low power) 1.2V MIPI_DPHY_DCI_LP 0.715 – 0.2 0.715 + 0.2 06 –
Notes:

1. The input delay measurement methodology parameters for LVDCI/HSLVDCI are the same for LVCMOS standards of the same voltage.
Parameters for all other DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between VL and VH.
3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements.
VREF values listed are typical.
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the VREF/VMEAS parameters found in IBIS models and/or noted in Figure 1.
6. The value given is the differential input voltage.

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Product Specification 29
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Output Delay Measurement Methodology

Output delays are measured with short output traces. Standard termination was used for all testing. The
propagation delay of the trace is characterized separately and subtracted from the final measurement, and is
therefore not included in the generalized test setups shown in Figure 1 and Figure 2.

Figure 1: Single-Ended Test Setup

VREF

Output RREF

VMEAS (voltage level when taking delay measurement)

CREF (probe capacitance)

X16654-072117

Figure 2: Differential Test Setup

Output
+

CREF RREF VMEAS

X16640-072117

Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most
accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using
this method:

1. Simulate the output driver of choice into the generalized test setup using values from Table 32.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation
delay of the PCB trace.

Table 32: Output Delay Measurement Methodology

RREF CREF1 VMEAS VREF

Description I/O Standard Attribute
(Ω) (pF) (V) (V)
LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0

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Product Specification 30
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 32: Output Delay Measurement Methodology (cont'd)

RREF CREF1 VMEAS VREF

Description I/O Standard Attribute
(Ω) (pF) (V) (V)
LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0
LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0
LVTTL, 3.3V LVTTL 1M 0 1.65 0
LVDCI, HSLVDCI, 1.5V LVDCI_15, HSLVDCI_15 50 0 VREF 0.75
LVDCI, HSLVDCI, 1.8V LVDCI_15, HSLVDCI_18 50 0 VREF 0.9
HSTL (high-speed transceiver logic), class I, 1.2V HSTL_I_12 50 0 VREF 0.6
HSTL, class I, 1.5V HSTL_I 50 0 VREF 0.75
HSTL, class I, 1.8V HSTL_I_18 50 0 VREF 0.9
HSUL (high-speed unterminated logic), 1.2V HSUL_12 50 0 VREF 0.6
SSTL12 (stub series terminated logic), 1.2V SSTL12 50 0 VREF 0.6
SSTL135 and SSTL135 class II, 1.35V SSTL135, SSTL135_II 50 0 VREF 0.675
SSTL15 and SSTL15 class II, 1.5V SSTL15, SSTL15_II 50 0 VREF 0.75
SSTL18, class I and class II, 1.8V SSTL18_I, SSTL18_II 50 0 VREF 0.9
POD10, 1.0V POD10 50 0 VREF 1.0
POD12, 1.2V POD12 50 0 VREF 1.2
DIFF_HSTL, class I, 1.2V DIFF_HSTL_I_12 50 0 VREF 0.6
DIFF_HSTL, class I, 1.5V DIFF_HSTL_I 50 0 VREF 0.75
DIFF_HSTL, class I, 1.8V DIFF_HSTL_I_18 50 0 VREF 0.9
DIFF_HSUL, 1.2V DIFF_HSUL_12 50 0 VREF 0.6
DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 VREF 0.6
DIFF_SSTL135 and DIFF_SSTL135 class II, 1.35V DIFF_SSTL135, DIFF_SSTL135_II 50 0 VREF 0.675
DIFF_SSTL15 and DIFF_SSTL15 class II, 1.5V DIFF_SSTL15, DIFF_SSTL15_II 50 0 VREF 0.75
DIFF_SSTL18, class I and II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 VREF 0.9
DIFF_POD10, 1.0V DIFF_POD10 50 0 VREF 1.0
DIFF_POD12, 1.2V DIFF_POD12 50 0 VREF 1.2
LVDS (low-voltage differential signaling), 1.8V LVDS 100 0 02 0
SUB_LVDS, 1.8V SUB_LVDS 100 0 02 0
MIPI D-PHY (high speed) 1.2V MIPI_DPHY_DCI_HS 100 0 02 0
MIPI D-PHY (low power) 1.2V MIPI_DPHY_DCI_LP 1M 0 0.6 0
Notes:

1. CREF is the capacitance of the probe, nominally 0 pF.

2. The value given is the differential output voltage.

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Product Specification 31
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Block RAM and FIFO Switching Characteristics

Table 33: Block RAM and FIFO Switching Characteristics

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
Maximum Frequency
FMAX_WF_NC Block RAM (WRITE_FIRST and NO_CHANGE modes) 825 738 645 585 516 MHz
FMAX_RF Block RAM (READ_FIRST mode) 718 637 575 510 460 MHz
FMAX_FIFO FIFO in all modes without ECC 825 738 645 585 516 MHz
FMAX_ECC Block RAM and FIFO in ECC configuration without 718 637 575 510 460 MHz
PIPELINE
Block RAM and FIFO in ECC configuration with 825 738 645 585 516 MHz
PIPELINE and Block RAM in WRITE_FIRST or
NO_CHANGE mode
TPW1 Minimum pulse width 495 542 543 577 578 ps
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO Clock CLK to DOUT output (without output register) 0.91 1.02 1.11 1.46 1.53 ns, Max
TRCKO_DO_REG Clock CLK to DOUT output (with output register) 0.27 0.29 0.30 0.42 0.44 ns, Max
Notes:

1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.

UltraRAM Switching Characteristics

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Kintex UltraScale+ FPGAs that
include this memory.

Table 34: UltraRAM Switching Characteristics

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
Maximum Frequency
FMAX UltraRAM maximum frequency with 650 600 575 500 481 MHz
OREG_B = True
FMAX_ECC_NOPIPELINE UltraRAM maximum frequency with 435 400 386 312 303 MHz
OREG_B = False and EN_ECC_RD_B = True
FMAX_NOPIPELINE UltraRAM maximum frequency with 528 500 478 404 389 MHz
OREG_B = False and EN_ECC_RD_B = False
TPW1 Minimum pulse width 650 700 730 800 832 ps
TRSTPW Asynchronous reset minimum pulse width. One 1 clock cycle
cycle required
Notes:

1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.

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Product Specification 32
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Input/Output Delay Switching Characteristics

Table 35: Input/Output Delay Switching Characteristics

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
FREFCLK Reference clock frequency for IDELAYCTRL 300 to 800 MHz
(component mode)
Reference clock frequency when using 300 to 800 MHz
BITSLICE_CONTROL with REFCLK (in native
mode (for RX_BITSLICE only))
Reference clock frequency for 300 to 300 to 300 to 300 to 300 to MHz
BITSLICE_CONTROL with PLL_CLK (in native 2666.67 2666.67 2400 2400 2133
mode)1
TMINPER_CLK Minimum period for IODELAY clock 3.195 3.195 3.195 3.195 3.195 ns
TMINPER_RST Minimum reset pulse width 52.00 ns
TIDELAY_RESOLUTION/ IDELAY/ODELAY chain resolution 2.1 to 12 ps
TODELAY_RESOLUTION
Notes:

1. PLL settings could restrict the minimum allowable data rate. For example, when using a PLL with CLKOUTPHY_MODE = VCO_HALF, the
minimum frequency is PLL_FVCOMIN/2.

DSP48 Slice Switching Characteristics

Table 36: DSP48 Slice Switching Characteristics

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V1 Units
-3 -2 -1 -2 -1
Maximum Frequency
FMAX With all registers used 891 775 645 644 600 MHz
FMAX_PATDET With pattern detector 794 687 571 562 524 MHz
FMAX_MULT_NOMREG Two register multiply without MREG 635 544 456 440 413 MHz
FMAX_MULT_NOMREG_PATDET Two register multiply without MREG 577 492 410 395 371 MHz
with pattern detect
FMAX_PREADD_NOADREG Without ADREG 655 565 468 453 423 MHz
FMAX_NOPIPELINEREG Without pipeline registers (MREG, 483 410 338 323 304 MHz
ADREG)
FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, 448 379 314 299 280 MHz
ADREG) with pattern detect
Notes:

1. For devices operating at the lower power VCCINT = 0.72V voltages, DSP cascades that cross the clock region center might operate below
the specified FMAX.

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Product Specification 33
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Clock Buffers and Networks

Table 37: Clock Buffers Switching Characteristics

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
Global Clock Switching Characteristics (Including BUFGCTRL)
FMAX Maximum frequency of a global clock tree (BUFG) 891 775 667 725 667 MHz
Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)
FMAX Maximum frequency of a global clock buffer with input 891 775 667 725 667 MHz
divide capability (BUFGCE_DIV)
Global Clock Buffer with Clock Enable (BUFGCE)
FMAX Maximum frequency of a global clock buffer with clock 891 775 667 725 667 MHz
enable (BUFGCE)
Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)
FMAX Maximum frequency of a leaf clock buffer with clock 891 775 667 725 667 MHz
enable (BUFCE_LEAF)
GTH or GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)
FMAX Maximum frequency of a serial transceiver clock buffer 512 512 512 512 512 MHz
with clock enable and clock input divide capability

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Product Specification 34
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

MMCM Switching Characteristics

Table 38: MMCM Specification

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
MMCM_FINMAX Maximum input clock frequency 1066 933 800 933 800 MHz
MMCM_FINMIN Minimum input clock frequency 10 10 10 10 10 MHz
MMCM_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max
MMCM_FINDUTY Input duty cycle range: 10–49 MHz 25–75 %
Input duty cycle range: 50–199 MHz 30–70 %
Input duty cycle range: 200–399 MHz 35–65 %
Input duty cycle range: 400–499 MHz 40–60 %
Input duty cycle range: >500 MHz 45–55 %
MMCM_FMIN_PSCLK Minimum dynamic phase shift clock frequency 0.01 0.01 0.01 0.01 0.01 MHz
MMCM_FMAX_PSCLK Maximum dynamic phase shift clock 550 500 450 500 450 MHz
frequency
MMCM_FVCOMIN Minimum MMCM VCO frequency 800 800 800 800 800 MHz
MMCM_FVCOMAX Maximum MMCM VCO frequency 1600 1600 1600 1600 1600 MHz
MMCM_FBANDWIDTH Low MMCM bandwidth at typical1 1.00 1.00 1.00 1.00 1.00 MHz
High MMCM bandwidth at typical1 4.00 4.00 4.00 4.00 4.00 MHz
MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs2 0.12 0.12 0.12 0.12 0.12 ns
MMCM_TOUTJITTER MMCM output jitter. Note 3
MMCM_TOUTDUTY MMCM output clock duty cycle precision4 0.165 0.20 0.20 0.20 0.20 ns
MMCM_TLOCKMAX MMCM maximum lock time for 100 100 100 100 100 µs
MMCM_FPFDMIN
MMCM_FOUTMAX MMCM maximum output frequency 891 775 667 725 667 MHz
MMCM_FOUTMIN MMCM minimum output frequency4, 5 6.25 6.25 6.25 6.25 6.25 MHz
MMCM_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max
MMCM_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 5.00 ns
MMCM_FPFDMAX Maximum frequency at the phase frequency 550 500 450 500 450 MHz
detector
MMCM_FPFDMIN Minimum frequency at the phase frequency 10 10 10 10 10 MHz
detector
MMCM_TFBDELAY Maximum delay in the feedback path 5 ns Max or one clock cycle
MMCM_FDPRCLK_MAX Maximum DRP clock frequency 250 250 250 250 250 MHz
Notes:

1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

PLL Switching Characteristics

Table 39: PLL Specification

Speed Grade and VCCINT Operating Voltages

Symbol Description1 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
PLL_FINMAX Maximum input clock frequency 1066 933 800 933 800 MHz
PLL_FINMIN Minimum input clock frequency 70 70 70 70 70 MHz
PLL_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max
PLL_FINDUTY Input duty cycle range: 70–399 MHz 35–65 %
Input duty cycle range: 400–499 MHz 40–60 %
Input duty cycle range: >500 MHz 45–55 %
PLL_FVCOMIN Minimum PLL VCO frequency 750 750 750 750 750 MHz
PLL_FVCOMAX Maximum PLL VCO frequency 1500 1500 1500 1500 1500 MHz
PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs2 0.12 0.12 0.12 0.12 0.12 ns
PLL_TOUTJITTER PLL output jitter. Note 3
PLL_TOUTDUTY PLL CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B 0.165 0.20 0.20 0.20 0.20 ns
duty-cycle precision4
PLL_TLOCKMAX PLL maximum lock time 100 µs
PLL_FOUTMAX PLL maximum output frequency at CLKOUT0, 891 775 667 725 667 MHz
CLKOUT0B, CLKOUT1, CLKOUT1B
PLL maximum output frequency at CLKOUTPHY 2667 2667 2400 2400 2133 MHz
PLL_FOUTMIN PLL minimum output frequency at CLKOUT0, 5.86 5.86 5.86 5.86 5.86 MHz
CLKOUT0B, CLKOUT1, CLKOUT1B5
PLL minimum output frequency at CLKOUTPHY 2 x VCO mode: 1500, 1 x VCO mode: 750, 0.5 x VCO mode: MHz
375
PLL_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 5.00 ns
PLL_FPFDMAX Maximum frequency at the phase frequency 667.5 667.5 667.5 667.5 667.5 MHz
detector
PLL_FPFDMIN Minimum frequency at the phase frequency 70 70 70 70 70 MHz
detector
PLL_FBANDWIDTH PLL bandwidth at typical 14 14 14 14 14 MHz
PLL_FDPRCLK_MAX Maximum DRP clock frequency 250 250 250 250 250 MHz
Notes:

1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.

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Product Specification 36
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Device Pin-to-Pin Output Parameter Guidelines

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the
device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the
Vivado Design Suite timing report for the actual pin-to-pin values.

Table 40: Global Clock Input to Output Delay Without MMCM (Near Clock Region)

Speed Grade and VCCINT Operating

Voltages
Symbol Description1 Device Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM
TICKOF Global clock input and output flip-flop XCKU3P 4.65 5.09 5.48 6.37 6.84 ns
without MMCM (near clock region)
XCKU5P 4.65 5.09 5.48 6.37 6.84 ns
XCKU9P 5.42 5.91 6.35 7.48 8.03 ns
XCKU11P 5.92 6.49 6.96 8.16 8.91 ns
XCKU13P 5.58 6.09 6.55 7.75 8.33 ns
XCKU15P 6.29 6.90 7.40 8.68 9.32 ns
Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible I/O and CLB flip-flops are clocked by the global clock net.

Table 41: Global Clock Input to Output Delay Without MMCM (Far Clock Region)

Speed Grade and VCCINT Operating Voltages

Symbol Description1 Device 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM
TICKOF_FAR Global clock input and output flip-flop XCKU3P 4.84 5.30 5.70 6.64 7.14 ns
without MMCM (far clock region)
XCKU5P 4.84 5.30 5.70 6.64 7.14 ns
XCKU9P 5.91 6.49 6.97 8.16 8.76 ns
XCKU11P 6.29 6.91 7.41 8.72 9.52 ns
XCKU13P 5.90 6.49 6.96 8.16 8.77 ns
XCKU15P 6.84 7.53 8.07 9.52 10.23 ns
Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible I/O and CLB flip-flops are clocked by the global clock net.

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Product Specification 37
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 42: Global Clock Input to Output Delay With MMCM

Speed Grade and VCCINT Operating

Voltages
Symbol Description1, 2 Device Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
TICKOFMMCMCC Global clock input and output flip-flop with XCKU3P 1.67 1.98 2.17 2.59 2.74 ns
MMCM
XCKU5P 1.67 1.98 2.17 2.59 2.74 ns
XCKU9P 1.83 2.15 2.36 2.80 2.95 ns
XCKU11P 1.96 2.30 2.51 2.99 3.20 ns
XCKU13P 1.85 2.18 2.38 2.82 2.98 ns
XCKU15P 2.08 2.44 2.66 3.15 3.33 ns
Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible I/O and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.

Table 43: Source Synchronous Output Characteristics (Component Mode)

Speed Grade and VCCINT Operating Voltages

Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
TOUTPUT_LOGIC_DELAY_VARIATION 1 80 ps
Notes:

1. Delay mismatch across a transmit bus when using component mode output logic (ODDRE1, OSERDESE3) within a bank.

Device Pin-to-Pin Input Parameter Guidelines

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the
device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the
Vivado Design Suite timing report for the actual pin-to-pin values.

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 44: Global Clock Input Setup and Hold With 3.3V HD I/O Without MMCM

Speed Grade and VCCINT Operating

Voltages
Symbol Description Device Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.1, 2, 3
TPSFD_KU3P Global clock input and input Setup XCKU3P 1.98 2.28 2.38 3.55 3.83 ns
flip-flop (or latch) without
TPHFD_KU3P MMCM Hold –0.36 –0.36 –0.36 –1.04 –1.04 ns
TPSFD_KU5P Setup XCKU5P 1.98 2.28 2.38 3.55 3.83 ns
TPHFD_KU5P Hold –0.36 –0.36 –0.36 –1.04 –1.04 ns
TPSFD_KU9P Setup XCKU9P 1.51 1.79 1.86 2.85 3.06 ns
TPHFD_KU9P Hold –0.05 –0.05 –0.05 –0.60 –0.60 ns
TPSFD_KU11P Setup XCKU11P 1.99 2.28 2.38 3.54 3.79 ns
TPHFD_KU11P Hold –0.38 –0.38 –0.38 –1.05 –1.05 ns
TPSFD_KU13P Setup XCKU13P 1.51 1.79 1.85 2.84 3.05 ns
TPHFD_KU13P Hold –0.04 –0.04 –0.04 –0.60 –0.60 ns
TPSFD_KU15P Setup XCKU15P 2.00 2.29 2.38 3.56 3.83 ns
TPHFD_KU15P Hold –0.38 –0.38 –0.38 –1.08 –1.08 ns
Notes:

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the
global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible I/O and CLB flip-flops are clocked by the global clock net.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

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Product Specification 39
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 45: Global Clock Input Setup and Hold With MMCM

Speed Grade and VCCINT Operating

Voltages
Symbol Description Device Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.1, 2, 3
TPSMMCMCC_KU3P Global clock input and input Setup XCKU3P 2.04 2.04 2.16 2.04 2.16 ns
flip-flop (or latch) with MMCM
TPHMMCMCC_KU3P Hold –0.17 –0.17 –0.17 –0.23 –0.23 ns
TPSMMCMCC_KU5P Setup XCKU5P 2.04 2.04 2.16 2.04 2.16 ns
TPHMMCMCC_KU5P Hold –0.17 –0.17 –0.17 –0.23 –0.23 ns
TPSMMCMCC_KU9P Setup XCKU9P 2.00 2.00 2.12 2.00 2.12 ns
TPHMMCMCC_KU9P Hold –0.11 –0.11 –0.11 –0.18 –0.18 ns
TPSMMCMCC_KU11P Setup XCKU11P 1.89 1.89 2.02 1.89 2.02 ns
TPHMMCMCC_KU11P Hold –0.20 –0.20 –0.20 –0.25 –0.25 ns
TPSMMCMCC_KU13P Setup XCKU13P 1.99 1.99 2.12 1.99 2.12 ns
TPHMMCMCC_KU13P Hold –0.10 –0.10 –0.10 –0.16 –0.16 ns
TPSMMCMCC_KU15P Setup XCKU15P 1.89 1.89 2.03 1.89 2.03 ns
TPHMMCMCC_KU15P Hold –0.16 –0.16 –0.16 –0.23 –0.23 ns
Notes:

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the
global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible I/O and CLB flip-flops are clocked by the global clock net.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

Table 46: Sampling Window

Speed Grade and VCCINT Operating Voltages

Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
TSAMP_BUFG1 510 610 610 610 610 ps
TSAMP_NATIVE_DPA 2 100 100 125 125 150 ps
TSAMP_NATIVE_BISC 3 60 60 85 85 110 ps
Notes:

1. This parameter indicates the total sampling error of the Kintex UltraScale+ FPGA DDR input registers, measured across voltage,
temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation.
These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These
measurements do not include package or clock tree skew.
2. This parameter is the receive sampling error for RX_BITSLICE when using dynamic phase alignment.
3. This parameter is the receive sampling error for RX_BITSLICE when using built-in self-calibration (BISC).

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 47: Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)

Speed Grade and VCCINT Operating Voltages

Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
TINPUT_LOGIC_UNCERTAINTY1 40 ps
TCAL_ERROR2 24 ps
Notes:

1. Input_logic_uncertainty accounts for the setup/hold and any pattern dependent jitter for the input logic (input register, IDDRE1, or
ISERDESE3).
2. Calibration error associated with quantization effects based on the IDELAY resolution. Calibration must be performed for each input pin
to ensure optimal performance.

Package Parameter Guidelines

The parameters in this section provide the necessary values for calculating timing budgets for clock transmitter
and receiver data-valid windows.

Table 48: Package Skew

Symbol Description Device Package Value Units

PKGSKEW Package Skew1, 2 XCKU3P SFVB784 75 ps
FFVA676 136 ps
FFVB676 69 ps
FFVD900 179 ps
XCKU5P SFVB784 75 ps
FFVA676 136 ps
FFVB676 69 ps
FFVD900 179 ps
XCKU9P FFVE900 212 ps
XCKU11P FFVD900 146 ps
FFVA1156 170 ps
FFVE1517 178 ps
XCKU13P FFVE900 197 ps
XCKU15P FFVA1156 203 ps
FFVE1517 167 ps
FFVA1760 191 ps
FFVE1760 172 ps
Notes:

1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from
die pad to ball.
2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.

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Product Specification 41
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

GTH Transceiver Specifications

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Kintex UltraScale+ FPGAs that
include the GTH transceivers.

GTH Transceiver DC Input and Output Levels

The following table summarizes the DC specifications of the GTH transceivers in Kintex UltraScale+ FPGAs.
Consult the UltraScale Architecture GTH Transceivers User Guide (UG576) for further details.

Table 49: GTH Transceiver DC Specifications

Symbol DC Parameter Conditions Min Typ Max Units

DVPPIN Differential peak-to-peak input voltage >10.3125 Gb/s 150 – 1250 mV
(external AC coupled)
6.6 Gb/s to 10.3125 Gb/s 150 – 1250 mV
≤ 6.6 Gb/s 150 – 2000 mV
VIN Single-ended input voltage. Voltage DC coupled VMGTAVTT = 1.2V –400 – VMGTAVTT mV
measured at the pin referenced to
GND
VCMIN Common mode input voltage DC coupled VMGTAVTT = 1.2V – 2/3 VMGTAVTT – mV
DVPPOUT Differential peak-to-peak output Transmitter output swing is set to 800 – – mV
voltage1 11111

VCMOUTDC Common mode output voltage: DC When remote RX is terminated to VMGTAVTT/2 – DVPPOUT/4 mV
coupled (equation based) GND
When remote RX termination is VMGTAVTT – DVPPOUT/2 mV
floating
When remote RX is terminated to mV
VRX_TERM2

VCMOUTAC Common mode output voltage: AC coupled (equation based) VMGTAVTT – DVPPOUT/2 mV
RIN Differential input resistance – 100 – Ω
ROUT Differential output resistance – 100 – Ω
TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew (all packages) – – 10 ps
CEXT Recommended external AC coupling capacitor3 – 100 – nF
Notes:

1. The output swing and pre-emphasis levels are programmable using the attributes discussed in the UltraScale Architecture GTH
Transceivers User Guide (UG576), and can result in values lower than reported in this table.
2. VRX_TERM is the remote RX termination voltage.
3. Other values can be used as appropriate to conform to specific protocols and standards.

Figure 3: Single-Ended Peak-to-Peak Voltage

+V P
Single-Ended
Peak-to-Peak
N Voltage
0

X16653-072117

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Product Specification 42
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Figure 4: Differential Peak-to-Peak Voltage

+V

Differential
0 Peak-to-Peak
Voltage

–V P–N
Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2
X16639-072117

Table 50 and Table 51 summarize the DC specifications of the GTH transceivers input and output clocks in
Kintex UltraScale+ FPGAs. Consult the UltraScale Architecture GTH Transceivers User Guide (UG576) for further
details.

Table 50: GTH Transceiver Clock Input Level Specification

Symbol DC Parameter Min Typ Max Units

VIDIFF Differential peak-to-peak input voltage 250 – 2000 mV
RIN Differential input resistance – 100 – Ω
CEXT Required external AC coupling capacitor – 10 – nF

Table 51: GTH Transceiver Clock Output Level Specification

Symbol Description Conditions Min Typ Max Units

VOL Output Low voltage for P and N RT = 100Ω across P and N signals 100 – 330 mV
VOH Output High voltage for P and N RT = 100Ω across P and N signals 500 – 700 mV
VDDOUT Differential output voltage (P–N), P = RT = 100Ω across P and N signals 300 – 430 mV
High (N–P), N = High
VCMOUT Common mode voltage RT = 100Ω across P and N signals 300 – 500 mV

GTH Transceiver Switching Characteristics

Consult the UltraScale Architecture GTH Transceivers User Guide (UG576) for further information.

Table 52: GTH Transceiver Performance

Speed Grade and VCCINT Operating Voltages

Output
Symbol Description 0.90V 0.85V 0.72V Units
Divider
-3 -2 -1 -2 -1
FGTHMAX GTH maximum line rate 16.375 16.375 12.5 12.5 10.3125 Gb/s
FGTHMIN GTH minimum line rate 0.5 0.5 0.5 0.5 0.5 Gb/s
Min Max Min Max Min Max Min Max Min Max
FGTHCRANGE CPLL line rate 1 4 12.5 4 12.5 4 8.5 4 8.5 4 8.5 Gb/s
range1
2 2 6.25 2 6.25 2 4.25 2 4.25 2 4.25 Gb/s
4 1 3.125 1 3.125 1 2.125 1 2.125 1 2.125 Gb/s
8 0.5 1.5625 0.5 1.5625 0.5 1.0625 0.5 1.0625 0.5 1.0625 Gb/s
16 N/A Gb/s

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 52: GTH Transceiver Performance (cont'd)

Speed Grade and VCCINT Operating Voltages

Output
Symbol Description 0.90V 0.85V 0.72V Units
Divider
-3 -2 -1 -2 -1
Min Max Min Max Min Max Min Max Min Max
FGTHQRANGE1 QPLL0 line rate 1 9.8 16.375 9.8 16.375 9.8 12.5 9.8 12.5 9.8 10.3125 Gb/s
range2
2 4.9 8.1875 4.9 8.1875 4.9 8.15 4.9 8.1875 4.9 8.15 Gb/s
4 2.45 4.0938 2.45 4.0938 2.45 4.075 2.45 4.0938 2.45 4.075 Gb/s
8 1.225 2.0469 1.225 2.0469 1.225 2.0375 1.225 2.0469 1.225 2.0375 Gb/s
16 0.6125 1.0234 0.6125 1.0234 0.6125 1.0188 0.6125 1.0234 0.6125 1.0188 Gb/s
Min Max Min Max Min Max Min Max Min Max
FGTHQRANGE2 QPLL1 line rate 1 8.0 13.0 8.0 13.0 8.0 12.5 8.0 12.5 8.0 10.3125 Gb/s
range3
2 4.0 6.5 4.0 6.5 4.0 6.5 4.0 6.5 4.0 6.5 Gb/s
4 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 Gb/s
8 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 Gb/s
16 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 Gb/s
Min Max Min Max Min Max Min Max Min Max
FCPLLRANGE CPLL frequency range 2 6.25 2 6.25 2 4.25 2 4.25 2 4.25 GHz
FQPLL0RANGE QPLL0 frequency range 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 GHz
FQPLL1RANGE QPLL1 frequency range 8 13 8 13 8 13 8 13 8 13 GHz
Notes:

1. The values listed are the rounded results of the calculated equation (2 × CPLL_Frequency)/Output_Divider.
2. The values listed are the rounded results of the calculated equation (QPLL0_Frequency)/Output_Divider.
3. The values listed are the rounded results of the calculated equation (QPLL1_Frequency)/Output_Divider.

Table 53: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics

Symbol Description All Speed Grades Units

FGTHDRPCLK GTHDRPCLK maximum frequency 250 MHz

Table 54: GTH Transceiver Reference Clock Switching Characteristics

All Speed Grades

Symbol Description Conditions Units
Min Typ Max
FGCLK Reference clock frequency range 60 – 820 MHz
TRCLK Reference clock rise time 20% – 80% – 200 – ps
TFCLK Reference clock fall time 80% – 20% – 200 – ps
TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 %

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 55: GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask

Offset
Symbol Description Min Typ Max Units
Frequency
QPLLREFCLKMASK1, 2 QPLL0/QPLL1 reference clock select phase noise 10 kHz – – –105 dBc/Hz
mask at REFCLK frequency = 312.5 MHz
100 kHz – – –124
1 MHz – – –130
CPLLREFCLKMASK1, 2 CPLL reference clock select phase noise mask at 10 kHz – – –105 dBc/Hz
REFCLK frequency = 312.5 MHz
100 kHz – – –124
1 MHz – – –130
50 MHz – – –140
Notes:

1. For reference clock frequencies other than 312.5 MHz, adjust the phase-noise mask values by 20 × Log(N/312.5) where N is the new
reference clock frequency in MHz.
2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol,
e.g., PCIe.

Table 56: GTH Transceiver PLL/Lock Time Adaptation

All Speed Grades

Symbol Description Conditions Units
Min Typ Max
TLOCK Initial PLL lock – – 1 ms
TDLOCK Clock recovery phase acquisition and After the PLL is locked to the – 50,000 37 x 106 UI
adaptation time for decision feedback reference clock, this is the time
equalizer (DFE) it takes to lock the clock data
recovery (CDR) to the data
Clock recovery phase acquisition and present at the input. – 50,000 2.3 x 106 UI
adaptation time for low-power mode (LPM)
when the DFE is disabled

Table 57: GTH Transceiver User Clock Switching Characteristics

Data Width Conditions Speed Grade and VCCINT Operating Voltages

(Bit) 0.90V 0.85V 0.72V
Symbol Description1 Units
Internal Interconnect
-32 -22, 3 -14, 5 -23 -15
Logic Logic
FTXOUTPMA TXOUTCLK maximum frequency sourced from 511.719 511.719 390.625 390.625 322.266 MHz
OUTCLKPMA
FRXOUTPMA RXOUTCLK maximum frequency sourced from 511.719 511.719 390.625 390.625 322.266 MHz
OUTCLKPMA
FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from 511.719 511.719 511.719 511.719 511.719 MHz
TXPROGDIVCLK
FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from 511.719 511.719 511.719 511.719 511.719 MHz
RXPROGDIVCLK
FTXIN TXUSRCLK6 16 16, 32 511.719 511.719 390.625 390.625 322.266 MHz
maximum
frequency 32 32, 64 511.719 511.719 390.625 390.625 322.266 MHz
20 20, 40 409.375 409.375 312.500 312.500 257.813 MHz
40 40, 80 409.375 409.375 312.500 312.500 257.813 MHz

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 57: GTH Transceiver User Clock Switching Characteristics (cont'd)

Data Width Conditions Speed Grade and VCCINT Operating Voltages

(Bit) 0.90V 0.85V 0.72V
Symbol Description1 Units
Internal Interconnect
-32 -22, 3 -14, 5 -23 -15
Logic Logic
FRXIN RXUSRCLK6 16 16, 32 511.719 511.719 390.625 390.625 322.266 MHz
maximum
frequency 32 32, 64 511.719 511.719 390.625 390.625 322.266 MHz
20 20, 40 409.375 409.375 312.500 312.500 257.813 MHz
40 40, 80 409.375 409.375 312.500 312.500 257.813 MHz
FTXIN2 TXUSRCLK26 16 16 511.719 511.719 390.625 390.625 322.266 MHz
maximum
frequency 16 32 255.859 255.859 195.313 195.313 161.133 MHz
32 32 511.719 511.719 390.625 390.625 322.266 MHz
32 64 255.859 255.859 195.313 195.313 161.133 MHz
20 20 409.375 409.375 312.500 312.500 257.813 MHz
20 40 204.688 204.688 156.250 156.250 128.906 MHz
40 40 409.375 409.375 312.500 312.500 257.813 MHz
40 80 204.688 204.688 156.250 156.250 128.906 MHz
FRXIN2 RXUSRCLK26 16 16 511.719 511.719 390.625 390.625 322.266 MHz
maximum
frequency 16 32 255.859 255.859 195.313 195.313 161.133 MHz
32 32 511.719 511.719 390.625 390.625 322.266 MHz
32 64 255.859 255.859 195.313 195.313 161.133 MHz
20 20 409.375 409.375 312.500 312.500 257.813 MHz
20 40 204.688 204.688 156.250 156.250 128.906 MHz
40 40 409.375 409.375 312.500 312.500 257.813 MHz
40 80 204.688 204.688 156.250 156.250 128.906 MHz
Notes:

1. Clocking must be implemented as described in UltraScale Architecture GTH Transceivers User Guide (UG576).
2. For speed grades -3E, -2E, and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s.
3. For speed grade -2LE, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s when VCCINT = 0.85V or
6.25 Gb/s when VCCINT = 0.72V.
4. For speed grades -1E and -1I, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s.
5. For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when VCCINT = 0.85V or
5.15625 Gb/s when VCCINT = 0.72V.
6. When the gearbox is used, these maximums refer to the XCLK. For more information, see the UltraScale Architecture GTH Transceivers User
Guide (UG576).

Table 58: GTH Transceiver Transmitter Switching Characteristics

Symbol Description Condition Min Typ Max Units

FGTHTX Serial data rate range 0.500 – FGTHMAX Gb/s
TRTX TX rise time 20%–80% – 21 – ps
TFTX TX fall time 80%–20% – 21 – ps
TLLSKEW TX lane-to-lane skew1 – – 500.00 ps
TJ16.375 Total jitter2, 4 16.375 Gb/s – – 0.28 UI
DJ16.375 Deterministic jitter2, 4 – – 0.17 UI

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Table 58: GTH Transceiver Transmitter Switching Characteristics (cont'd)

Symbol Description Condition Min Typ Max Units

TJ15.0 Total jitter2, 4 15.0 Gb/s – – 0.28 UI
DJ15.0 Deterministic jitter2, 4 – – 0.17 UI
TJ14.1 Total jitter2, 4 14.1 Gb/s – – 0.28 UI
DJ14.1 Deterministic jitter2, 4 – – 0.17 UI
TJ14.1 Total jitter2, 4 14.025 Gb/s – – 0.28 UI
DJ14.1 Deterministic jitter2, 4 – – 0.17 UI
TJ13.1 Total jitter2, 4 13.1 Gb/s – – 0.28 UI
DJ13.1 Deterministic jitter2, 4 – – 0.17 UI
TJ12.5_QPLL Total jitter2, 4 12.5 Gb/s – – 0.28 UI
DJ12.5_QPLL Deterministic jitter2, 4 – – 0.17 UI
TJ12.5_CPLL Total jitter3, 4 12.5 Gb/s – – 0.33 UI
DJ12.5_CPLL Deterministic jitter3, 4 – – 0.17 UI
TJ11.3_QPLL Total jitter2, 4 11.3 Gb/s – – 0.28 UI
DJ11.3_QPLL Deterministic jitter2, 4 – – 0.17 UI
TJ10.3125_QPLL Total jitter2, 4 10.3125 Gb/s – – 0.28 UI
DJ10.3125_QPLL Deterministic jitter2, 4 – – 0.17 UI
TJ10.3125_CPLL Total jitter3, 4 10.3125 Gb/s – – 0.33 UI
DJ10.3125_CPLL Deterministic jitter3, 4 – – 0.17 UI
TJ9.953_QPLL Total jitter2, 4 9.953 Gb/s – – 0.28 UI
DJ9.953_QPLL Deterministic jitter2, 4 – – 0.17 UI
TJ9.953_CPLL Total jitter3, 4 9.953 Gb/s – – 0.33 UI
DJ9.953_CPLL Deterministic jitter3, 4 – – 0.17 UI
TJ8.0 Total jitter3, 4 8.0 Gb/s – – 0.32 UI
DJ8.0 Deterministic jitter3, 4 – – 0.17 UI
TJ6.6 Total jitter3, 4 6.6 Gb/s – – 0.30 UI
DJ6.6 Deterministic jitter3, 4 – – 0.15 UI
TJ5.0 Total jitter3, 4 5.0 Gb/s – – 0.30 UI
DJ5.0 Deterministic jitter3, 4 – – 0.15 UI
TJ4.25 Total jitter3, 4 4.25 Gb/s – – 0.30 UI
DJ4.25 Deterministic jitter3, 4 – – 0.15 UI
TJ4.0 Total jitter3, 4 4.0 Gb/s – – 0.32 UI
DJ4.0 Deterministic jitter3, 4 – – 0.16 UI
TJ3.20 Total jitter3, 4 3.20 Gb/s5 – – 0.20 UI
DJ3.20 Deterministic jitter3, 4 – – 0.10 UI
TJ2.5 Total jitter3, 4 2.5 Gb/s6 – – 0.20 UI
DJ2.5 Deterministic jitter3, 4 – – 0.10 UI
TJ1.25 Total jitter3, 4 1.25 Gb/s7 – – 0.15 UI
DJ1.25 Deterministic jitter3, 4 – – 0.06 UI

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Table 58: GTH Transceiver Transmitter Switching Characteristics (cont'd)

Symbol Description Condition Min Typ Max Units

TJ500 Total jitter3, 4 500 Mb/s8 – – 0.10 UI
DJ500 Deterministic jitter3, 4 – – 0.03 UI
Notes:

1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTH Quad) at
the maximum line rate.
2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
4. All jitter values are based on a bit-error ratio of 10–12.
5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
8. CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.

Table 59: GTH Transceiver Receiver Switching Characteristics

Symbol Description Condition Min Typ Max Units

FGTHRX Serial data rate 0.500 – FGTHMAX Gb/s
RXSST Receiver spread-spectrum tracking1 Modulated at 33 kHz –5000 – 0 ppm
RXRL Run length (CID) – – 256 UI
RXPPMTOL Data/REFCLK PPM offset tolerance Bit rates ≤ 6.6 Gb/s –1250 – 1250 ppm
Bit rates > 6.6 Gb/s and –700 – 700 ppm
≤ 8.0 Gb/s
Bit rates > 8.0 Gb/s –200 – 200 ppm
SJ Jitter Tolerance2
JT_SJ16.375 Sinusoidal jitter (QPLL)3 16.375 Gb/s 0.30 – – UI
JT_SJ15.0 Sinusoidal jitter (QPLL)3 15.0 Gb/s 0.30 – – UI
JT_SJ14.1 Sinusoidal jitter (QPLL)3 14.1 Gb/s 0.30 – – UI
JT_SJ13.1 Sinusoidal jitter (QPLL)3 13.1 Gb/s 0.30 – – UI
JT_SJ12.5 Sinusoidal jitter (QPLL)3 12.5 Gb/s 0.30 – – UI
JT_SJ11.3 Sinusoidal jitter (QPLL)3 11.3 Gb/s 0.30 – – UI
JT_SJ10.32_QPLL Sinusoidal jitter (QPLL)3 10.32 Gb/s 0.30 – – UI
JT_SJ10.32_CPLL Sinusoidal jitter (CPLL)3 10.32 Gb/s 0.30 – – UI
JT_SJ9.953_QPLL Sinusoidal jitter (QPLL)3 9.953 Gb/s 0.30 – – UI
JT_SJ9.953_CPLL Sinusoidal jitter (CPLL)3 9.953 Gb/s 0.30 – – UI
JT_SJ8.0 Sinusoidal jitter (QPLL)3 8.0 Gb/s 0.42 – – UI
JT_SJ6.6_CPLL Sinusoidal jitter (CPLL)3 6.6 Gb/s 0.44 – – UI
JT_SJ5.0 Sinusoidal jitter (CPLL)3 5.0 Gb/s 0.44 – – UI
JT_SJ4.25 Sinusoidal jitter (CPLL)3 4.25 Gb/s 0.44 – – UI
JT_SJ3.2 Sinusoidal jitter (CPLL)3 3.2 Gb/s4 0.45 – – UI
JT_SJ2.5 Sinusoidal jitter (CPLL)3 2.5 Gb/s5 0.30 – – UI
JT_SJ1.25 Sinusoidal jitter (CPLL)3 1.25 Gb/s6 0.30 – – UI
JT_SJ500 Sinusoidal jitter (CPLL)3 500 Mb/s7 0.30 – – UI

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Table 59: GTH Transceiver Receiver Switching Characteristics (cont'd)

Symbol Description Condition Min Typ Max Units

SJ Jitter Tolerance with Stressed Eye2
JT_TJSE3.2 Total jitter with stressed eye8 3.2 Gb/s 0.70 – – UI
JT_TJSE6.6 6.6 Gb/s 0.70 – – UI
JT_SJSE3.2 Sinusoidal jitter with stressed eye8 3.2 Gb/s 0.10 – – UI
JT_SJSE6.6 6.6 Gb/s 0.10 – – UI
Notes:

1. Using RXOUT_DIV = 1, 2, and 4.

2. All jitter values are based on a bit error ratio of 10–12.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
7. CPLL frequency at 2.0 GHz and RXOUT_DIV = 8.
8. Composite jitter with RX equalizer enabled. DFE disabled.

GTH Transceiver Electrical Compliance

The UltraScale Architecture GTH Transceivers User Guide (UG576)) contains recommended use modes that ensure
compliance for the protocols listed in the following table. The transceiver wizard provides the recommended
settings for those use cases and for protocol specific characteristics.

Table 60: GTH Transceiver Protocol List

Electrical
Protocol Specification Serial Rate (Gb/s)
Compliance
CAUI-10 IEEE 802.3-2012 10.3125 Compliant
nPPI IEEE 802.3-2012 10.3125 Compliant
10GBASE-KR1 IEEE 802.3-2012 10.3125 Compliant
40GBASE-KR IEEE 802.3-2012 10.3125 Compliant
SFP+ SFF-8431 (SR and LR) 9.95328–11.10 Compliant
XFP INF-8077i, revision 4.5 10.3125 Compliant
RXAUI CEI-6G-SR 6.25 Compliant
XAUI IEEE 802.3-2012 3.125 Compliant
1000BASE-X IEEE 802.3-2012 1.25 Compliant
5.0G Ethernet IEEE 802.3bx (PAR) 5 Compliant
2.5G Ethernet IEEE 802.3bx (PAR) 2.5 Compliant
HiGig, HiGig+, HiGig2 IEEE 802.3-2012 3.74, 6.6 Compliant
OTU2 ITU G.8251 10.709225 Compliant
OTU4 (OTL4.10) OIF-CEI-11G-SR 11.180997 Compliant
OC-3/12/48/192 GR-253-CORE 0.1555–9.956 Compliant
TFI-5 OIF-TFI5-0.1.0 2.488 Compliant
Interlaken OIF-CEI-6G, OIF-CEI-11G-SR 4.25–12.5 Compliant
PCIe Gen1, 2, 3 PCI Express base 3.0 2.5, 5.0, and 8.0 Compliant

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Table 60: GTH Transceiver Protocol List (cont'd)

Electrical
Protocol Specification Serial Rate (Gb/s)
Compliance
SDI2 SMPTE 424M-2006 0.27–2.97 Compliant
UHD-SDI2 SMPTE ST-2081 6G, SMPTE ST-2082 12G 6 and 12 Compliant
Hybrid memory cube (HMC) HMC-15G-SR 10, 12.5, and 15.0 Compliant
MoSys Bandwidth Engine CEI-11-SR and CEI-11-SR (overclocked) 10.3125, 15.5 Compliant
CPRI CPRI_v_6_1_2014-07-01 0.6144–12.165 Compliant
HDMI2 HDMI 2.0 All Compliant
Passive optical network (PON) 10G-EPON, 1G-EPON, NG-PON2, XG-PON, and 2.5G- 0.155–10.3125 Compliant
PON
JESD204a/b OIF-CEI-6G, OIF-CEI-11G 3.125–12.5 Compliant
Serial RapidIO RapidIO specification 3.1 1.25–10.3125 Compliant
DisplayPort2 DP 1.2B CTS 1.62–5.4 Compliant
Fibre channel FC-PI-4 1.0625–14.025 Compliant
SATA Gen1, 2, 3 Serial ATA revision 3.0 specification 1.5, 3.0, and 6.0 Compliant
SAS Gen1, 2, 3 T10/BSR INCITS 519 3.0, 6.0, and 12.0 Compliant
SFI-5 OIF-SFI5-01.0 0.625–12.5 Compliant
Aurora CEI-6G, CEI-11G-LR up to 11.180997 Compliant
Notes:

1. The transition time of the transmitter is faster than the IEEE Std 802.3-2012 specification.
2. This protocol requires external circuitry to achieve compliance.

GTY Transceiver Specifications

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Kintex UltraScale+ FPGAs that
include the GTY transceivers.

GTY Transceiver DC Input and Output Levels

Table 61 summarizes the DC specifications of the GTY transceivers in Kintex UltraScale+ FPGAs. Consult the
UltraScale Architecture GTY Transceivers User Guide (UG578) for further details.

Table 61: GTY Transceiver DC Specifications

Symbol DC Parameter Conditions Min Typ Max Units

DVPPIN Differential peak-to-peak input voltage >10.3125 Gb/s 150 – 1250 mV
(external AC coupled)
6.6 Gb/s to 10.3125 Gb/s 150 – 1250 mV
≤ 6.6 Gb/s 150 – 2000 mV
VIN Single-ended input voltage. Voltage DC coupled VMGTAVTT = 1.2V –400 – VMGTAVTT mV
measured at the pin referenced to
GND.
VCMIN Common mode input voltage DC coupled VMGTAVTT = 1.2V – 2/3 VMGTAVTT – mV
DVPPOUT Differential peak-to-peak output Transmitter output swing is set 800 – – mV
voltage1 to 11111

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Table 61: GTY Transceiver DC Specifications (cont'd)

Symbol DC Parameter Conditions Min Typ Max Units

VCMOUTDC Common mode output voltage: DC When remote RX is terminated to VMGTAVTT/2 – DVPPOUT/4 mV
coupled (equation based) GND
When remote RX termination is VMGTAVTT – DVPPOUT/2 mV
floating
When remote RX is terminated to mV
VRX_TERM2

VCMOUTAC Common mode output voltage: AC Equation based VMGTAVTT – DVPPOUT/2 mV

coupled
RIN Differential input resistance – 100 – Ω
ROUT Differential output resistance – 100 – Ω
TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew – – 10 ps
CEXT Recommended external AC coupling capacitor3 – 100 – nF
Notes:

1. The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes discussed in the UltraScale Architecture
GTY Transceivers User Guide (UG578) and can result in values lower than reported in this table.
2. VRX_TERM is the remote RX termination voltage.
3. Other values can be used as appropriate to conform to specific protocols and standards.

Figure 5: Single-Ended Peak-to-Peak Voltage

+V P
Single-Ended
Peak-to-Peak
N Voltage
0

X16653-072117

Figure 6: Differential Peak-to-Peak Voltage

+V

Differential
0 Peak-to-Peak
Voltage

–V P–N
Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2
X16639-072117

The following tables summarize the DC specifications of the clock input/output levels of the GTY transceivers in
Kintex UltraScale+ FPGAs. Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further
details.

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Table 62: GTY Transceiver Clock DC Input Level Specification

Symbol DC Parameter Min Typ Max Units

VIDIFF Differential peak-to-peak input voltage 250 – 2000 mV
RIN Differential input resistance – 100 – Ω
CEXT Required external AC coupling capacitor – 10 – nF

Table 63: GTY Transceiver Clock Output Level Specification

Symbol Description Conditions Min Typ Max Units

VOL Output Low voltage for P and N RT = 100Ω across P and N signals 100 – 330 mV
VOH Output High voltage for P and N RT = 100Ω across P and N signals 500 – 700 mV
VDDOUT Differential output voltage (P–N), P = RT = 100Ω across P and N signals 300 – 430 mV
High (N–P), N = High
VCMOUT Common mode voltage RT = 100Ω across P and N signals 300 – 500 mV

GTY Transceiver Switching Characteristics

Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further information.

Table 64: GTY Transceiver Performance

Speed Grade and VCCINT Operating Voltages

Output
Symbol Description 0.90V 0.85V 0.72V Units
Divider
-3 -2 -1 -2 -1
FGTYMAX GTY maximum line rate 32.751 28.211 25.7851 28.211 12.5 Gb/s
FGTYMIN GTY minimum line rate 0.5 0.5 0.5 0.5 0.5 Gb/s
Min Max Min Max Min Max Min Max Min Max
FGTYCRANGE CPLL line rate 1 4.0 12.5 4.0 12.5 4.0 8.5 4.0 12.5 4.0 8.5 Gb/s
range2
2 2.0 6.25 2.0 6.25 2.0 4.25 2.0 6.25 2.0 4.25 Gb/s
4 1.0 3.125 1.0 3.125 1.0 2.125 1.0 3.125 1.0 2.125 Gb/s
8 0.5 1.5625 0.5 1.5625 0.5 1.0625 0.5 1.5625 0.5 1.0625 Gb/s
16 N/A Gb/s
32 N/A Gb/s
Min Max Min Max Min Max Min Max Min Max
FGTYQRANGE1 QPLL0 line rate 1 19.6 32.75 19.6 28.21 19.6 25.785 19.6 28.21 N/A Gb/s
range3
1 9.8 16.375 9.8 16.375 9.8 12.5 9.8 16.375 9.8 12.5 Gb/s
2 4.9 8.1875 4.9 8.1875 4.9 8.1875 4.9 8.1875 4.9 8.1875 Gb/s
4 2.45 4.0938 2.45 4.0938 2.45 4.0938 2.45 4.0938 2.45 4.0938 Gb/s
8 1.225 2.0469 1.225 2.0469 1.225 2.0469 1.225 2.0469 1.225 2.0469 Gb/s
16 0.6125 1.0234 0.6125 1.0234 0.6125 1.0234 0.6125 1.0234 0.6125 1.0234 Gb/s

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Table 64: GTY Transceiver Performance (cont'd)

Speed Grade and VCCINT Operating Voltages

Output
Symbol Description 0.90V 0.85V 0.72V Units
Divider
-3 -2 -1 -2 -1
Min Max Min Max Min Max Min Max Min Max
FGTYQRANGE2 QPLL1 line rate 1 16.0 26.0 16.0 26.0 16.0 25.785 16.0 26.0 N/A Gb/s
range4
1 8.0 13.0 8.0 13.0 8.0 12.5 8.0 13.0 8.0 12.5 Gb/s
2 4.0 6.5 4.0 6.5 4.0 6.5 4.0 6.5 4.0 6.5 Gb/s
4 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 Gb/s
8 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 Gb/s
16 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 Gb/s
Min Max Min Max Min Max Min Max Min Max
FCPLLRANGE CPLL frequency range 2.0 6.25 2.0 6.25 2.0 4.25 2.0 6.25 2.0 4.25 GHz
FQPLL0RANGE QPLL0 frequency range 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 GHz
FQPLL1RANGE QPLL1 frequency range 8.0 13.0 8.0 13.0 8.0 13.0 8.0 13.0 8.0 13.0 GHz
Notes:

1. GTY transceiver line rates are package limited: SFVB784 to 12.5 Gb/s; FFVA676, FFVD900, and FFVA1156 to 16.3 Gb/s.
2. The values listed are the rounded results of the calculated equation (2 × CPLL_Frequency)/Output_Divider.
3. The values listed are the rounded results of the calculated equation (2 × QPLL0_Frequency)/Output_Divider.
4. The values listed are the rounded results of the calculated equation (2 × QPLL1_Frequency)/Output_Divider.

Table 65: GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics

Symbol Description All Speed Grades Units

FGTYDRPCLK GTYDRPCLK maximum frequency 250 MHz

Table 66: GTY Transceiver Reference Clock Switching Characteristics

All Speed Grades

Symbol Description Conditions Units
Min Typ Max
FGCLK Reference clock frequency range 60 – 820 MHz
TRCLK Reference clock rise time 20% – 80% – 200 – ps
TFCLK Reference clock fall time 80% – 20% – 200 – ps
TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 %

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Table 67: GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask

Offset
Symbol Description1, 2 Min Typ Max Units
Frequency
QPLLREFCLKMASK QPLL0/QPLL1 reference clock select phase noise 10 kHz – – –112 dBc/Hz
mask at REFCLK frequency = 156.25 MHz
100 kHz – – –128
1 MHz – – –145
QPLL0/QPLL1 reference clock select phase noise 10 kHz – – –103 dBc/Hz
mask at REFCLK frequency = 312.5 MHz
100 kHz – – –123
1 MHz – – –143
QPLL0/QPLL1 reference clock select phase noise 10 kHz – – –98 dBc/Hz
mask at REFCLK frequency = 625 MHz
100 kHz – – –117
1 MHz – – –140
CPLLREFCLKMASK CPLL reference clock select phase noise mask at 10 kHz – – –112 dBc/Hz
REFCLK frequency = 156.25 MHz
100 kHz – – –128
1 MHz – – –145
50 MHz – – –145
CPLL reference clock select phase noise mask at 10 kHz – – –103 dBc/Hz
REFCLK frequency = 312.5 MHz
100 kHz – – –123
1 MHz – – –143
50 MHz – – –145
CPLL reference clock select phase noise mask at 10 kHz – – –98 dBc/Hz
REFCLK frequency = 625 MHz
100 kHz – – –117
1 MHz – – –140
50 MHz – – –144
Notes:

1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.
2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol,
e.g., PCIe.

Table 68: GTY Transceiver PLL/Lock Time Adaptation

All Speed Grades

Symbol Description Conditions Units
Min Typ Max
TLOCK Initial PLL lock. – – 1 ms
TDLOCK Clock recovery phase acquisition and After the PLL is locked to the – 50,000 37 x 106 UI
adaptation time for decision feedback reference clock, this is the
equalizer (DFE) time it takes to lock the clock
data recovery (CDR) to the
Clock recovery phase acquisition and data present at the input. – 50,000 2.3 x 106 UI
adaptation time for low-power mode (LPM)
when the DFE is disabled

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Table 69: GTY Transceiver User Clock Switching Characteristics

Data Width Conditions Speed Grade and VCCINT Operating Voltages

(Bit) 0.90V 0.85V 0.72V
Symbol Description1 Units
Internal Interconnect
-32 -22, 3 -14, 5, 6 -23 -15
Logic Logic
FTXOUTPMA TXOUTCLK maximum frequency sourced from 511.719 511.719 402.891 402.832 322.266 MHz
OUTCLKPMA
FRXOUTPMA RXOUTCLK maximum frequency sourced from 511.719 511.719 402.891 402.832 322.266 MHz
OUTCLKPMA
FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from 511.719 511.719 511.719 511.719 511.719 MHz
TXPROGDIVCLK
FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from 511.719 511.719 511.719 511.719 511.719 MHz
RXPROGDIVCLK
FTXIN TXUSRCLK7 16 16, 32 511.719 511.719 390.625 390.625 322.266 MHz
maximum
frequency 32 32, 64 511.719 511.719 390.625 390.625 322.266 MHz
64 64, 128 511.719 440.781 402.891 402.832 195.313 MHz
20 20, 40 409.375 409.375 312.500 312.500 257.813 MHz
40 40, 80 409.375 409.375 312.500 350.000 257.813 MHz
80 80, 160 409.375 352.625 322.313 352.625 156.250 MHz
FRXIN RXUSRCLK7 16 16, 32 511.719 511.719 390.625 390.625 322.266 MHz
maximum
frequency 32 32, 64 511.719 511.719 390.625 390.625 322.266 MHz
64 64, 128 511.719 440.781 402.891 402.832 195.313 MHz
20 20, 40 409.375 409.375 312.500 312.500 257.813 MHz
40 40, 80 409.375 409.375 312.500 350.000 257.813 MHz
80 80, 160 409.375 352.625 322.313 352.625 156.250 MHz
FTXIN2 TXUSRCLK27 16 16 511.719 511.719 390.625 390.625 322.266 MHz
maximum
frequency 16 32 255.859 255.859 195.313 195.313 161.133 MHz
32 32 511.719 511.719 390.625 390.625 322.266 MHz
32 64 255.859 255.859 195.313 195.313 161.133 MHz
64 64 511.719 440.781 402.891 402.832 195.313 MHz
64 128 255.859 220.391 201.445 201.416 97.656 MHz
20 20 409.375 409.375 312.500 312.500 257.813 MHz
20 40 204.688 204.688 156.250 156.250 128.906 MHz
40 40 409.375 409.375 312.500 350.000 257.813 MHz
40 80 204.688 204.688 156.250 175.000 128.906 MHz
80 80 409.375 352.625 322.313 352.625 156.250 MHz
80 160 204.688 176.313 161.156 176.313 78.125 MHz

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Table 69: GTY Transceiver User Clock Switching Characteristics (cont'd)

Data Width Conditions Speed Grade and VCCINT Operating Voltages

(Bit) 0.90V 0.85V 0.72V
Symbol Description1 Units
Internal Interconnect
-32 -22, 3 -14, 5, 6 -23 -15
Logic Logic
FRXIN2 RXUSRCLK27 16 16 511.719 511.719 390.625 390.625 322.266 MHz
maximum
frequency 16 32 255.859 255.859 195.313 195.313 161.133 MHz
32 32 511.719 511.719 390.625 390.625 322.266 MHz
32 64 255.859 255.859 195.313 195.313 161.133 MHz
64 64 511.719 440.781 402.891 402.832 195.313 MHz
64 128 255.859 220.391 201.445 201.416 97.656 MHz
20 20 409.375 409.375 312.500 312.500 257.813 MHz
20 40 204.688 204.688 156.250 156.250 128.906 MHz
40 40 409.375 409.375 312.500 350.000 257.813 MHz
40 80 204.688 204.688 156.250 175.000 128.906 MHz
80 80 409.375 352.625 322.313 352.625 156.250 MHz
80 160 204.688 176.313 161.156 176.313 78.125 MHz
Notes:

1. Clocking must be implemented as described in the UltraScale Architecture GTY Transceivers User Guide (UG578).
2. For speed grades -3E, -2E, and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s.
3. For speed grade -2LE, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s when VCCINT = 0.85V or
6.25 Gb/s when VCCINT = 0.72V.
4. For speed grades -1E and -1I, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s.
5. For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when VCCINT = 0.85V or
5.15625 Gb/s when VCCINT = 0.72V.
6. For the speed grades -1E and -1I, only a 64- or 80-bit internal data path can be used for line rates above 12.5 Gb/s.
7. When the gearbox is used, these maximums refer to the XCLK. For more information, see the Valid Data Width Combinations for TX
Asynchronous Gearbox table in the UltraScale Architecture GTY Transceivers User Guide (UG578).

Table 70: GTY Transceiver Transmitter Switching Characteristics

Symbol Description Condition Min Typ Max Units

FGTYTX Serial data rate range 0.500 – FGTYMAX Gb/s
TRTX TX rise time 20%–80% – 21 – ps
TFTX TX fall time 80%–20% – 21 – ps
TLLSKEW TX lane-to-lane skew1 – – 500.00 ps
TJ32.75 Total jitter2, 4 32.75 Gb/s – – 0.35 UI
DJ32.75 Deterministic jitter2, 4 – – 0.19 UI
TJ28.21 Total jitter2, 4 28.21 Gb/s – – 0.28 UI
DJ28.21 Deterministic jitter2, 4 – – 0.17 UI
TJ16.375 Total jitter2, 4 16.375 Gb/s – – 0.28 UI
DJ16.375 Deterministic jitter2, 4 – – 0.17 UI
TJ15.0 Total jitter2, 4 15.0 Gb/s – – 0.28 UI
DJ15.0 Deterministic jitter2, 4 – – 0.17 UI

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Table 70: GTY Transceiver Transmitter Switching Characteristics (cont'd)

Symbol Description Condition Min Typ Max Units

TJ14.1 Total jitter2, 4 14.1 Gb/s – – 0.28 UI
DJ14.1 Deterministic jitter2, 4 – – 0.17 UI
TJ14.1 Total jitter2, 4 14.025 Gb/s – – 0.28 UI
DJ14.1 Deterministic jitter2, 4 – – 0.17 UI
TJ13.1 Total jitter2, 4 13.1 Gb/s – – 0.28 UI
DJ13.1 Deterministic jitter2, 4 – – 0.17 UI
TJ12.5_QPLL Total jitter2, 4 12.5 Gb/s – – 0.28 UI
DJ12.5_QPLL Deterministic jitter2, 4 – – 0.17 UI
TJ12.5_CPLL Total jitter3, 4 12.5 Gb/s – – 0.33 UI
DJ12.5_CPLL Deterministic jitter3, 4 – – 0.17 UI
TJ11.3_QPLL Total jitter2, 4 11.3 Gb/s – – 0.28 UI
DJ11.3_QPLL Deterministic jitter2, 4 – – 0.17 UI
TJ10.3125_QPLL Total jitter2, 4 10.3125 Gb/s – – 0.28 UI
DJ10.3125_QPLL Deterministic jitter2, 4 – – 0.17 UI
TJ10.3125_CPLL Total jitter3, 4 10.3125 Gb/s – – 0.33 UI
DJ10.3125_CPLL Deterministic jitter3, 4 – – 0.17 UI
TJ9.953_QPLL Total jitter2, 4 9.953 Gb/s – – 0.28 UI
DJ9.953_QPLL Deterministic jitter2, 4 – – 0.17 UI
TJ9.953_CPLL Total jitter3, 4 9.953 Gb/s – – 0.33 UI
DJ9.953_CPLL Deterministic jitter3, 4 – – 0.17 UI
TJ8.0 Total jitter3, 4 8.0 Gb/s – – 0.32 UI
DJ8.0 Deterministic jitter3, 4 – – 0.17 UI
TJ6.6 Total jitter3, 4 6.6 Gb/s – – 0.30 UI
DJ6.6 Deterministic jitter3, 4 – – 0.15 UI
TJ5.0 Total jitter3, 4 5.0 Gb/s – – 0.30 UI
DJ5.0 Deterministic jitter3, 4 – – 0.15 UI
TJ4.25 Total jitter3, 4 4.25 Gb/s – – 0.30 UI
DJ4.25 Deterministic jitter3, 4 – – 0.15 UI
TJ3.20 Total jitter3, 4 3.20 Gb/s5 – – 0.20 UI
DJ3.20 Deterministic jitter3, 4 – – 0.10 UI
TJ2.5 Total jitter3, 4 2.5 Gb/s6 – – 0.20 UI
DJ2.5 Deterministic jitter3, 4 – – 0.10 UI
TJ1.25 Total jitter3, 4 1.25 Gb/s7 – – 0.15 UI
DJ1.25 Deterministic jitter3, 4 – – 0.06 UI

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Table 70: GTY Transceiver Transmitter Switching Characteristics (cont'd)

Symbol Description Condition Min Typ Max Units

TJ500 Total jitter3, 4 500 Mb/s8 – – 0.10 UI
DJ500 Deterministic jitter3, 4 – – 0.03 UI
Notes:

1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTY Quad) at
maximum line rate.
2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
4. All jitter values are based on a bit-error ratio of 10–12.
5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
8. CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.

Table 71: GTY Transceiver Receiver Switching Characteristics

Symbol Description Condition Min Typ Max Units

FGTYRX Serial data rate 0.500 – FGTYMAX Gb/s
RXSST Receiver spread-spectrum tracking1 Modulated at 33 kHz –5000 – 0 ppm
RXRL Run length (CID) – – 256 UI
RXPPMTOL Data/REFCLK PPM offset tolerance Bit rates ≤ 6.6 Gb/s –1250 – 1250 ppm
Bit rates > 6.6 Gb/s and –700 – 700 ppm
≤ 8.0 Gb/s
Bit rates > 8.0 Gb/s –200 – 200 ppm
SJ Jitter Tolerance2
JT_SJ32.75 Sinusoidal jitter (QPLL)3 32.75 Gb/s 0.25 – – UI
JT_SJ28.21 Sinusoidal jitter (QPLL)3 28.21 Gb/s 0.30 – – UI
JT_SJ16.375 Sinusoidal jitter (QPLL)3 16.375 Gb/s 0.30 – – UI
JT_SJ15.0 Sinusoidal jitter (QPLL)3 15.0 Gb/s 0.30 – – UI
JT_SJ14.1 Sinusoidal jitter (QPLL)3 14.1 Gb/s 0.30 – – UI
JT_SJ13.1 Sinusoidal jitter (QPLL)3 13.1 Gb/s 0.30 – – UI
JT_SJ12.5 Sinusoidal jitter (QPLL)3 12.5 Gb/s 0.30 – – UI
JT_SJ11.3 Sinusoidal jitter (QPLL)3 11.3 Gb/s 0.30 – – UI
JT_SJ10.32_QPLL Sinusoidal jitter (QPLL)3 10.32 Gb/s 0.30 – – UI
JT_SJ10.32_CPLL Sinusoidal jitter (CPLL)3 10.32 Gb/s 0.30 – – UI
JT_SJ9.953_QPLL Sinusoidal jitter (QPLL)3 9.953 Gb/s 0.30 – – UI
JT_SJ9.953_CPLL Sinusoidal jitter (CPLL)3 9.953 Gb/s 0.30 – – UI
JT_SJ8.0 Sinusoidal jitter (CPLL)3 8.0 Gb/s 0.42 – – UI
JT_SJ6.6 Sinusoidal jitter (CPLL)3 6.6 Gb/s 0.44 – – UI
JT_SJ5.0 Sinusoidal jitter (CPLL)3 5.0 Gb/s 0.44 – – UI
JT_SJ4.25 Sinusoidal jitter (CPLL)3 4.25 Gb/s 0.44 – – UI
JT_SJ3.2 Sinusoidal jitter (CPLL)3 3.2 Gb/s4 0.45 – – UI
JT_SJ2.5 Sinusoidal jitter (CPLL)3 2.5 Gb/s5 0.30 – – UI
JT_SJ1.25 Sinusoidal jitter (CPLL)3 1.25 Gb/s6 0.30 – – UI
JT_SJ500 Sinusoidal jitter (CPLL)3 500 Mb/s7 0.30 – – UI

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 71: GTY Transceiver Receiver Switching Characteristics (cont'd)

Symbol Description Condition Min Typ Max Units

SJ Jitter Tolerance with Stressed Eye2
JT_TJSE3.2 Total jitter with stressed eye8 3.2 Gb/s 0.70 – – UI
JT_TJSE6.6 6.6 Gb/s 0.70 – – UI
JT_SJSE3.2 Sinusoidal jitter with stressed eye8 3.2 Gb/s 0.10 – – UI
JT_SJSE6.6 6.6 Gb/s 0.10 – – UI
Notes:

1. Using RXOUT_DIV = 1, 2, and 4.

2. All jitter values are based on a bit error ratio of 10–12.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
7. CPLL frequency at 2.0 GHz and RXOUT_DIV = 8.
8. Composite jitter with RX equalizer enabled. DFE disabled.

GTY Transceiver Electrical Compliance

The UltraScale Architecture GTY Transceivers User Guide (UG578) contains recommended use modes that ensure
compliance for the protocols listed in the following table. The transceiver wizard provides the recommended
settings for those use cases and for protocol specific characteristics.

Table 72: GTY Transceiver Protocol List

Electrical
Protocol Specification Serial Rate (Gb/s)
Compliance
CAUI-4 IEEE 802.3-2012 25.78125 Compliant
28 Gb/s backplane CEI-25G-LR 25–28.05 Compliant
Interlaken OIF-CEI-6G, OIF-CEI-11GSR, OIF-CEI-28G-MR 4.25–25.78125 Compliant
100GBASE-KR4 IEEE 802.3bj-2014, CEI-25G-LR 25.78125 Compliant1
100GBASE-CR4 IEEE 802.3bj-2014, CEI-25G-LR 25.78125 Compliant1
50GBASE-KR4 IEEE 802.3by-2014, CEI-25G-LR 25.78125 Compliant1
50GBASE-CR4 IEEE 802.3by-2014, CEI-25G-LR 25.78125 Compliant1
25GBASE-KR4 IEEE 802.3by-2014, CEI-25G-LR 25.78125 Compliant1
25GBASE-CR4 IEEE 802.3by-2014, CEI-25G-LR 25.78125 Compliant1
OTU4 (OTL4.4) CFP2 OIF-CEI-28G-VSR 27.952493–32.75 Compliant
OTU4 (OTL4.4) CFP OIF-CEI-11G-MR 11.18–13.1 Compliant
CAUI-10 IEEE 802.3-2012 10.3125 Compliant
nPPI IEEE 802.3-2012 10.3125 Compliant
10GBASE-KR2 IEEE 802.3-2012 10.3125 Compliant
SFP+ SFF-8431 (SR and LR) 9.95328–11.10 Compliant
XFP INF-8077i, revision 4.5 10.3125 Compliant
RXAUI CEI-6G-SR 6.25 Compliant
XAUI IEEE 802.3-2012 3.125 Compliant

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Table 72: GTY Transceiver Protocol List (cont'd)

Electrical
Protocol Specification Serial Rate (Gb/s)
Compliance
1000BASE-X IEEE 802.3-2012 1.25 Compliant
5.0G Ethernet IEEE 802.3bx (PAR) 5 Compliant
2.5G Ethernet IEEE 802.3bx (PAR) 2.5 Compliant
HiGig, HiGig+, HiGig2 IEEE 802.3-2012 3.74, 6.6 Compliant
QSGMII QSGMII v1.2 (Cisco System, ENG-46158) 5 Compliant
OTU2 ITU G.8251 10.709225 Compliant
OTU4 (OTL4.10) OIF-CEI-11G-SR 11.180997 Compliant
OC-3/12/48/192 GR-253-CORE 0.1555–9.956 Compliant
PCIe Gen1, 2, 3 PCI Express base 3.0 2.5, 5.0, and 8.0 Compliant
SDI3 SMPTE 424M-2006 0.27–2.97 Compliant
UHD-SDI3 SMPTE ST-2081 6G, SMPTE ST-2082 12G 6 and 12 Compliant
Hybrid memory cube (HMC) HMC-15G-SR 10, 12.5, and 15.0 Compliant
MoSys bandwidth engine CEI-11-SR and CEI-11-SR (overclocked) 10.3125, 15.5 Compliant
CPRI CPRI_v_6_1_2014-07-01 0.6144–12.165 Compliant
Passive optical network (PON) 10G-EPON, 1G-EPON, NG-PON2, XG-PON, and 2.5G-PON 0.155–10.3125 Compliant
JESD204a/b OIF-CEI-6G, OIF-CEI-11G 3.125–12.5 Compliant
Serial RapidIO RapidIO specification 3.1 1.25–10.3125 Compliant
DisplayPort DP 1.2B CTS 1.62–5.4 Compliant3
Fibre channel FC-PI-4 1.0625–14.025 Compliant
SATA Gen1, 2, 3 Serial ATA revision 3.0 specification 1.5, 3.0, and 6.0 Compliant
SAS Gen1, 2, 3 T10/BSR INCITS 519 3.0, 6.0, and 12.0 Compliant
SFI-5 OIF-SFI5-01.0 0.625 - 12.5 Compliant
Aurora CEI-6G, CEI-11G-LR All rates Compliant
Notes:

1. 25 dB loss at Nyquist without FEC.

2. The transition time of the transmitter is faster than the IEEE Std 802.3-2012 specification.
3. This protocol requires external circuitry to achieve compliance.

Integrated Interface Block for Interlaken

More information and documentation on solutions using the integrated interface block for Interlaken can be
found at UltraScale+ Interlaken. The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how
many blocks are in each Kintex UltraScale+ FPGA. This section describes the following Interlaken
configurations.

• 12 x 12.5 Gb/s protocol and lane logic mode (Table 73).

• 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s protocol and lane logic mode (Table 74).
• 12 x 25.78125 Gb/s lane logic only mode (Table 75).

Kintex UltraScale+ FPGAs in the SFVB784, FFVA676, FFVD900, and FFVA1156 packages are only supported
using the 12 x 12.5 Gb/s Interlaken configuration. See the FGTYMAX maximum line rates.

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Table 73: Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode
Designs

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
FRX_SERDES_CLK Receive serializer/ 195.32 195.32 195.32 195.32 195.32 MHz
deserializer clock
FTX_SERDES_CLK Transmit serializer/ 195.32 195.32 195.32 195.32 195.32 MHz
deserializer clock
FDRP_CLK Dynamic reconfiguration 250.00 250.00 250.00 250.00 250.00 MHz
port clock
Min1 Max Min1 Max Min1 Max Min1 Max Min1 Max
FCORE_CLK Interlaken core clock 300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27 MHz
FLBUS_CLK Interlaken local bus 300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27 MHz
clock
Notes:

1. These are the minimum clock frequencies at the maximum lane performance.

Table 74: Maximum Performance for Interlaken 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s Protocol and
Lane Logic Mode Designs

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-31 -21 -1 -2 -1
FRX_SERDES_CLK Receive serializer/ 440.79 440.79 N/A 402.84 N/A MHz
deserializer clock
FTX_SERDES_CLK Transmit serializer/ 440.79 440.79 N/A 402.84 N/A MHz
deserializer clock
FDRP_CLK Dynamic reconfiguration 250.00 250.00 N/A 250.00 N/A MHz
port clock
Min2 Max Min2 Max Min Max Min2 Max Min Max
FCORE_CLK Interlaken core clock 412.503 479.20 412.503 479.20 N/A 412.50 429.69 N/A MHz
FLBUS_CLK Interlaken local bus clock 300.004 349.52 300.004 349.52 N/A 300.00 349.52 N/A MHz
Notes:

1. 6 x 28.21 mode is only supported in the -2 (VCCINT = 0.85V) and -3 (VCCINT = 0.90V) speed grades.
2. These are the minimum clock frequencies at the maximum lane performance.
3. The minimum value for CORE_CLK is 451.36 MHz for the 6 x 28.21 Gb/s protocol.
4. The minimum value for LBUS_CLK is 330.00 MHz for the 6 x 28.21 Gb/s protocol.

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Table 75: Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
FRX_SERDES_CLK Receive serializer/ 402.84 402.84 N/A N/A N/A MHz
deserializer clock
FTX_SERDES_CLK Transmit serializer/ 402.84 402.84 N/A N/A N/A MHz
deserializer clock
FDRP_CLK Dynamic reconfiguration port 250.00 250.00 N/A N/A N/A MHz
clock
FCORE_CLK Interlaken core clock 412.50 412.50 N/A N/A N/A MHz
FLBUS_CLK Interlaken local bus clock 349.52 349.52 N/A N/A N/A MHz

Integrated Interface Block for 100G Ethernet MAC and

PCS
More information and documentation on solutions using the integrated 100 Gb/s Ethernet block can be found
at UltraScale+ Integrated 100G Ethernet MAC/PCS. The UltraScale Architecture and Product Data Sheet:
Overview (DS890) lists how many blocks are in each Kintex UltraScale+ FPGA.

Table 76: Maximum Performance for 100G Ethernet Designs

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
CAUI-10 Mode
FTX_CLK Transmit clock 390.625 390.625 322.266 322.266 322.266 MHz
FRX_CLK Receive clock 390.625 390.625 322.266 322.266 322.266 MHz
FRX_SERDES_CLK Receive serializer/deserializer clock 390.625 390.625 322.266 322.266 322.266 MHz
FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 250.00 250.00 250.00 MHz
CAUI-4, CAUI-4 + RS-FEC, and RS-FEC Transcode Bypass Modes
FTX_CLK Transmit clock 390.625 322.266 322.266 322.266 N/A MHz
FRX_CLK Receive clock 390.625 322.266 322.266 322.266 N/A MHz
FRX_SERDES_CLK Receive serializer/deserializer clock 390.625 322.266 322.266 322.266 N/A MHz
FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 250.00 250.00 N/A MHz

Integrated Interface Block for PCI Express Designs

More information and documentation on solutions for PCI Express designs can be found at PCI Express. The
UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many blocks are in each
Kintex UltraScale+ FPGA.

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Table 77: Maximum Performance for PCI Express Designs

Speed Grade and VCCINT Operating Voltages

Symbol Description1, 2 0.90V 0.85V 0.72V3 Units
-3 -2 -1 -2 -1
FPIPECLK Pipe clock maximum frequency 250.00 250.00 250.00 250.00 250.00 MHz
FCORECLK Core clock maximum frequency 500.00 500.00 500.00 250.00 250.00 MHz
FDRPCLK DRP clock maximum frequency 250.00 250.00 250.00 250.00 250.00 MHz
FMCAPCLK MCAP clock maximum frequency 125.00 125.00 125.00 125.00 125.00 MHz
Notes:

1. PCI Express Gen4 operation is supported for x1, x2, x4, and x8 widths.
2. PCI Express Gen4 operation is supported in -3E, -2E, and -2I speed grades.
3. PCI Express Gen3 x16 operation is not supported when VCCINT = 0.72V.

System Monitor Specifications

Table 78: System Monitor Specifications

Parameter Symbol Comments/Conditions Min Typ Max Units

VCCADC = 1.8V ±3%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = –40°C to 100°C, typical values at Tj = 40°C
ADC Accuracy1
Resolution 10 – – Bits
Integral nonlinearity2 INL – – ±1.5 LSBs
Differential nonlinearity DNL No missing codes, guaranteed monotonic – – ±1 LSBs
Offset error Offset calibration enabled – – ±2 LSBs
Gain error – – ±0.4 %
Sample rate – – 0.2 MS/s
RMS code noise External 1.25V reference – – 1 LSBs
On-chip reference – 1 – LSBs
ADC Accuracy at Extended Temperatures
Resolution Tj = –55°C to 125°C 10 – – Bits
Integral nonlinearity2 INL Tj = –55°C to 125°C – – ±1.5 LSBs
Differential nonlinearity DNL No missing codes, guaranteed monotonic – – ±1
Tj = –55°C to 125°C
Analog Inputs2
ADC input ranges Unipolar operation 0 – 1 V
Bipolar operation –0.5 – +0.5 V
Unipolar common mode range (FS input) 0 – +0.5 V
Bipolar common mode range (FS input) +0.5 – +0.6 V
Maximum external channel input ranges Adjacent channels set within these ranges should –0.1 – VCCADC V
not corrupt measurements on adjacent channels
On-Chip Sensor Accuracy
Temperature sensor error1, 3 Tj = –55°C to 125°C (with external REF) – – ±3 °C
Tj = –55°C to 110°C (with internal REF) – – ±3.5 °C
Tj = 110°C to 125°C (with internal REF) – – ±5 °C

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Table 78: System Monitor Specifications (cont'd)

Parameter Symbol Comments/Conditions Min Typ Max Units

Supply sensor error4 Supply voltages 0.72V to 1.2V, – – ±0.5 %
Tj = –40°C to 100°C (with external REF)
Supply voltages 0.72V to 1.2V, – – ±1.0 %
Tj = –55°C to 125°C (with external REF)
All other supply voltages, – – ±1.0 %
Tj = –40°C to 100°C (with external REF)
All other supply voltages, – – ±2.0 %
Tj = –55°C to 125°C (with external REF)
Supply voltages 0.72V to 1.2V, – – ±1.0 %
Tj = –40°C to 100°C (with internal REF)
Supply voltages 0.72V to 1.2V, – – ±2.0 %
Tj = –55°C to 125°C (with internal REF)
All other supply voltages, – – ±1.5 %
Tj = –40°C to 100°C (with internal REF)
All other supply voltages, – – ±2.5 %
Tj = –55°C to 125°C (with internal REF)
Conversion Rate5
Conversion time—continuous tCONV Number of ADCCLK cycles 26 – 32 Cycles
Conversion time—event tCONV Number of ADCCLK cycles – – 21 Cycles
DRP clock frequency DCLK DRP clock frequency 8 – 250 MHz
ADC clock frequency ADCCLK Derived from DCLK 1 – 5.2 MHz
DCLK duty cycle 40 – 60 %
SYSMON Reference6
External reference VREFP Externally supplied reference voltage 1.20 1.25 1.30 V
On-chip reference Ground VREFP pin to AGND, Tj = –40°C to 100°C 1.2375 1.25 1.2625 V
Ground VREFP pin to AGND, Tj = –55°C to 125°C 1.225 1.25 1.275 V
Notes:

1. ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is
enabled.
2. See the Analog Input section in the UltraScale Architecture System Monitor User Guide (UG580).
3. When reading temperature values directly from the PMBus interface, the SYSMON has a +4°C offset due to the transfer function used by
the PMBus application. For example, the external REF temperature sensor error’s range of ±3°C becomes +1°C to +7°C when the
temperature is read through the PMBus interface.
4. Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values are specified
for when this feature is enabled.
5. See the Adjusting the Acquisition Settling Time section in the UltraScale Architecture System Monitor User Guide (UG580).
6. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for
external ratiometric type applications allowing reference to vary by ±4% is permitted.

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SYSMON I2C/PMBus Interfaces

Table 79: SYSMON I2C Fast Mode Interface Switching Characteristics

Symbol Description1 Min Max Units

TSMFCKL SCL Low time 1.3 – µs
TSMFCKH SCL High time 0.6 – µs
TSMFCKO SDAO clock-to-out delay – 900 ns
TSMFDCK SDAI setup time 100 – ns
FSMFCLK SCL clock frequency – 400 kHz
Notes:

1. The test conditions are configured to the LVCMOS 1.8V I/O standard.

Table 80: SYSMON I2C Standard Mode Interface Switching Characteristics

Symbol Description1 Min Max Units

TSMSCKL SCL Low time 4.7 – µs
TSMSCKH SCL High time 4.0 – µs
TSMSCKO SDAO clock-to-out delay – 3450 ns
TSMSDCK SDAI setup time 250 – ns
FSMSCLK SCL clock frequency – 100 kHz
Notes:

1. The test conditions are configured to the LVCMOS 1.8V I/O standard.

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 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Configuration Switching Characteristics

Table 81: Configuration Switching Characteristics

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
Power-up Timing Characteristics
TPL Program latency 7.5 7.5 7.5 7.5 7.5 ms, Max
TPOR Power-on reset (40 ms maximum ramp rate) 65 65 65 65 65 ms, Max
0 0 0 0 0 ms, Min
Power-on reset with POR override (2 ms 15 15 15 15 15 ms, Max
maximum ramp rate)
5 5 5 5 5 ms, Min
TPROGRAM Program pulse width 250 250 250 250 250 ns, Min
CCLK Output (Master Mode)
TICCK Master CCLK output delay from INIT_B 150 150 150 150 150 ns, Min
TMCCKL 1 Master CCLK clock Low time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max
TMCCKH Master CCLK clock High time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max
FMCCK Master SPI/BPI CCLK XCKU3P, XCKU5P 125 125 125 60 60 MHz, Max
frequency
All other devices 150 150 150 125 125
FMCCK_START Master CCLK frequency at start of 2.70 2.70 2.70 2.70 2.70 MHz, Typ
configuration
FMCCKTOL Frequency tolerance, master mode with ±15 ±15 ±15 ±15 ±15 %, Max
respect to nominal CCLK
CCLK Input (Slave Mode)
TSCCKL Slave CCLK clock minimum Low time 2.5 2.5 2.5 2.5 2.5 ns, Min
TSCCKH Slave CCLK clock minimum High time 2.5 2.5 2.5 2.5 2.5 ns, Min
FSCCK Slave serial/ Slave XCKU3P, XCKU5P 125 125 125 60 60 MHz, Max
SelectMAP CCLK
frequency All other devices 125 125 125 125 125

EMCCLK Input (Master Mode)

TEMCCKL External master CCLK Low time 2.5 2.5 2.5 2.5 2.5 ns, Min
TEMCCKH External master CCLK High time 2.5 2.5 2.5 2.5 2.5 ns, Min
FEMCCK External master CCLK XCKU3P, XCKU5P 125 125 125 60 60 MHz, Max
frequency
All other devices 150 150 150 125 125
Internal Configuration Access Port
FICAPCK Internal configuration access port (ICAPE3) 200 200 200 150 150 MHz, Max
Slave Serial Mode Programming Switching
TDCCK/TCCKD DIN setup/hold 3.0/0 3.0/0 3.0/0 4.0/0 4.0/0 ns, Min
TCCO DOUT clock to out 8.0 8.0 8.0 9.0 9.0 ns, Max
SelectMAP Mode Programming Switching
TSMDCCK/TSMCCKD D[31:00] setup/hold XCKU3P, XCKU5P 4.5/0 4.5/0 4.5/0 8.0/0 8.0/0 ns, Min
All other devices 3.5/0 3.5/0 3.5/0 4.5/0 4.5/0

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Product Specification 66
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 81: Configuration Switching Characteristics (cont'd)

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
TSMCSCCK/TSMCCKCS CSI_B setup/hold XCKU3P, XCKU5P 4.5/0 4.5/0 4.5/0 7.0/0 7.0/0 ns, Min
All other devices 4.0/0 4.0/0 4.0/0 5.0/0 5.0/0
TSMWCCK/TSMCCKW RDWR_B setup/hold XCKU3P, XCKU5P 10.0/0 10.0/0 10.0/0 17.0/0 17.0/0 ns, Min
All other devices 10.0/0 10.0/0 10.0/0 11.0/0 11.0/0
TSMCKCSO CSO_B clock to out XCKU3P, XCKU5P 7.0 7.0 7.0 10.0 10.0 ns, Max
(330Ω pull-up resistor
required) All other devices 7.0 7.0 7.0 7.0 7.0

TSMCO D[31:00] clock to out in XCKU3P, XCKU5P 8.0 8.0 8.0 10.0 10.0 ns, Max
readback
All other devices 8.0 8.0 8.0 8.0 8.0
FRBCCK Readback frequency XCKU3P, XCKU5P 125 125 125 60 60 MHz, Max
All other devices 125 125 125 125 125
Boundary-Scan Port Timing Specifications
TTAPTCK/TTCKTAP TMS and TDI setup/hold 3.0/2.0 3.0/2.0 3.0/2.0 3.0/2.0 3.0/2.0 ns, Min
TTCKTDO TCK falling edge to TDO output 7.0 7.0 7.0 7.0 7.0 ns, Max
FTCK TCK frequency XCKU15P 66 66 66 50 50 MHz, Max
All other devices 66 66 66 66 66
BPI Master Flash Mode Programming Switching
TBPICCO A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, 10 10 10 10 10 ns, Max
ADV_B clock to out
TBPIDCC/TBPICCD D[15:00] setup/hold XCKU3P, XCKU5P 4.5/0 4.5/0 4.5/0 8.0/0 8.0/0 ns, Min
All other devices 3.5/0 3.5/0 3.5/0 4.5/0 4.5/0
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPICCD D[03:00] setup/hold 3.0/0 3.0/0 3.0/0 4.0/0 4.0/0 ns, Min
TSPIDCC/TSPICCD D[07:04] setup/hold XCKU3P, XCKU5P 4.5/0 4.5/0 4.5/0 8.0/0 8.0/0 ns, Min
All other devices 3.5/0 3.5/0 3.5/0 4.5/0 4.5/0
TSPICCM MOSI clock to out 8.0 8.0 8.0 8.0 8.0 ns, Max
TSPICCM2 D[04] clock to out 10.0 10.0 10.0 10.0 10.0 ns, Max
TSPICCFC FCS_B clock to out 8.0 8.0 8.0 8.0 8.0 ns, Max
TSPICCFC2 FCS2_B clock to out 10.0 10.0 10.0 10.0 10.0 ns, Max
DNA Port Switching
FDNACK DNA port frequency 200 200 200 175 175 MHz, Max
STARTUPE3 Ports
TUSRCCLKO STARTUPE3 USRCCLKO input port to CCLK 0.25/6.00 0.25/6.50 0.25/7.50 0.25/9.00 0.25/9.00 ns, Min/Max
pin output delay
TDO DO[3:0] ports to D03-D00 pins output delay 0.25/6.70 0.25/7.70 0.25/8.40 0.25/10.00 0.25/10.00 ns, Min/Max
TDTS DTS[3:0] ports to D03-D00 pins 3-state delays 0.25/6.70 0.25/7.70 0.25/8.40 0.25/10.00 0.25/10.00 ns, Min/Max
TFCSBO FCSBO port to FCS_B pin output delay 0.25/6.90 0.25/7.50 0.25/8.40 0.25/9.80 0.25/9.80 ns, Min/Max
TFCSBTS FCSBTS port to FCS_B pin 3-state delay 0.25/6.90 0.25/7.50 0.25/8.40 0.25/9.80 0.25/9.80 ns, Min/Max
TUSRDONEO USRDONEO port to DONE pin output delay 0.25/8.60 0.25/9.40 0.25/10.50 0.25/12.10 0.25/12.10 ns, Min/Max
TUSRDONETS USRDONETS port to DONE pin 3-state delay 0.25/8.60 0.25/9.40 0.25/10.50 0.25/12.10 0.25/12.10 ns, Min/Max
TDI D03-D00 pins to DI[3:0] ports input delay 0.5/2.6 0.5/3.1 0.5/3.5 0.5/4.0 0.5/4.0 ns, Min/Max

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Product Specification 67
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Table 81: Configuration Switching Characteristics (cont'd)

Speed Grade and VCCINT Operating Voltages

Symbol Description 0.90V 0.85V 0.72V Units
-3 -2 -1 -2 -1
FCFGMCLK STARTUPE3 CFGMCLK output frequency 50 50 50 50 50 MHz, Typ
FCFGMCLKTOL STARTUPE3 CFGMCLK output frequency ±15 ±15 ±15 ±15 ±15 %, Max
tolerance
TDCI_MATCH Specifies a stall in the startup cycle until the 4 4 4 4 4 ms, Max
digitally controlled impedance (DCI) match
signals are asserted
Notes:

1. When the CCLK is sourced from the EMCCLK pin with a divide-by-one setting, the external EMCCLK must meet this duty-cycle
requirement.

Revision History

Date Version Description of Revisions

08/01/2018 1.13 Updated Table 20, Table 21, and Table 22 to production release the XCKU9P devices in the -3E speed/
temperature grade in Vivado Design Suite 2018.2.1 v1.21.
In Table 24, added Note 4 to the LVDS RX DDR maximum data.
In Table 76, revised the calculated values from 322.223 to 322.266.
06/18/2018 1.12 Revised the speed grade -1 (VCCINT = 0.85) FGTYMAX in Table 64, which also revised values in Table 69 and
added Note 6.
04/09/2018 1.11 Updated Table 20, Table 21, and Table 22 to production release the XCKU3P, XCKU5P, XCKU11P,
XCKU13P, and XCKU15P devices in the -3E speed/temperature grade in Vivado Design Suite 2018.1 v1.19.
Added Table 43 and Table 47. Added Note 2 and 3 to Table 46.
Revised Table 76
02/07/2018 1.10 Updated Table 20, Table 21, and to add specific mode specifications and remove Notes 1 and 2.Table 22
to production release the XCKU11P with -2LE and -1LI speed/temperature grades in Vivado Design Suite
2017.4.1.
to add specific mode specificationsRevised some of the -3E and -1LI/-2LE (VCCINT = 0.72V) speed files in
Table 28, Table 40, Table 41, Table 42, Table 44, and Table 45.
12/22/2017 1.9 Revised Table 21 and Table 22 to production release the XCKU15P -1L, -2L, -1LV, and -2LV speed/
temperature grades in Vivado Design Suite 2017.4.
11/28/2017 1.8 Updated Table 20, Table 21, and Table 22 to production release the following devices/speed/temperature
grades in Vivado Design Suite 2017.4.
XCKU3P: -2LE, -1LI
XCKU5P: -2LE, -1LI
Revised the FREFCLK descriptions in Table 35. Revised the FGTYQRANGE2 -1 speed grade minimum in Table
64. Added TSPICCM2 and TSPICCFC2 to Table 81.
11/17/2017 1.7 In Table 1, corrected the minimum voltage for the System Monitor section.
Updated Table 20, Table 21, and Table 22 to production release the following devices/speed/temperature
grades in Vivado Design Suite 2017.3.1.
XCKU9P: -2LE, -1LI
XCKU13P: -2LE, -1LI
Updated speed file data for this release in Table 40, Table 41, Table 42, and Table 44. Updated the notes
for FGTYMAX in Table 64.

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Product Specification 68
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

Date Version Description of Revisions

10/05/2017 1.6 In Table 1, because the voltages are covered in Table 4, removed the note on VIN for I/O input voltage for
HD I/O banks. Updated TSOL by package in Table 1. Added Note 2 to Table 4.
Updated Table 20, Table 21, and Table 22 the XCKU11P: -2E, -2I, -1E, -1I (all VCCINT = 0.85V) to production
in Vivado Design Suite 2017.3 v1.14. Also updated speed file data for this release in Table 40, Table 41,
Table 42, Table 44, and Table 45.
08/29/2017 1.5 Updated Table 20, Table 21, and Table 22 to production release the following devices/speed/temperature
grades in Vivado Design Suite 2017.2.1.
XCKU15P: -2E, -2I, -1E, -1I (all VCCINT = 0.85V)
In Table 29, revised the TOUTBUF_DELAY_O_PAD -2 (VCCINT = 0.85V) values for DIFF_SSTL135_S,
DIFF_SSTL15_DCI_S, DIFF_SSTL15_S, DIFF_SSTL18_I_DCI_S, and DIFF_SSTL18_I_S.
Revised some of the -3E and -1LI/-2LE (VCCINT = 0.72V) speed files in Table 28, Table 29, Table 30, Table 40,
Table 41, Table 42, Table 44, and Table 45.
06/26/2017 1.4 Updated Table 20, Table 21, and Table 22 to production release the following devices/speed/temperature
grades in Vivado Design Suite 2017.2.
XCKU13P: -2E, -2I, -1E, -1I (all VCCINT = 0.85V)
Updated Note 11 in Table 2 for clarity. Revised the -3E and -1LI/-2LE (VCCINT = 0.72V) speed files in Table
28, Table 29, Table 30, Table 40, Table 41, Table 42, Table 44, and Table 45. Updated the FMAX symbol
names and values in Table 34. Added Note 1 to Table 36. Added Note 3 to Table 77.
05/08/2017 1.3 Updated Table 21 and Table 22 to production release the following devices/speed/temperature grades in
Vivado Design Suite 2017.1.
XCKU9P: -2E, -2I, -1E, -1I
Removed the MIPI_DPHY_DCI_LP standard from Table 9 (HD I/O banks never supported DCI). Revised
the minimum 32.75 Gb/s sinusoidal jitter in Table 71.
04/11/2017 1.2 Updated the Summary description. In Table 1, updated and added data, and updated Note 6, added
Note 7, Note 8, and Note 9. Updated and added data to Table 2, revised Note 11 and added Note 12 and
Note 13. Updated Table 3 and added Note 6. Added specifications to Table 4 though Table 6. Updated
maximum VICM and Note 1 in Table 18. Updated the maximum VODIFF in Table 19.
Updated Table 20, Table 21, and Table 22 to production release the following devices/speed/temperature
grades in Vivado Design Suite 2017.1.
XCKU3P: -2E, -2I, -1E, -1I
XCKU5P: -2E, -2I, -1E, -1I
Added Note 1 to Table 21. Updated Table 23. Updated Table 24 and added Note 2. Added Table 25.
Updated Table 27 and added Note 3. Many revisions to the speed specifications in Table 28, Table 29,
Table 30, Table 33, Table 34, Table 35, Table 40, Table 41, Table 42, Table 44, Table 45, and Table 46.
Updated VL and VH values in Table 31. In Table 35, added TMINPER_CLK and Note 1, and revised FREFCLK.
Added MMCM_FDPRCLK_MAX to Table 38 and PLL_FDPRCLK_MAX to Table 39. Updated Table 48. Revised the
GTH Transceiver Specifications and GTY Transceiver Specifications sections. Revised the Integrated
Interface Block for Interlaken and Integrated Interface Block for 100G Ethernet MAC and PCS sections.
Updated the System Monitor Specifications section including On-Chip Sensor Accuracy and adding Note
3 to Table 78. Removed timing diagrams from the SYSMON I2C/PMBus Interfaces section. Updated the
Configuration Switching Characteristics section. Removed the eFUSE Programming Conditions table and
added the specifications to Table 2 and Table 3. Updated Table 81. Updated the Automotive Applications
Disclaimer.
05/09/2016 1.1 In Table 1 revised VIN for HP I/O banks. Updated Note 5 in Table 3. Added values to Table 7. Added
MIPI_DPHY_DCI to Table 9, Table 10, and Table 12. Updated and added notes in Table 18 and Table 19.
Updated Table 20 speed specifications for Vivado Design Suite 2016.1. Removed Table 23, Video Codec
Unit Performance. Updated Table 24. Expanded and updated Table 27. Updated Table 28 and Table 29.
Updated Table 31 and Table 32 with MIPI D-PHY values. Updated Table 31 and Table 32. In Table 33,
added the Block RAM and FIFO Clock-to-Out Delays section. Updated Table 40 to Table 45. Revised the
symbol names in Table 44. Revised typical values in Table 50. Updated the -2 (0.72V) and -1 (0.72V) values
in Table 52. Added Table 55 and Table 67. Added Note 2 to Table 61. Revised Table 69. Revised data and
added notes to Table 64, Table 73, and Table 76. Revised INL in Table 78. Added notes to Table 79 and
Table 80. Many revised sections in Table 81.
11/24/2015 1.0 Initial Xilinx release.

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Product Specification 69
 Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics

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