VLSI Architecture and FPGA Implementation of Image Enhancement Algorithms for Medical Images

Hitendra gupta1 K.K Sharma2 S.D. Joshi3

Abstract Image enhancement is an important task in the field of image processing and is widely used in real time medical imaging systems that are used for diagnosis. A number of these systems do not produce good visual quality image that hinders the diagnosis of disease. Major attributes of these systems include real time speed and robustness. These systems also require Post-processing of the acquired images in order to improve the visibility or detect ability of the image features. The required post-processing can be done using a high speed general purpose processor (GPP) that comply with the speed requirement of these systems, but they are sensitive to the hard onsite environment conditions and also consume a significant amount of power. Dedicated hardware processing unit allows these systems to do the processing on the fly (on capture) and are robust as compared to the GPPs. In this paper, we propose a pipelined VLSI architecture of the image enhancement algorithms applicable to medical images. The implementation of these architectures onto the Xilinx SpartanIII FPGA is also included in this work. Enhancement results of these algorithms, on application to medical images for diagnosis are presented here. We also present the analysis and comparison of the hardware and operating speed of the proposed architectures in this work. The proposed architectures can easily be embedded on the existing medical imaging systems and hence enhance the speed and robustness of the complete process significantly.
Keywords Image enhancement, FPGA.

Introduction Image enhancement is a process that improves the quality (clarity) of the image for a particular task. Removing blur and noise, increasing contrast, and revealing details are examples of enhancement operations. Image enhancement approach fall into two broad categories: Spatial domain and frequency domain [1]. The term spatial domain refers to the image plane itself and approaches in this category are based on direct manipulation of pixels in an image. Frequency domain processing techniques are based on modifying the Fourier transform of an image. The spatial domain algorithms have less complex hardware and hence are computationally faster in comparison to the frequency domain algorithms. Thus, in this work we address implementing the first category of algorithms that will improve the computational speed of the imaging system significantly.

1 2

LNMIIT Jaipur. [email protected] MNIT Jaipur. [email protected] 3 IIT Delhi. :sdjoshi.iitd.ac.in

In this work Field Programmable Gate Array (FPGA) is chosen to implement image enhancement algorithms because software implementation of these requires processors (microprocessors, DSPs) that work at very high clock frequency and hence are prone to the environment conditions such as temperature, electromagnetic noise, etc. Also, at high clock frequency, the power requirement and dissipation is large [2]. Moreover, the specialized image processing programs running on a computer can not adequately handle huge amounts of high-resolution images, since their processors are produced for general use [2]. The contemporary DSPs offer enough speed and architectural features for image processing (DMA, multiple cores, vector processing, etc.), but as mentioned earlier, at the cost of high clock rates, power consumption and unit price of the devices. Moreover the algorithms designed for a DSP cannot be highly parallel without using multiple DSPs. One area where DSPs are particularly powerful is the design of floating point systems, while for ASICs and FPGAs, floating point operations are difficult to implement. For the scope of this work, this is not an issue because all the proposed architectures use fixed point operations only. In ASICs the circuit is fixed once fabricated, so it is impossible to modify the function or even optimize it. Further, except in large volume commercial application, ASICs are considered too costly for many designs. FPGAs represent reconfigurable computing technology. These consist of logical blocks and some amount of Random Access Memory (RAM), all of which are wired by a vast array of interconnects. All logic in FPGA can be rewired, or reconfigured with different purposes as many times as a designer likes. Thus, considering availability, cost, design cycle and ease to handle these were chosen for the implementation. Further this paper is organised as follows: Section II presents the mathematics of the chosen spatial domain image enhancement algorithms. It also includes the results of algorithms on specific medical images used for diagnosis. Section III presents the proposed VLSI pipelined architectures of these algorithms. Section IV includes the results of the FPGA implementation along with the hardware and speed based comparison of each algorithm. SELECTED ENHANCEMENT ALGORITHMS A. Contrast stretching The concept of contrast stretching comprises of the piecewise linear transformation. Generally, the low-contrast images are a result of poor illumination or lack of dynamic range in the imaging sensor [1]. The basic idea behind this algorithm is to increase the dynamic range of the gray levels in the image being processed, that will in turn enhance the visibility of the image. Fig. 1 shows the nature of the transformation function [1]. Here selection of the points (a1, b1) and (a2, b2) plays a crucial role in application of this algorithm, as they decide the degree of contrast enhancement.

Fig. 1 Contrast Stretching function

Here, , and represents the slope of the linear functions. I and E represent the normalised pixel value of the original image and the enhanced image respectively. L is the intensity of the white pixel (26).

Eq. (1) models the given transformation function mathematically.

I, E = ( I a 1 ) + b 1, (I a 2 ) + b 2,

0 I a1 a1 I a 2 a2 I L 1
(1)

Fig. 2 shows the CT scan image of a liver. In this case we need to increase the contrast between the tumour and liver gray level intensities. Fig. 3 shows the result of contrast stretching algorithm. The shown results were obtained using the following parameter values: =1.2, =1.2, =1.5, b1=0.2, b2=0.3, a1=0.3, a2=0.6. On visual inspection we can find the clear position of tumour presented in lever. The parameter values can be varied or made adaptive depending upon the degree of contrast enhancement required as well as upon the application.

Fig. 2

Fig. 3

Fig. 2 CT scan image of liver (original image) Fig. 3 Enhanced image after applying contrast stretching B. Image negative The negative of an image with gray levels in the range [0, L-1] is obtained by using the negative transformation as shown in Fig. 4,

Fig. 4 Negative Function Mathematically, it is given by:

E = L 1 I

(2)

reversing the intensity levels of an image in this manner produces the equivalent of a photographic negative. This type of processing is particularly suited for enhancing white or gray detail embedded in dark

regions of an image, especially when the black area is dominant in size. Mammogram is a class of medical image where we require finding the region of micro-calcification (typically white region) in the image, which is the symbol of the breast cancer as shown in Fig. 5 [1].

Fig. 5

Fig. 6

Fig. 5 Mammogram scan (original image) Fig. 6 Enhanced image after applying image negative Obtaining negative of the following image makes the whiter regions more prominent and clearly visible. The result of image negative is shown in Fig. 6 [1]. C. Log transformation enhancement algorithm The general form of the log transformation enhancement is given by: (3) E = C Log (1 + I ) This transformation maps a narrow range of low gray level values in the input image into a wider range of output levels. The opposite is true for higher values of input levels. We would use a transformation of this type to expand the values of dark pixels in an image while compressing the higherlevel values. The opposite is true of the inverse log transformation. An important characteristic of this algorithm is that it compresses the dynamic range of images with large variations in pixel values.

Fig. 7

Fig. 8

Fig. 7 Fluorescein angiography of retina (original image) Fig. 8 Enhanced image after applying log transformation Here, after applying log transformation to the fluorescein angiography image of a retina as shown in figure 7. The dynamic range of the pixels in the image increases, which in turn increases the visibility of the hole as well as retinal nerves, as showed in the enhanced image figure 8.

D. Histogram Equalization The histogram of a digital image with gray levels in the range [0, L-1] is a discrete function h(rk) = nk, where rk is the kth gray level and nk is the number of pixels in the image having gray level rk. It is a common practice to normalize a histogram by dividing each of its values by the total number of pixels in the image, denoted by n. Thus, a normalized histogram is given by P(rk) = nk/n for k = 0, 1 L-1, P(rk) gives an estimate of the probability of occurrence of gray level rk. Note that the sum of all components of a normalized histogram is equal to 1. The equation for histogram equalization is given by
Sk = T ( rk ) =

P (r )
r j J=0

k = 0,1...L-1,

n
j =0

nj

(4)

The number of different light intensities in an image often does not use the whole available spectrum and mostly accentuate a narrow spectrum. Images with such poor intensity distributions can be helped with a process known as histogram equalization, which in essence redistributes intensity distributions [3]. The result of applying the histogram equalization enhancement algorithm on a CT scan image, Figure 7 of brain is depicted in Figure 8. It is observed that the visibility and detect ability of the disease called obscuration of the lentiform nucleus, which is one of the early signs of acute cerebral artery infraction (ACAI), in CT brain images. In ACAI disease the blood goes through in our brain with very high speed, in this condition any vein in our brain can be damaged [4][5]. This is shown in figure by dark black spots.

Fig. 9

Fig. 10

Fig. 9 CT scan image of brain (original image) Fig. 10 Enhanced image after applying histogram equalization Proposed VLSI Architectures A. Contrast stretching enhancement algorithm Description of the datapath: The given architecture (Fig. 9) shows the datapath of the contrast stretching algorithm. Here, since we are dealing with the point processing algorithms, so each pixel I (8 bit), is processed at a time. Initially the pixel that is stored

in the input register is compared using an 8 bit comparator in order to find the range, in which the pixel lies. If the pixel lies between 0 and a1, a1 and a2 and a2 and L-1 then the outputs c2, c1 and c0 of the comparator becomes high respectively. Output c2, triggers the multiplication of input pixel with a constant (8 bit). Further the outputs c1 and c0 of the comparator are connected as select lines of a 4:1 Multiplexer in order to select the values of b1 and b2 that is to be subtracted from the input pixel I.

Fig. 9

c1 and c0 are also acting as select lines of another 4:1 multiplexer as shown in the figure that decides whether the input values of the multiplier will be (beta) or (gamma), which are constants stored in respective registers. The output of this multiplexer and that of the subtractor are then multiplied. This multiplier has two possible outputs i.e. *(I - a1) and *(I - a2). A 4:1 multiplexer is used here that selects the constants either b1 or b2 which is further added to the output of the above multiplier. We now obtain the output of the adder as either (b1 + (I-a1)) or (b2 + (I-a2)). Here, we connect a 2:1 multiplexer in order to select the final transformed output, which is either of the first multiplier (*I) or of the adder. This final pixel value is then stored in the output register. Each pixel of the image is then transformed by this pipelined hardware [6] architecture. The multipliers mentioned above are using fixed point arithmetic [7] which reduces the complexity of the hardware significantly B. Image negative enhancement algorithm Description: Fig. 10 shows the RTL level block diagram of image negative algorithm. Here, the input pixel value of an image is subtracted from the maximum gray value L minus 1. Here the value of L, depending upon the input image is stored in the register, from which one and input pixel I is further

subtracted as shown. Each pixel of the input image is transformed in a pipelined fashion using this hardware architecture.

Fig. 10

Fig. 10

C. log transformation enhancement algorithm Description: The above figure shows the RTL level block diagram of the log transformation algorithm, in which the input pixel of an image is initially stored in the register. We use an 8 bit adder that adds 1 to it. The next block evaluates the logarithmic of the adder output that is further multiplied by a constant c (8 bit), and final transformed pixel S (8 bit) is then stored into the output register. The above architecture is pipelined in three stages as depicted. Here since we are using fixed point arithmetic in logarithmic as well as multiplier module, it hence reduces the complexity as well as the computation time of the overall hardware architecture significantly. D Histogram Equalization Description: The architecture for evaluating the histogram of input image is mainly composed of four units viz counters (16 bit), switching decoder (8 to 256), multiplexer, and Timing and Control module [8]. Fig.14 below shows the architecture. There are 256 counters as a replacement to the 256 locations look up table RAM. Each counter is responsible for two tasks. The first task is to calculate the number of the occurrences of the pixel gray levels that range from 0 to 255. The second task is to simultaneously accumulate the current gray level statistics with the statistics of all pixels whose values are less than the current pixel value.

Fig. 11

Fig. 12

The result of this accumulation process is the final value of the histogram equalization. Since histogram equalization calculation is performed during the phase of computing the histogram, this adds to saving the total time of computation. The switching decoder is an (8 to 256) special purpose decoder which has an eight input lines and 256 outputs. Its function differs from the normal decoders that activate a unique output for each input combination. Specifically, switching decoder has the additional property in that all the outputs associated with inputs having gray levels higher than the current pixel value are forced to take on high state. Therefore, the main function of the switching decoder is to enable the counter assigned to the current pixel and all the counters assigned to pixels whose values are greater than the current one so that the computation of histogram and transformation function are performed at the same time. Switching decoder The concept of the basic decoder circuit is to accept a set of inputs that represents a binary number and activates only a unique output that corresponds to that input number; all other outputs remain inactive. Let us consider a (3 to 8) switching decoder configuration as depicted in the truth table of table 1. The switching decoder has three inputs a, b, and c (a is the most significant bit) and eight different outputs y7 to y0. Unlike the basic decoder, more than one output could be active (high state) at a time for the corresponding binary number representing the Gray level of the image pixel at the input.
A 0 0 0 0 1 1 1 1 Input b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 y7 1 1 1 1 1 1 1 1 y6 1 1 1 1 1 1 1 0 y5 1 1 1 1 1 1 0 0 Output Y4 y3 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 y2 1 1 1 0 0 0 0 0 y1 1 1 0 0 0 0 0 0 y0 1 0 0 0 0 0 0 0

Table. 1

The switching decoder works as follows: When the input combination is 000, the y0 and all the outputs denoted by higher suffix are activated to high state. If the combination at the input is 001, y1 and all the next higher suffix outputs are high while the output denoted by the lower suffix (y0 in this case) remains at low state, when the combination at the input is 010, y2 and all the next higher suffix outputs are high while the outputs denoted by the lower suffix (in this case y0 and y1) remain low, and so forth. The easiest and straight forward way to implement the switching decoder is to the normal decoder of the same size. The switching decoder is then simply composed of a normal decoder with every output ORed with the next output denoted by higher suffix. The equivalent logic circuit is described by the following logic equations:

y0 = q0 yn = qn + yn 1 n = 1, 2.........255.
(5) As shown in the block diagram of Fig 12, the size of the switching decoder used is an (8 to 256) and it has the same function and perform the same switching behaviour, but in a larger scale. The Control FSM of histogram equalization is shown in Fig. 13. Here the architecture is pipelined into 12 states. In State1 the input pixel value is loaded in to the register. In State2 and State3 the decoder is activated and it performs its function as described in the previous section. In State5 the decoder output enables the respective counter that is assigned to the current pixel. In State6 and State7 the counters are incremented and State8 is used to check whether all the input image pixels are processed, if not then this process is repeated for all pixels of the input image. In the next state i.e. State9 multiplexer is enabled in order to select a location in the transformation look up table (memory). State10 is used to increment the select signal of the multiplexer by 1 from 0 to 255. In the next subsequent state the address of the look up table is incremented. This address is of the look up table RAM (256X8) at which the output of multiplexer (value of the histogram as output of counters) is stored. This address is then incremented by 1. At last when all pixels will be processed then done signal will be 0. In State12 it is checked whether all pixels of the transformed image have been read out, If yes, then completion of the process is indicated through a signal else the address is further incremented.

STATE 0

STATE 1

. .
STATE 5

STATE 6

STATE 7

STATE8 8

. .
STATE 11

Fig. 13 Control FSM

STATE 12

Hardware comparison of the Enhancement Algorithms: No of slices 26/3584 (0.8 %) 14/3584 (0.5 %) 19/3584 (0.5 %) 1741/3584 (48%) Table. 2 Conclusions The pipelined VLSI architectures implemented on Field Programmable Logic Devices (FPGA) provides a constant, strictly defined latency and throughput of the image enhancement path, which fulfills the main condition of real-time medical imaging systems. The cost of the proposed implementations is relatively low, and will decrease with FPGA chips enhancement. Implementing the algorithms is well supported by widespread design tools (VHDL compilers, libraries, etc.). Issues like power consumption and size of the devices encourages the manufacturers to embed the processor into the medical image sensing unit. Moreover, the possibility to implement the selected processor in FPGA provides means of Max frequency (MHz) 66.988 299.312 Min period (ns) 14.928 3.341 2.816

Algorithms Contrast Stretching Image Negative Log Transformation Histogram Equalization

355.114 226.552

4.414

implementing the required low level post-processing and additional, high level procedures (image analysis, pattern recognition, etc.). Future Work As seen from table 2, the first three algorithms take minimal number of slices in comparison to the implementation of histogram equalization. Thus combining all the four will not make much difference in the hardware count but will in turn increase the flexibility and versatility of the processor to a greater extent. Thus, future work is in direction of combining all the four architectures into one with maximum resource sharing. This will be done in such a manner that one can control the selection of either of the algorithms based on the application or the equipment used for the diagnosis. Acknowledgements We heartily acknowledge the valuable inputs from Prof. R. Sharan, Lalit Jiwani and the coding for simulation by Mukta Sharma is also acknowledged. References [1] R. C. Gonzales and R. E. Woods, Digital Image Processing. PrenticeHall, 2002. [2] Marek Wnuk, Remarks on Hardware Implementation of Image Processing Algorithms Int. J. Appl. Math. Comput. Sci., 2008, Vol. 18, No. 1, 105110 [3] A.K. Jain, Fundamentals of digital image processing, PHI Publication. [4] Du-Yih Tsai1, Noriyuki Takahashi1, and Yongbum Lee, An Adaptive Enhancement Algorithm for CT Brain Images, Proceedings of the 2005 IEEE Engineering in Medicine and Biology 27th Annual Conference Shanghai, China, September, 2005. [5] Joanna M. Wardlaw FRCP, FRCR, MD Orell Mielke, MD, Early Signs of Brain Infarction at CT: Observer Reliability and outcome after Thrombolytic TreatmentSystematic Review1 Radiology, May 2005, 235, 444-453. [6] S. Cadambi, J. Weener, S.C. Goldstein, H. Schmit, D.E. Thomas, Managing Pipeline-Reconfigurable FPGAs, Proceedings of the 1998 ACM/SIGDA 6th international symposium on Field Programmable Gate Arrays, pp. 55-64. [7] http://en.wikipedia.org/wiki/Fixed-point_arithmetic [8] B. Lianfa, L. Xing, C. Qian, and Z. Baomin, The hardware design of a real-time infrared image enhancement system, IEEE Int. Conf. Neural Networks & Signal Processing. Dec. 2003, pp. 1009-1012. [9] VHDL: programming by example, Douglas L. Perry, McGraw-Hill publication. [10] Xilinx, Spartan-III Platform FPGAs: Complete Data Sheet, XC3SPQ208 March 1, 2005.