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Lab - VHDL Multiplexer With A Clock

This document contains VHDL code for a 4-bit multiplexer with a clock. It uses a case statement to select one of the 4 data inputs (a, b, c, d) to output based on the 2-bit address value. The output is only updated on the rising edge of the clock. A testbench is provided that simulates different input combinations over time to test the multiplexer functionality.

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Iulia Popescu
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41 views

Lab - VHDL Multiplexer With A Clock

This document contains VHDL code for a 4-bit multiplexer with a clock. It uses a case statement to select one of the 4 data inputs (a, b, c, d) to output based on the 2-bit address value. The output is only updated on the rising edge of the clock. A testbench is provided that simulates different input combinations over time to test the multiplexer functionality.

Uploaded by

Iulia Popescu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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4-bit multiplexer with clock, case when instruction, VHDL code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mplex is
port(
a,b,c,d: in std_logic;
s: in std_logic_vector (1 downto 0);
f: out std_logic;
Clock: in std_logic);
end mplex;
--four data ports and 2bit address vector

architecture Behavioral of mplex is

begin
process (Clock) is
begin
--addressing is active only when the rising edge is detected otherwise no action
if (rising_edge(Clock)) then
--choosing data from the required input based on address
case s is
when "00" => f <= a;
when "01" => f <= b;
when "10" => f <= c;
when others => f <= d;
end case;
end if;
end process;
end Behavioral;

Testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY muxtb IS
END muxtb;

ARCHITECTURE behavior OF muxtb IS

COMPONENT mplex
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
s : IN std_logic_vector(1 downto 0);
f : OUT std_logic;
Clock : IN std_logic
--clock belongs to standard logic it exhibits transitions between 0 and 1
);
END COMPONENT;

--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';
signal d : std_logic := '0';
signal s : std_logic_vector(1 downto 0) := (others => '0');
signal Clock : std_logic := '0';
--initial values are assigned

--Outputs
signal f : std_logic;

-- Clock period definitions


constant Clock_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: mplex PORT MAP (
a => a,
b => b,
c => c,
d => d,
s => s,
f => f,
Clock => Clock
);

-- Clock process definitions


Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
--clock will be periodic half period is 0 the other half is 1 rising edge can be observed

if NOW > 200 ns then


wait;
end if;
--some simulators work with "wait" ghdl doesnt stop the run so we end it manually after 200 ns

end process;

-- Stimulus process
stim_proc: process

begin
wait for 3 ns;
--I don't want the clock and data change at the same time, I delay by 3 ns

s <= "00";
a<='1';
b<='0';
c<='0';
d<='0';
--checking if data is taken from input a
wait for 10 ns;
a<='0';
--checking again if data is taken from input a
wait for 10 ns;
a<='1';
s<="01";
wait for 10 ns;
b<='0';
--checking if output data is updated based on b
wait for 10 ns;
b<='1';
--checking if output data is updated based on b
s<="10";
wait for 10 ns;
c<='0';
wait for 10 ns;
c<='1';
s<="11";
wait for 10 ns;
d<='0';
wait for 10 ns;
d<='1';
wait for 10 ns;
a<='0';
b<='0';
c<='0';
d<='0';

if NOW > 200 ns then


wait;
end if;
--some simulators work with "wait" ghdl doesnt stop the run so we end it manually after 200 ns
end process;

END;

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