NIRMA UNIVERSITY

SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY

M.Tech. in Electronics & Communication Engineering (VLSI Design)

M.Tech. Semester-II
w.e.f. 2022-23

Teaching Scheme Examination Scheme

(hours/week)
Course Course Name
Code Duration Component Weight age
L T P C Hours
SEE CE LPW SEE
3EC1223 VLSI Design Testing and 3 - 2 4 3.00 0.4 0.2 0.4
Verification
3EC12D1XX Department Elective – I 3 - - 3 3.00 0.6 - 0.4
3EC12D2XX Department Elective – II 3 - - 3 3.00 0.6 - 0.4
3EC12D3XX Department Elective – III 2 - 2 3 3.00 0.4 0.2 0.4
3SS1201 Research Methodology and 2 - - 2 - 1.00 -
IPR
3EC1224 Minor Project - - 10 5 - - 1.00
TOTAL 13 - 14 20

List of Electives
Department Elective I (3EC12D1XX) Faculty Name
Department Elective II (3EC12D2XX ) Faculty Name
3EC12D101 VLSI Signal Processing Dr. Manish Patel
3EC12D201
3EC12D106 IC
Low
Department ElectiveFabrication
Power Technology
VLSI Design
III (3EC12D3XX) Prof. Jayesh
Dr. Usha Patel
Mehta
Faculty Name
3EC12D206
3EC12D104 MemoryCMOS RF Technology
Circuit Design Dr. Piyush Bhatasana
Akash Mecwan
3EC12D305
3EC12D204 VLSI Advanced
System Topics
on Chip in VLSI Dr.Dr. Usha
ManishMehta
Patel
Testing and Verification
3EC12306 Advanced Processor Architecture Dr. Vijay Savani
3EC12D304 MEMS Design Dr. Vijay Savani
L=Lecture, T=Tutorial, P=LPW, C=Credit, SEE=Semester End Exam, LPW=Lab/Project Work,
CE=Continuous Evaluation

NIRMA UNIVERSITY
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
M.Tech. in Electronics & Communication Engineering (VLSI Design)
M.Tech. Semester - II
Department Elective I
L T Practical component C

LPW PW W S

3 - - - - - 3
Course Code 3EC12D101
Course Title VLSI Signal Processing
Course Learning Outcomes (CLOs):

At the end of the course, students will be able to -

1. Estimate the iteration bound of given digital systems using data flow graph representation.
2. Apply pipelining and parallel processing to improve speed and power performance of the digital
systems.
3. Perform folding, unfolding and retiming operations on the given digital systems.
4. Design digital processing systems architecture for performance improvement in terms of area,
power and speed.

Syllabus: Teaching Hours:45

UNIT I: Introduction to DSP Systems 06
Typical DSP algorithms, Representation of DSP Algorithms, Data Flow Graph
Representations, Loop Bound and Iteration Bound, Algorithms for Computing iteration
Bound.
UNIT II: Pipelined and Parallel Processing 04
Pipelining of FIR Filters, Parallel Processing, Pipelining and Parallel Processing for Low
Power
UNIT III: Retiming, Folding and Unfolding 11
Parallel FIR Filters, Retiming of DSP Systems, Data Flow Graph Algorithms for retiming
Definitions Properties, Retiming Techniques, Algorithms for Unfolding, Folding
Transformations, Folding of Multirate Systems
UNIT IV: Systolic Architecture and Filter Structures 08
Applications Systolic, Systolic Array Design, FIR Systolic Arrays, Matrix Multiplication and
2D Systolic Array Design, Digital Basic Lattice Structure and Schur Algorithm, Pipelining of
Lattice IIR Digital Filters, Low power CMOS Lattice IIR Filters .
UNIT V: Fast Convolution 05
Cook - Toom Algorithm, Winograd Algorithm, Iterated Algorithm, Cyclic Convolution,
Design of fast convolution Algorithm.
UNIT VI: Bit Level Arithmetic Architectures 05
Parallel Multipliers, Bit Serial Multipliers, Bit Serial Filter Design and Implementation,
Canonic Signed Digit Arithmetic, Distributed Arithmetic
UNIT VII: Synchronous, Wave, Asynchronous Pipelines and Low Power Design 06
Synchronous Pipelining and Clocking Styles, Clock Skew and Clock Distribution in Bit Level
Pipelined VLSI Designs, Wave Pipelining, Asynchronous Pipe-lining, Scaling versus Power
Consumption, Power Reduction Techniques, Power Estimation Approaches.

Self-Study:
The self-study contents will be declared at the commencement of Semester. Around 10% of the
questions will be asked from self-study contents.

Suggested Readings:
1. VLSI Digital Signal Processing systems, Design and Implementation by Keshab K.Parthi,
Wiley, Inter Science
2. Digital Signal Processing with FPGA by Uwe, Meyer-Bease, 3rd Springer
 NIRMA UNIVERSITY
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
M.Tech. in Electronics & Communication Engineering (VLSI Design)
M.Tech. Semester - II
Department Elective I
L T Practical component C
 LPW PW W S

3 - - - - - 3

Course Code 3EC12D106

Course Title Low Power VLSI Design
Course Learning Outcomes (CLOs):

At the end of the course, the students will be able to -

1. Analyze the static and dynamic power dissipation for CMOS digital designs.
2. Estimate power dissipation at different abstraction levels using simulation and probability
techniques.
3. Apply low power schemes at architecture and circuit level.

Syllabus: Teaching Hours: 45

UNIT I: Need for Low Power VLSI Chips 08

Charging and discharging of capacitance, short circuit currents in CMOS circuit, CMOS leakage
current, Static current, Basic Principles of low power Design, low power figure of merit
UNIT II: Power Analysis 08
Simulating at various abstraction level like circuit, gate, architecture level for power estimation,
UPF (unified power format), Probabilistic power analysis: Random logic signals, probability &
frequency, probabilistic power analysis techniques, signal entropy
UNIT III: Low Power Design at Circuit and Logic Level 12
Transistor and gate sizing, equivalent pin ordering, Network restructuring and reorganizing,
Special latches and flip flop, low power digital cell library, Adjustable device threshold voltage,
Gate reorganization, signal gating, logic encoding, state machine encoding, Pre computation logic
UNIT IV: Special Techniques 03
Power reduction in clock network, CMOS floating node, low power bus, Delay balancing, low
power techniques for SRAM
UNIT V: Low power Architecture and Systems 05
Power performance Management, Switching activity reduction, Parallel architecture for voltage
reduction
UNIT VI: Advance Techniques for Power Reduction 04
Adiabatic computation, Pass transistor logic synthesis, Asynchronous circuits
UNIT VII Low Power Testing 05
Introduction, sources of excessive Power dissipation during testing, power dissipation estimation,
test power optimization.

Self-Study:
The self-study contents will be declared at the commencement of Semester. Around 10% of the
questions will be asked from self-study contents.

Suggested Readings:
1. Gary K. Yeap, Practical Low Power Digital VLSI Design, Kluwer
2. Rabaey, Pedram, Low Power Design Methodologies, Kluwer
3. Kaushik Roy, Sharat Prasad, Low-Power CMOS VLSI Circuit Design, Wiley
4. Kint-Seng and Kaushik Roy, Low Voltage Power VLSI Subsystems, TM
5. Anantha Chandrakasan, Low Power CMOS Design, IEEE Press
 NIRMA UNIVERSITY
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
M.Tech. in Electronics & Communication Engineering (VLSI Design)
M.Tech. Semester - II
Department Elective I
L T Practical component C

LPW PW W S

3 - - - - - 3

Course Code 3EC12D104

Course Title CMOS RF Circuit Design
Course Learning Outcomes (CLOs):
At the end of the course, students will be able to -
1. Evaluate receiver architectures based on the RF performance parameters.
2. Analyse high frequency MOS based circuits working under Linear or Saturation Region.
3. Design and implement RF integrated circuits using active and passive components for given
specifications.

Syllabus: Teaching Hours:45

UNIT I: Introduction and Transmission Media 04
Introduction and applications of RF systems. RF systems – Basic architectures, Transmission
media and reflections, Maximum power transfer.
UNIT II: RF Concepts 05
Smith Charts, Two Port networks, Noise, Non-linearity, Sensitivity and Dynamic Range.
UNIT III: RLC Circuits using MOS 04
Matching networks basics, Pi network, T network, RL, RC and RLC matching circuits,
Fabrication of passive Devices using MOS.
UNIT VI: Noise 04
Types of noises, Noise in MOSFETs, Noise modelling for CMOS, Intrinsic MOS noise
parameters, Noise figure.
UNIT V: LNA and Mixer 09
Power match versus noise match, Large signal performance, Mixer basics, single balanced
mixers, double balanced mixers.
UNIT VI: RF Power Amplifiers 06
Class A, AB, B, C amplifiers, Class D, E, F amplifiers.
UNIT VII: Phase Lock Loops, Oscillators and Frequency Synthesizers 13
Linearized PLL models, Phase detectors, charge pumps, Loop filters, Resonators, Negative
resistance, Oscillators, Frequency division, Integer-N synthesis, Fractional frequency
synthesis, NCO and DDS

Self-Study:
The self-study contents will be declared at the commencement of Semester. Around 10% of the
questions will be asked from self-study contents.

Suggested Readings:
1. Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge
University Press
2. Behzad Razavi, RF Microelectronics, Prentice Hall of India
3. Bosco Lenug , VLSI for Wireless Communication, Prentice Hall of India
4. Robert Caverly, CMOS RF IC Design Principles, Artech House.
5. M. Jamal Deen, Tor A. Fjeldly, CMOS RF Modelling characterization and application, World
Scientific Publication
 NIRMA UNIVERSITY
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
M.Tech. in Electronics & Communication Engineering (VLSI Design)
M.Tech. Semester - II
Department Elective II
L T Practical component C

LPW PW W S

3 - - - - - 3

Course Code 3EC12D201

Course Title IC Fabrication Technology
Course Learning Outcomes (CLOs):

At the end of the course, students will be able to -

1. Comprehend use of materials and parameters involved in the wafer preparation.
2. Illustrate and list the processes involved in fabrication of VLSI circuits.
3. Visualize the complete VLSI fabrication flow from wafer preparation to packaging .

Syllabus: Teaching Hours:45

UNIT I: Crystal Growth and Wafer Preparation 05

Introduction, electronic grade silicon, material properties, crystal growth, silicon shaping,
clean room
UNIT II: Epitaxy 05
Introduction, wafer-phase epitaxy, molecular beam epitaxy, silicon on insulator, epitaxial
evaluation
UNIT III: Oxidation 10
Thin oxides, peroxidation cleaning, dry and wet oxidation, high pressure oxidation, oxidation
of polysilicon, oxidation induced defects
UNIT IV: Lithography 05
Lithography techniques: optical lithography, electron beam lithography, ion beam
lithography, comparisons of lithography techniques
UNIT V: Doping, Diffusion and Ion Implantation 10
Doping technology, Deposition of films using chemical vapour deposition (CVD), Low
pressure chemical vapour deposition LPCVD and Sputtering Techniques, ion implantation
techniques
UNIT VI: Device and Circuit Fabrication 05
Isolation, self-alignment, metallization, NMOS IC technology, CMOS IC technology,
Advancement in IC fabrication technology including 3D IC
UNIT VII: Packaging 05
Package types, packaging design consideration, package fabrication technology, advanced
packaging

Self-Study:
The self-study contents will be declared at the commencement of Semester. Around 10% of the
questions will be asked from self-study contents.

Suggested Readings:
1. S. M. Sze, VLSI Technology, Second Edition, McGraw-Hill
2. S. K. Gandhi, VLSI Fabrication Principles, Second Edition, John Wiley & Sons
3. James Plummer, M. Deal and P.Griffin, Silicon VLSI Technology, Prentice Hall     Electronics
and VLSI series.
 NIRMA UNIVERSITY
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
M.Tech. in Electronics & Communication Engineering (VLSI Design)
M.Tech. Semester - II
Department Elective II
L T Practical component C

LPW PW W S

3 - - - - - 3

Course Code 3EC12D206

Course Title Memory Technology
Course Learning Outcomes (CLOs):

At the end of the course, the students will be able to -

1. Comprehend the architecture of RAM and non-volatile memory.
2. Apply reliability modelling and failure modes to memory design.
3. Design the memory cell using advanced technology.

Syllabus: Teaching Hours:45

UNIT I: Static Random Access Memory Technologies 10

MOS RAM technologies, SRAMs, architecture, SRAM cell and peripheral, Circuit
operation, SRAM Technologies, SOI Technology, advanced SRAM architectures and
technologies, DRAM technology development, CMOS DRAMs cell, theory and
advanced cell structures
UNIT II: Embedded Memory Designs 08
Nonvolatile memories, MOS ROMs, PROMs, EPROMs, One-Time Programmable
EPROMS, EEPROM technology and architecture, Nonvolatile SRAM-Flash
Memories, advanced Flash Memory architecture
UNIT III: Failure Memory Directions 09
Memory failure modes, reliability modelling, Prediction design for reliability,
reliability test structures, reliability screening and qualification, radiation effects,
radiation hardening, process and techniques, Radiation hardened memory
characteristics, soft errors
UNIT IV: Advanced Memory Designs 08
Ferroelectric random access memories (FRAMs), Gallium arsenide FRAMs, Analog
memories, Magneto resistive RAMs, Experimental memory devices, Memory hybrids
and MCMs (2D), Memory stacks and MCMs(3D), memory cards, high density memory
packaging
UNIT V Memory Testing 10
RAM Fault Modeling, Memory Testing Algorithms, Electrical Testing, Pseudo
Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing,
IDDQ Fault Modeling and Testing-Application Specific Memory Testing

Self-Study:
The self-study contents will be declared at the commencement of Semester. Around 10% of the
questions will be asked from self-study contents.
Suggested Readings:
1. Ashok K. Sharma, Advanced Semiconductor Memories: Architectures, Designs, and
Applications, John Wiley
2. Ashok K. Sharma, Semiconductor Memories Technology, Testing and Reliability, IEEE
Press
3. Kiyoo Itoh, VLSI Memory Chip Design, Springer International Edition
4. Santosh K. Kurinec, Krzysztof Iniewski, Nanoscale Semiconductor Memories:
Technology and Applications, CRC Press
 NIRMA UNIVERSITY
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
M.Tech. in Electronics & Communication Engineering (VLSI Design)
M.Tech. Semester - II
Department Elective II
L T Practical component C

LPW PW W S

3 - - - - - 3

Course Code 3EC12D204

Course Title VLSI System on Chip
Course Learning Outcomes (CLOs):

At the end of the course, students will be able to -

1. Analyze modeling styles for design of system on chip.
2. Design data path architectures and solve intra-chip communication issues for given system on
chip.
3. Apply partitioning and floor planning algorithms for effective system on chip design.
4. Utilize System Verilog, TLM, and System C for modeling and testing of system on chip.

Syllabus: Teaching Hours:45

UNIT I: Introduction 05
System on Chip technology challenges, System on a Chip (SoC) components, SoC design
methodology.
UNIT II: SoC Architecture 07
Parameterized SoC, SoC peripheral cores, SoC and Interconnect Centric Architectures
UNIT III: System Level Design 09
System level design representations and modelling languages, Target architecture models,
Intra-chip communication, Graph partitioning algorithms, Floor planning algorithms, Task
time measurement
UNIT IV: Synthesis and Timing Analysis 09
Interconnect latency modelling, Back annotation of lower level timing to high-level models,
Synthesis of SoC components.
UNIT V: SoC Verification and Testing 15
System level verification, Block level verification and Hardware/Software Co-verification
using System C, TLM, System Verilog, Emulation, Physical Verification.

Self-Study:
The self-study contents will be declared at the commencement of Semester. Around 10% of the
questions will be asked from self-study contents.

Suggested Readings:
1. Wayone Wolf, Modern VLSI Design: SOC Design, Pearson Education.
2. Prakash Rashnikar, Peter Paterson, Lenna Singh, System-on-a-Chip, Verification Methodology &
Techniques, Kluwer Academic Publishers.
3. Alberto Sangiovanni Vincentelli, Surviving the SOC Revolution: A Guide to Platform based
Design, Kluwer Academic Publishers.
4. J. Bhasker, A System C Primer, Star Galaxy.
 NIRMA UNIVERSITY
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
M.Tech. in Electronics & Communication Engineering (VLSI Design)
M.Tech. Semester - II
Department Elective III
L T Practical component C

LPW PW W S

2 - 2 - - - 3

Course Code 3EC12D305

Course Title Advanced Topics in Verification and System Verilog
Course Learning Outcomes (CLOs):

At the end of the course, the students will be able to -

1. Use the concept of Object-Oriented Programming for verification
2. Develop the higher level testbench using System Verilog
3. Choose effective methods for verification of complex digital designs.

Syllabus: Teaching Hours: 30

UNIT I: Timing Analysis 04

Importance, Issues and Challenges, Static and Dynamic Timing Analysis, Set-up and
Hold Violation and Remedies
UNIT II: Logic and Fault Simulation 04
Introduction, Simulation Methods, Logic Simulation, Fault Simulation, Serial and
Parallel fault simulation
UNIT III: Higher Level Verification Guidelines 06
Constrained Random Stimulus, Testbench Components, Layered Testbenches, Code
Reuse
UNIT IV: Data Types, Procedural Statements and Routines 05
Data Types, Types of Arrays, Packages, Tasks, Functions, Void Functions, Time
Values, Case study
UNIT V: OOPS for Testbench 06
OOPS Terminology, Class Methods, Building a testbench using OOPs
UNIT VI: Functional Coverage 05
Gathering Coverage data, Coverage types, Functional Coverage Strategies, Anatomy
of a cover group, Analyzing coverage data

Self-Study:
The self-study contents will be declared at the commencement of Semester. Around 10% of the
questions will be asked from self-study contents.

Laboratory Work:
Laboratory work will be based on the above syllabus with a minimum of 10 experiments to be
incorporated.

Suggested Readings:
1. Jenick Bergeron, Writing Testbenches using System Verilog, Springer
2. Spear, Chris, Tumbush, Greg, System Verilog for Verification-A Guide to Learning the
Testbench Language Features, Springer
 NIRMA UNIVERSITY
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
M.Tech. in Electronics & Communication Engineering (VLSI Design)
M.Tech. Semester - II
Department Elective III
L T Practical component C

LPW PW W S

2 - 2 - - - 3

Course Code 3EC12D306

Course Title Advanced Processor Architecture

Course Learning Outcomes (CLOs):

At the end of the course, the students will be able to -

1. Comprehend architecture of modern controller and bus protocols for embedded systems.
2. Apply the compiler techniques to exploit the instruction-level parallelism.
3. Analyze the performance of symmetric and distributed shared memory-based multiprocessors.

Syllabus: Teaching Hours:30

UNIT I: Processor Architecture Fundamentals

Classification of Processor Architectures, Instruction set principles, Memory Hierarchy 04
Design, Measuring and Reporting performance
UNIT II: Instruction Level Parallelism 07
Pipeline concept, Classification of Pipeline Processors, Instruction flow and Register data
flow techniques, Compiler Techniques to exploit Instruction level parallelism
UNIT III: Multiprocessors and Thread-Level Parallelism 07
Symmetric Shared-Memory Architectures, Performance of Symmetric Shared-Memory
Multiprocessors, Distributed Shared Memory and Directory-Based Coherence, Thread level
parallelism
UNIT IV: ARM Microcontroller Architecture 07
Block Diagram, Features, Memory Mapping Memory Controller (MC), Memory Controller
Block Diagram, Address Decoder, External Memory Areas, Internal Memory Mapping,
External Bus Interface (EBI), Organization of the External Bus Interface, EBI Connections to
Memory Devices, External Memory Interface, Write Access, Read Access, Wait State
Management, Memory Management Units, details of the ARM MMU, ARM Instruction Set,
Thumb Instruction Set and Interrupt
UNIT V: Bus Standard 05
Introduction to Serial and Parallel Bus standard, PCI, AXI

Self-Study:
The self-study contents will be declared at the commencement of Semester. Around 10% of the
questions will be asked from self-study contents.
Laboratory Work:
Laboratory work will be based on above syllabus with minimum 10 experiments to be incorporated.

Suggested Readings:
1. John L. Hennessy, David A. Patterson, Computer Architecture: A Quantitative Approach,
Elsevier
2. John Paul Shen and Mikko H. Lipasti, Modern Processor Design Fundamentals of Superscalar
Processors, TMH
3. Behrooz Parahami, Computer Architecture from Microprocessor to Super Computer, Oxford.
4. Steve Furber, ARM System- On- Chip Architecture, Pearson Education Asia
5. Andrew N Sloss, Dominic Symes, Chris Wright, ARM System Developer’s Guide - Designing
and Optimizing System Software, Elsevier
 NIRMA UNIVERSITY
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
M.Tech. in Electronics & Communication Engineering (VLSI Design)
M.Tech. Semester - II
Department Elective III
L T Practical component C

LPW PW W S

2 - 2 - - - 3

Course Code 3EC12D304

Course Title MEMS Design
Course Learning Outcomes (CLOs):

At the end of the course, students will be able to -

1. Comprehend the concepts of advanced Micro/Nano fabrication technologies.
2. Develop the applications of MEMS in area of optical, modulators, switches, and displays.
3. Apply design techniques of RF MEMS switches, relays, varactor, phase shifter, antennas.

Syllabus: Teaching Hours:45

UNIT I: Introduction to MEMS 08
Advanced Micro/Nano Fabrication Technologies: Plasma physics, ICP etch, Deep Si etch,
Deep oxide etch, Surface micromachining, Bulk micromachining: multiple wafer stack, SOI,
SCREAM, CMOS-MEMS: Thin-film, bulk, DRIE, CMOS-based Sensors and Interface
Circuits Design
UNIT II: Electrical, Mechanical and Optical properties of MEMS material 10
Chemical, Thermal, Inertial, Interface circuit design, Optical MEMS: Fundamentals of light:
Propagation, Interference, Doppler Effect, Polarization, Coherence, Micromirrors, Microlens;
Microgratings Corner cube reflectors, Optical communications, case study
UNIT III: Applications of MEMS 10
Phase modulators, attenuators, switches, Displays, Scanners, Biosensors, Spectroscopy
UNIT IV: RF MEMS 13
RF MEMS switches and Micro Relays, MEMS varactors and inductors, MEMS phase
shifters and filters, Micro machined Antenna, case study
UNIT V: MEMS Packaging 04
Packaging design, materials, Packaging techniques: Bonding, Sealing, Dicing, Wafer-level
packaging, Packaging for medical, aerospace and RF MEMS applications

Self-Study:
The self-study contents will be declared at the commencement of Semester. Around 10% of the
questions will be asked from self-study contents.

Laboratory Work:
Laboratory work will be based on above syllabus with minimum 10 experiments to be incorporated.

Suggested Readings:
1. G. Kovacs, Micromachined Transducers Sourcebook, McGraw-Hill
2. S. Senturia, Microsystem Design, Kluwer Academic Publishers
3. M. Madou, Fundamentals of Microfabrication, Chemical Rubber Company Press
4. G. Rebeiz, RF MEMS: Theory, Design and Technology, John Wiley & Sons
5. B. Bouma and G. Tearney, Handbook of Optical Coherence Tomography, Marcel Dekker Inc