J Comput Electron (2017) 16:896–906

DOI 10.1007/s10825-017-1022-7

On fault-tolerant design of Exclusive-OR gates in QCA

Dharmendra Kumar1 · Debasis Mitra1 · Bhargab B. Bhattacharya2

Published online: 17 June 2017

© Springer Science+Business Media, LLC 2017

Abstract Design paradigms of logic circuits with quantum- proposed designs facilitates low-cost fabrication of such sys-
dot cellular automata (QCA) have been extensively studied in tems.
the recent past. Unfortunately, due to the lack of mature fabri-
cation support, QCA-based circuits often suffer from various Keywords Quantum-dot cellular automata · Fault-
types of manufacturing defects and variations and, therefore, tolerance · Exclusive-OR (XOR gate)
are unreliable and error-prone. QCA-based exclusive-OR
(XOR) gates are frequently used in the construction of sev-
eral computing subsystems such as adders, linear feedback 1 Introduction
shift registers, parity generators and checkers. However, none
of the existing designs for QCA XOR gates have considered Having matured over around six decades, CMOS technology
the issue of ensuring fault-tolerance. Simulation results also is now expected to reach its physical limit in the near future
show that these designs can hardly tolerate any fault. We [25]. The never-ending quest for smaller computing devices
investigate the applicability of various existing fault-tolerant has driven the research on alternative nanotechnologies.
schemes such as triple modular redundancy, NAND multi- Quantum-dot cellular automata (QCA) [20] has emerged as
plexing and majority multiplexing in the context of practical a possible option in recent years. In QCA, information flows
realization of QCA XOR gate. Our investigations reveal that through basic elements (referred to as cells) not by actual flow
these techniques incur prohibitively large area and delay and of current, as in conventional CMOS-based designs, but by
hence, they are unsuitable for practical scenarios. We pro- Coulombic interactions between electrons present in neigh-
pose here realistic designs of QCA XOR gates (in terms of boring cells resulting in very low power dissipation [20].
area and delay) with significantly high fault-tolerance against Other promising features of QCA technology include high
all types of cell misplacement defects such as cell omission, device packing density, high speed (in order of THz), inher-
cell displacement, cell misalignment and extra/additional cell ent pipelining [39]. Implementations of basic logic devices
deposition. Furthermore, the absence of any crossing in the in QCA have been demonstrated [39]. Design and simulation
of common digital modules (both combinational and sequen-
tial) have been studied extensively [8,9,21,22,40].
B Dharmendra Kumar As in other nanotechnologies, QCA-based circuits often
[email protected]
suffer from various types of manufacturing defects [24,
Debasis Mitra 28,38]. Experimental studies revealed that cell misplace-
[email protected]
ment defects are the most common among all such defects
Bhargab B. Bhattacharya [38]. Several types of cell misplacement defects, viz., cell
[email protected]
displacement, cell misalignment, cell omission, have been
1 Department of Information Technology, National Institute of reported in the literature so far [38]. Hence, low-cost
Technology, Durgapur, India fault-tolerant designs for such defects are needed. Fault-
2 Advanced Computing and Microelectronics Unit, Indian tolerance and thermal characteristics of fundamental QCA
Statistical Institute, Kolkata, India logic devices have been analyzed by Anduwan et al. [2].

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J Comput Electron (2017) 16:896–906 897

Errors due to random clock shifts in QCA circuits have been applied on it. In order to overcome the above shortcom-
studied by Karim et al. [15]. Ma et al. [24] presented a ings, we propose new designs of 2-input and 3-input XOR
comparative study on the applicability of a few generic fault- gates in QCA that attain significantly high fault-tolerance
tolerant schemes such as triple modular redundancy (TMR) with respect to all types of cell misplacement defects. The
[23], NAND multiplexing [31] and majority multiplexing proposed XOR designs require 85 and 124 QCA cells for
[33] in the context of reliable realization of QCA systems. 2-input and 3-input, respectively, and hence show signif-
A few new fault-tolerant QCA designs of majority gates and icantly better fault-tolerance versus area trade-off than all
adders have been reported in the literature [10,12,17,29,34]. the existing designs of QCA XOR gates. Furthermore, the
An exclusive-OR (XOR) gate is a digital logic gate that absence of any wire crossing (coplanar or multilayer) in the
results a true output (logic 1) if one, and only one, of proposed designs facilitates low-cost fabrication. Simulation
the two inputs of the gate is true. The associative nature results are presented based on semiconductor implemen-
of the exclusive-OR function implies the possibility of tation of QCA with an intermediate dot size of about
using exclusive-OR gates with three or more inputs. The 5 nm.
exclusive-OR operation with three or more variables can The rest of the paper is organized as follows. Background
be defined as an odd function where the output assumes and related prior work are discussed in Sect. 2. Section 3
logic value 1 if an odd number of variables be equal to demonstrates the applicability of TMR, NAND multiplex-
1 [26]. XOR gates are often considered as the important ing and majority multiplexing on existing QCA XOR gates.
modules in digital circuit design due to their frequent use Design and simulation of the proposed fault-tolerant 2-input
in the construction of several computing subsystems such and 3-input XOR gates are presented in Sect. 4. Detailed
as adders, linear feedback shift registers, parity generators, comparative study between the proposed XOR gates and the
parity checkers, decoders for error correction and chan- existing ones against various cell misplacement defects is
nel codes [26]. An XOR gate with three or more inputs presented in Sect. 5. Conclusions are drawn in Sect. 6.
is usually constructed by appropriately connecting two or
more than 2-input XOR gates only. However, as described
in [11], XOR gates with four or higher inputs can be effi-
2 Background and related prior work
ciently constructed with the help of 2-input and 3-input XOR
gates.
The basic element in QCA technology is referred to as cell. A
Several designs for 2-input QCA XOR gates have been
QCA cell consists of four potential wells or dots located at the
presented in recent past [1,4–6,13,14,27,30,32,35,37]. A
four corners of a square. There are two extra electrons which
multilayer 2-input XOR design is also given as sample file in
can tunnel quantum mechanically from one dot to another.
QCADesigner version 2.0.3 [41]. A few 3-input XOR gate
Due to Coulombic repulsion between these two electrons,
designs have also been presented recently [16,36]. But, both
they always occupy diagonally opposite corner dots. This
of them have used 2-input XORs and, hence, show very poor
results in two possible orientations, referred to as polariza-
performance in terms of common design parameters such as
tions ( p). Figure 1a, b shows QCA cells with p = +1 and
latency and area. Another 3-input XOR gate is proposed by
p = −1, respectively. These two polarization states are used
Angizi et al. [3] which uses alternate clock zone for wire
to represent binary information 1 and 0, respectively.
crossing. Most importantly, to the best of our knowledge,
Majority voter (MV) and inverter gates are considered
none of the XOR designs (both 2-input and 3-input) con-
as the two most fundamental building blocks of QCA. A
sidered fault-tolerance. Again, wire crossing (coplanar or
variety of MVs and inverter gates have been reported in the
multilayer), inherent to some of these designs, makes them
literature [17,29,39]. Typical designs of MV and inverter are
difficult to realize in practice [7].
shown in Fig. 2a, b, respectively. Two types of QCA wires,
In this paper, we investigate the applicability of various
namely binary wire and inverter chain, are shown in Fig. 3a,
existing fault-tolerant schemes such as TMR, NAND multi-
b, respectively.
plexing and majority multiplexing in the context of practical
realization of QCA XOR gate. Our investigations reveal
that the XOR function realized under these fault-tolerant
schemes requires a large number of cells, thereby showing
a very poor fault-tolerance versus area trade-off. Addition-
ally, these designs demand a large number of clock zones
leading to higher delay, which is unacceptable for practi-
cal realizations. For example, best existing design of 2-input (a) (b)
QCA XOR gate [5] requires 249–529 cells and 6–8 clock
zones when the above-mentioned fault-tolerant schemes are Fig. 1 QCA cell with a p = +1 and b p = −1

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898 J Comput Electron (2017) 16:896–906

XOR

XOR
B
Y
A M

XOR
(a) (b)
Fig. 2 Fundamental gates in QCA a majority gate, b inverter

Fig. 4 Block diagram of a TMR system for an XOR gate

(a) (b)
Fig. 3 Wires in QCA a binary wire, b inverter chain 3 Applicability of generic fault-tolerant schemes on
existing QCA XOR gates

To apply input to a logic device, input cell(s) are forced to Fault-tolerance of digital circuits is often achieved by adding
assume a particular state by applying external electric field. redundancy into the original design. Triple modular redun-
The input cell(s) then interact with its neighboring cells and dancy (TMR) [23] and NAND multiplexing [31] are the two
change their polarization states accordingly. The process con- most popular classical generic fault-tolerance schemes that
tinues, and finally the output cell assumes the desired state. are often employed to increase the reliability of a circuit
Note that the magnitude of the Coulomb force decreases with module. Recently, a new adaptation of NAND multiplexing
respect to distance and time. A four-phase clocking scheme referred to as majority multiplexing [33] has appeared to be
[19] is used to synchronize and control the information flow. a better alternative for nanotechnologies. In this section, we
For the last two decades, a major part of the research investigate the applicability of TMR, NAND multiplexing
on QCA has focused on the design and simulation of var- and majority multiplexing in the context of practical realiza-
ious digital modules. Designing different types of adders tion of fault-tolerant QCA XOR gate.
[8,17,22] has received considerable interest due to their In a TMR system, the original circuit module is triplicated
importance in a computing system. A conceptual design where the three copies perform the same task in parallel with
of QCA XOR gate was first presented in [39]. Note that a corresponding outputs being compared through a majority
straightforward realization of the design is not possible since voter circuit. Figure 4 shows the block diagram of a TMR
it does not consider clocking. A number of QCA imple- system for a 2-input XOR gate. TMRs can be cascaded to
mentations of 2-input XOR gate have been presented so further improve the system’s reliability at the cost of higher
far [1,4–6,13,14,27,30,32,35,37,41]. A few 3-input QCA redundancy. The basic idea behind NAND multiplexing is to
XOR gate designs have also appeared in the recent literature replace the original module by a multiplexing unit, which has
[3,16,36]. The designers have used a number of metrics such N copies of every input and output of the original unit. The
as area, latency, number of cells and the type of crossovers. multiplexing unit randomly permutates the input signals pro-
The summary of a comparative study considering these met- ducing N outputs in parallel. Figure 5 shows the basic block
rics is presented in Sect. 4 (Tables 2, 3). It is apparent that diagram of a NAND multiplexing system for a 2-input XOR
all the existing designs of 2-input XOR gates show more gate. The unit consists of two stages: the executive stage and
or less similar performances in terms of number of cells, the restorative stage. The executive stage carries out the basic
area and latency with the design proposed by Berarzadeh et function of the original unit. The restorative stage (consisting
al. [5] seems to be the best. For 3-input XOR, the design of NAND gates) is used to reduce the degradation in the exec-
presented in [3] outperforms all the designs presented in utive stage caused by faults in the original unit. Note that a
Table 3. Interestingly, none of these XOR designs has con- single stage of NAND gates in the restorative unit inverts the
sidered fault-tolerance. Considering the importance of XOR result. Hence, at least two stages are required. The restora-
module in digital circuit design, we analyze the degree of tive stage can further be iterated to improve the restoration.
fault-tolerance of these designs. Simulation results (Sect. Majority multiplexing is similar to NAND multiplexing. As
5) show that all of them perform very poorly against most shown in Fig. 6, the only difference lies with the use of major-
of the cell misplacement defects. This fact motivates us to ity gates in place of NAND gates in the restorative stage.
investigate the applicability of various existing fault-tolerant Although the generic fault-tolerant techniques discussed
schemes in the context of practical realization of QCA XOR above can tolerate a variety of faults (including cell mis-
gate. placements), the degree of redundancy is unacceptably high.

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J Comput Electron (2017) 16:896–906 899

XOR
digital computing subsystems such as adders, linear feedback
O
shift registers, parity generators and checkers. In general, an
U
XOR
n-variable exclusive-OR function is an odd function defined
B T n
U U as the logical sum of the 22 minterms whose binary numer-
A P
ical values have an odd number of 1s [26]. In conventional
U
XOR CMOS-based designs, an XOR gate with three or more inputs
T
is usually constructed by appropriately connecting two or
more 2-input XOR gates only. However, a closer look reveals
Executive Stage Restorative Stages
that this approach, especially for QCA-based design, may
Fig. 5 Block diagram of a NAND multiplexing unit for an XOR gate lead to larger area and delay. Feinstein and Thornton [11]
have shown how XOR gates with four or higher inputs can
XOR be efficiently constructed with the help of 2-input and 3-input
M M O XOR gates only. Figure 7 shows few examples demonstrating
U
B XOR the idea.
T
A U M U M This motivates us to propose fault-tolerant designs of 2-
P
XOR U
input and 3-input XOR gates in QCA.
M M T
The logical expression representing a 2-input XOR func-
tion (AB + AB) can be rewritten equivalently as
Executive Stage Restorative Stages ((A + B) + AB) using simple Boolean algebra.
As mentioned in Sect. 2, majority gate and inverter pair
Fig. 6 Block diagram of a majority multiplexing unit for an XOR
are commonly used as the basic building blocks in QCA cir-
cuits. Note that a majority gate acts as an AND gate when one
For example, a single-stage TMR system for the best 2-input
of its input cell polarization is set to −1 (logic 0). Similarly,
XOR gate [5] identified in Sect. 4 requires minimum 249
it acts as an OR gate when one of its input cell polarization
QCA cells. Moreover, the fault-tolerance of the TMR system
is set to +1 (logic 1). A NOR gate may be implemented by
strongly depends on the fault-tolerant capability of the major-
adding an inverter gate in front of an OR gate. Hence, con-
ity gate. Use of a fault-tolerant majority gate [34] may add up
sidering majority voter and inverter-based synthesis (which
more overhead (22 more cells). The situation becomes even
suits QCA-based implementation), the above expression
worse in the case of NAND multiplexing and majority multi-
plexing. Construction of a NAND multiplexing system (Fig. may also be rewritten as M[M(A, B, 1), M(A, B, 0), 1],
5) for the same XOR gate [5] requires minimum 529 cells. where M(a, b, c) represents the majority function defined as
Similarly, a majority multiplexing system (Fig. 6) requires M(a, b, c) = ab + bc + ac. Figure 8a shows the gate-level
minimum 523 cells. High degree of redundancy involved implementation of the expression.
in all the three systems makes them impractical to realize Following a similar approach, the logical expression rep-
from both the point of views of area and latency. The above resenting 3-input XOR function ( Ā B̄C + ĀB C̄ + A B̄ C̄ +
observations (summarized in Table 1) motivate us to design ABC) may be rewritten as M[ M(A,¯ B, C), C, M(A, B, C̄)].
two new practically realizable (in terms of area and delay) Figure 8b shows the corresponding gate-level implementa-
fault-tolerant XOR gates which are presented in the next sec- tion. Figure 9a, b shows the layouts of the proposed 2-input
tion. and 3-input XOR gates. As apparent from the figures, the
proposed designs consist of 85 QCA cells and 124 cells,
respectively. Assuming QCA cell size of 18 nm×18 nm with
a gap of 2 nm between two consecutive cells, the layouts con-
4 Proposed fault-tolerant XOR gate designs
sume area 0.08 µm2 and 0.10 µm2 , respectively. Moreover,
each of the designs uses 5 phases (1.25 clock cycles) of clock
As mentioned in Sect. 1, exclusive-OR operation with two or
latency and have no crossover.
more variables acts as the key elements in designing many

Table 1 Area and latency

Technique Min. #cells Min. area Latency Crossover
incurred by generic
(µm2 ) (clock phases)
fault-tolerant techniques applied
on a 2-input QCA XOR gate [5] Best XOR [5] 13 0.015 2 No
TMR 249 0.30 6 Yes
NAND-MUX 529 0.53 8 Yes
MAJ-MUX 523 0.40 8 Yes

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900 J Comput Electron (2017) 16:896–906

XOR3 XOR3 XOR3

A XOR2 A XOR3 A XOR2
B B B
C OUT C OUT C OUT

D D
E XOR3
(a) 4−Input XOR D
(b) 5−Input XOR E
F
XOR3 XOR3
A XOR3 A (c) 6−Input XOR
B B
C OUT C XOR3
A
B
XOR3 XOR3 XOR3 C
D D
E E OUT
F F XOR3 XOR3
D
G E OUT
XOR2 F
(d) 7−Input XOR G

H XOR3
G
H
(e) 8−Input XOR I

(f) 9−Input XOR

Fig. 7 Gate-level implementation of XOR gates of four and higher inputs using only 2- and 3-input XOR gates

1.00
+1 +1
1.00

OUT
M M XOR
XOR

A B A B
C
B A
M

−1 (a) -1.00

(a) (b)

XOR
Fig. 9 Layout of the proposed a 2-input XOR gate and b 3-input XOR
M M gate
C
B A

M
one of the input wires of the majority gate, we have also made
them wider (equal to two QCA cells). Moreover, to make the
(b) majority gate more robust, we have introduced an extra clock
zone. We have also used redundant cells in appropriate places
Fig. 8 Gate-level implementation of the proposed a 2-input XOR gate
and b 3-input XOR gate
of the inverters used in both the proposed XOR gates (2-
input and 3-input) to make them highly fault-tolerant against
various misplacement defects. It may be noted that QCA
The fault-tolerance of any QCA circuit against various wire crossings (both coplanar and multilayer) are also very
misplacement defects is highly dependent on the degree of prone to various misplacement defects. Accordingly, we have
fault-tolerance of its basic building blocks, i.e., majority gate designed the layouts of both the XOR gates in such a way
and inverter. Note that the QCA majority gate of Fig. 2(a) that there is no crossover (not even coplanar one).
is more susceptible to various misplacement defects at the To verify the functional behavior of the proposed XOR
central cell. To cope with this problem, we have used a 2 × gates, we carried out simulations with bistable simulation
2 tile instead of the single central cell so that the negative engine of QCADesigner [41] (version 2.0.3) with the fol-
effect caused by cell misplacement at any one of them is lowing parameters: (i) cell size: 18 nm × 18 nm with a
diminished by the presence of other three redundant cells. In gap of 2 nm between two consecutive cells, (ii) radius of
order to withstand any possible misplacement defects in any effect: 65 nm, (iii) relative permittivity: 12.9, (iv) conver-

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J Comput Electron (2017) 16:896–906 901

Simulation Results Simulation Results

max: 1.00e+000 max: 1.00e+000

A
B
min: -1.00e+000

min: -1.00e+000
max: 1.00e+000

max: 1.00e+000
C

A min: -1.00e+000

max: 1.00e+000
min: -1.00e+000
B
max: 9.84e-001
min: -1.00e+000

XOR max: 9.85e-001

XOR
min: -9.84e-001
min: -9.85e-001
max: 9.80e-022
max: 9.80e-022
CLOCK 0
CLOCK 0

min: 3.80e-023 min: 3.80e-023

max: 9.80e-022 max: 9.80e-022

CLOCK 1
CLOCK 1
min: 3.80e-023

min: 3.80e-023
max: 9.80e-022

max: 9.80e-022 CLOCK 2

min: 3.80e-023
CLOCK 2

max: 9.80e-022
min: 3.80e-023
CLOCK 3
max: 9.80e-022
min: 3.80e-023

CLOCK 3 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000

min: 3.80e-023 Fig. 11 Simulation result for the proposed 3-input XOR gate
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000

Fig. 10 Simulation result for the proposed 2-input XOR gate

QCA XOR designs is shown in Tables 2 and 3, respectively.
It is interesting to note that the proposed 3-input XOR gate
gence tolerance: 0.001000, (v) number of samples: 50000, outperforms all the existing 3-input XOR designs in terms
(vi) intermediate dot size: 5 nm. The bistable simulation of the above metrics. Although the proposed 2-input XOR
engine of QCADesigner uses intercellular Hartree approx- design cannot outperform the existing designs in terms of
imation (ICHA) assuming a simple two-state system to these metrics, it does not compromise much too for most
represent each QCA cell. A little compromise in accuracy of them. The number of cells used (and hence the area) by
as compared to full-basis computation is often compensated the proposed 2-input XOR gate is higher than the most of
by the significantly better scalability [18]. ICHA is found the existing 2-input XOR designs. However, as described in
to be valid and sufficient for verifying the functionality of the next section, the degree of fault-tolerance achieved by the
large QCA circuits. The simulation output of QCADesigner proposed design leads to a significantly better fault-tolerance
is shown in Figs. 10 and 11 for 2-input and 3-input XOR vs area trade-off as compared to other designs. In fact, fault-
gates, respectively. Note that the maximum polarization at tolerance of the proposed designs against cell misplacements
the 2-input XOR output (Pmax = 0.984) and at the 3-input is achieved at the cost of redundancy (increased number of
XOR output (Pmax = 0.985) is significantly strong. To verify cells).
the robustness of the proposed XOR gates further, we have
also simulated it for various values of radius of effect (for
example, 40 or 75 nm). The behavior of the proposed XORs 5 Comparison of proposed XOR gates with
is found to remain unaltered. The maximum polarization at existing XORs in terms of fault-tolerance
the output remains almost the same.
In order to judge the quality of the proposed designs in In this section, we demonstrate the degree of fault-tolerance
terms of the popular design metrics such as area, latency, achieved by our proposed XOR gates against different cell
number of cells and the type of crossover, we have made a misplacement defects and also present a detailed comparative
comparative study with the existing designs. The summary study with the existing XOR designs in this regard. Although
of the comparative study separately for 2-input and 3-input none of the existing XOR designs consider fault-tolerance,

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902 J Comput Electron (2017) 16:896–906

Table 2 Comparisons of
XOR gates No. of Area (µm2 ) Latency (clock Crossover
various 2-input QCA XOR gates
#cells phases)
in terms of common design
metrics [1] 32 0.030 3 Multilayer
[4] 42 0.036 3 None
[5] 13 0.015 2 None
[6] 14 0.015 2 None
[13] 58 0.062 3 None
[14] 35 0.040 3 None
[30] 41 0.044 4 None
[32] 62 0.090 6 None
[37] 28 0.022 3 None
[41] 85 0.078 4 Multilayer
Proposed 85 0.078 5 None

Table 3 Comparisons of
XOR gates No. of #cells Area (µm2 ) Latency (clock Crossover
various 3-input QCA XOR gates
phases)
in terms of common design
metrics [3] 95 0.10 5 Coplanar
[16] 98 0.12 8 Coplanar
[36] 164 0.22 10 Coplanar
[36] 136 0.18 9 Coplanar
Proposed 124 0.10 5 None

100
we reproduce them [1,4–6,13,14,16,30,32,36,37,41] and
Fault tolerance against single cell

simulate them with bistable simulation engine of QCADe- 80

omission defect (%)

signer [41] (version 2.0.3) to perform the above-mentioned

60
comparative study. Note that Shin et al. have proposed two 3-
input XOR gates in [36]. In this comparative study, we have 40

included the best one (in terms of common design metrics 20

identified in the previous section).
0
First, we simulate all the XOR gates including the pro- Proposed [1] [4] [5] [6] [13] [14] [30] [32] [37] [41]
posed ones for single-cell omission defects at all the device
cells (excluding the input/output cells and the cells with fixed Fig. 12 Comparison of fault-tolerance of various 2-input XOR gates
against single-cell omission defect
polarization). For the proposed 2-input XOR gates, out of 79
device cells omission of 73 of them produces correct out-
put, thereby achieving 92.41% ( 73 79 × 100%) fault-tolerance. posed XOR gates are able to tolerate double-cell omissions
For the proposed 3-input XOR gates, out of 120 possible to a large extent. Simulation results of similar experiments on
instances of single-cell omissions, correct output is produced the existing XOR designs reveal that they can hardly tolerate
for 112 cases, thereby achieving 93.33% fault-tolerance. The any double-cell omission. This is also apparent from Figs.
summary of comparison is illustrated in Figs. 12 and 13 with 14 and 15.
the help of bar charts. It is apparent that both the proposed We next investigate the effect of additional cell deposi-
XOR designs outperform their existing counterparts. tion defects on the functional behavior of the proposed XOR
We also inspect the effect of double-cell omissions on the gates. The output of the proposed 2-input XOR gate is found
functional behavior of various XOR designs. It is found that to produce correct output for 107 cases out of total 111 pos-
out of total 107 possible instances of double-cell omissions, sible instances of extra-cell depositions, thereby achieving
the proposed 2-input XOR gate produces correct outputs for 96.40% fault-tolerance. Similarly, the output of the proposed
63 cases. For the proposed 3-input XOR gate, correct output 3-input XOR gate is found to produce correct output for
is produced for 100 cases out of total 158 possible instances of 125 cases out of total 131 possible instances of extra-cell
double-cell omissions. Above finding indicates that the pro- depositions, thereby achieving 95.42% fault-tolerance. The

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J Comput Electron (2017) 16:896–906 903

Fault tolerance against single cell omission defect (%)

100 100

Fault tolerance against extra cell

80

deposition defect (%)

80 60

40
60
20

0
40 Proposed [1] [4] [5] [6] [13] [14] [30] [32] [37] [41]

Fig. 16 Comparison of fault-tolerance of various 2-input XOR gates

against extra-cell deposition defect
20

Fault tolerance against extra cell deposition defect (%)

100
0
Proposed [3] [16] [36]
80
Fig. 13 Comparison of fault-tolerance of various 3-input XOR gates
against single-cell omission defect
60
100
Fault tolerance against double cell

80 40
omission defect (%)

60

40 20

20

0
0
Proposed [1] [4] [5] [6] [13] [14] [30] [32] [37] [41] Proposed [3] [16] [36]

Fig. 14 Comparison of fault-tolerance of various 2-input XOR gates Fig. 17 Comparison of fault-tolerance of various 3-input XOR gates
against double-cell omission defect against extra-cell deposition defect
Fault tolerance against double cell omission defect (%)

100
Finally, we explore the effect of cell displacement and
cell misalignment defects on the functional behavior of the
80 proposed XOR gates and all other existing XOR gates.
Displacement or misalignment larger than a critical value
(referred to as permissible displacement) of a cell in a partic-
60 ular direction causes the circuit to malfunction [17]. Larger is
the value of permissible displacement associated with a cell
40
displacement or misalignment defect; the circuit is expected
to have better fault-tolerance against that defect. The per-
centage of defects having permissible displacements more
20 than a certain value could be a measure of fault-tolerance
of the design against such defects. We simulate all the XOR
designs to find out the percentage of such defects having per-
0
Proposed
missible displacements greater than certain values. Tables 4
[3] [16] [36]
and 5 show the percentage of defects having permissible dis-
Fig. 15 Comparison of fault-tolerance of various 3-input XOR gates placements greater than 10 nm (i.e., more than the half of the
against double-cell omission defect width of a QCA cell), 20 nm (i.e., more than the width of a
QCA cell) and 500 nm for various 2-input and 3-input XOR
gates. For better illustration, we have also included bar charts
comparison of fault-tolerance achieved by various XOR gates to present the comparison (Figs. 18, 19, 20 for proposed 2-
(existing and proposed) against extra-cell deposition defects input XOR gate and Fig. 21 for proposed 3-input XOR gate).
is illustrated in Figs. 16 and 17. It is apparent that the proposed XOR gates completely outper-

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904 J Comput Electron (2017) 16:896–906

100
Table 4 Comparison of fault-tolerance of various 2-input XOR gates Percentage of cells with permissible displacements and misalignments greater than 20nm
against cell displacements and misalignments
80
XOR gates % of cells with permissible displacement
60
≥10 nm ≥20 nm ≥500 nm
40
[1] 14.52 1.61 0.0
[4] 43.90 32.93 10.98 20
[5] 3.33 0.0 0.0
0
[6] 13.33 3.33 3.33 Proposed [1] [4] [5] [6] [13] [14] [30] [32] [37] [41]

[13] 47.45 29.66 10.17

Fig. 19 Comparison of various 2-input XOR gates on the basis of
[14] 27.78 8.33 4.16
percentage of cells with permissible displacement greater than 20 nm
[30] 41.67 26.38 5.55
[32] 30.58 13.20 4.13 100
Percentage of cells with permissible displacements and misalignments greater than 500nm
[37] 29.41 9.80 5.88
80
[41] 30.89 20.78 9.55
Proposed 91.67 89.58 88.54 60

40

Table 5 Comparison of fault-tolerance of various 3-input XOR gates

20
against cell displacements and misalignments
XOR gates % of cells with permissible displacement 0
Proposed [1] [4] [5] [6] [13] [14] [30] [32] [37] [41]
≥10 nm ≥20 nm ≥500 nm
Fig. 20 Comparison of various 2-input XOR gates on the basis of
[3] 39.77 22.72 5.11 percentage of cells with permissible displacement greater than 500 nm
[16] 11.0 7.0 1.5
100
[36] 59.35 41.73 12.95 Percentage of cells with permissible displacements and misalignments
Greater tan 10nm Greater than 20nm Greater than 500nm
Proposed 91.93 89.44 34.78 80

60

100 40
Percentage of cells with permissible displacements and misalignments greater than 10nm

80 20

0
60 Proposed [3] [16] [36] Proposed [3] [16] [36] Proposed [3] [16] [36]

40 Fig. 21 Comparison of permissible displacements for various 3-input

XOR gates
20

0
Proposed [1] [4] [5] [6] [13] [14] [30] [32] [37] [41] A consolidated summary of our comparative study on
fault-tolerance of various 2-input and 3-input XOR gates
Fig. 18 Comparison of various 2-input XOR gates on the basis of
percentage of cells with permissible displacement greater than 10 nm (including the proposed XOR gates) against various cell mis-
placement defects is shown in Tables 6 and 7.
As mentioned earlier, one of the most common tools for
form all the existing ones in terms of fault-tolerance against improving the fault-tolerance of a QCA circuit against vari-
cell displacement and cell misalignment defects as well. A ous cell misplacement defects is to use redundant cells which
significant percentage (88.54 and 34.78%, respectively) hav- in turn may lead to increase in area. Both fault-tolerance and
ing permissible displacements more than 500 nm for the cell area act as two important design metrics for practical realiz-
displacement/misalignment defects in the proposed 2-input ability of a QCA circuit. In other words, a practical design
and 3-input XOR gates indicates that the complete removal of must not compromise with any one of these two (beyond an
the corresponding cell from the design area does not have any acceptable limit) for the shake of improving the other. Hence,
effect on the functional behavior of the circuit. In other words, the ratio of fault-tolerance (in %) and area (in µm2 ) may be
the proposed design contains a large number of redundant considered as a figure of merit (FOM) for such designs. A
cells. In fact, the presence of redundant cells plays a major good fault-tolerant design must show high degree of fault-
role in achieving higher degree of fault-tolerance against cell tolerance against all types of cell misplacements without
omission defects. increasing the area overhead too much. Figures 22 and 23

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J Comput Electron (2017) 16:896–906 905

Table 6 Comparison summary

XOR gates % of fault-tolerance against
of fault-tolerance of various
2-input XOR gates against Single-cell Double-cell Extra-cell Cell displacement
various cell misplacement omission omission deposition and misalignment
defects
[1] 0.0 0.0 73.68 14.52
[4] 17.14 0.0 77.0 43.90
[5] 14.28 0.0 47.06 3.33
[6] 12.50 0.0 75.00 13.33
[13] 30.77 0.0 94.89 47.45
[14] 10.34 0.0 85.71 27.78
[30] 11.43 0.0 91.3 41.67
[32] 20.0 3.70 67.54 30.58
[37] 13.04 8.00 73.07 29.41
[41] 26.58 12.86 97.20 30.89
Proposed 92.31 58.90 96.40 91.67

Table 7 Comparison summary

XOR gates Percentage of fault-tolerance against
of fault-tolerance of various
3-input XOR gates against Single-cell Double-cell Extra-cell Cell displacement
various cell misplacement omission omission deposition and misalignment
defects
[3] 25.55 9.18 89.51 39.77
[16] 2.27 0.0 50.0 11.0
[36] 48.41 11.90 95.40 59.35
Proposed 93.33 63.29 95.42 91.93
Fault tolerance against single cell omission/

1200 1000
Fault tolerance against single cell omission/ Area of
Area of various 2−input XOR gates

1000

800
800
various 3−input XOR gates

600
600
400

200
400
0
Proposed [1] [4] [5] [6] [13] [14] [30] [32] [37] [41]

200
Fig. 22 Comparison of various 2-input XOR gates on the basis of FOM
(fault-tolerance/area) for single-cell omission
0
Proposed [3] [16] [36]

illustrate a case of comparison in terms of this figure of merit Fig. 23 Comparison of various 3-input XOR gates on the basis of FOM
for single-cell omission defect for 2-input and 3-input XOR (fault-tolerance/area) for single-cell omission
gates, respectively. It is apparent that the proposed designs
outperform all the existing designs in terms of this newly
defined figure of merit too.
in the construction of several computing subsystems. The
applicability of popular fault-tolerant schemes such as TMR,
NAND multiplexing and majority multiplexing in the context
6 Conclusions of practical realization of QCA XOR gate has been investi-
gated and is observed to perform poorly. In order to bridge the
Design of effective fault-tolerant schemes is desirable for gap, a new fault-tolerant designs of QCA XOR gates have
reliable realization of various digital modules in QCA. XOR been presented. Simulation results show that the proposed
gates are found to be one of the important components used designs achieve significantly high fault-tolerance against var-

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906 J Comput Electron (2017) 16:896–906

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