0% found this document useful (0 votes)
17 views8 pages

Dec50143 PW2

The document describes designing and simulating layouts for CMOS logic gates including a basic inverter, inverter with dual contacts and substrate, and a 4-input NAND gate IC. It provides instructions on using Microwind software to design the layouts and perform timing simulations and area calculations.

Uploaded by

Muhammad Jazli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
17 views8 pages

Dec50143 PW2

The document describes designing and simulating layouts for CMOS logic gates including a basic inverter, inverter with dual contacts and substrate, and a 4-input NAND gate IC. It provides instructions on using Microwind software to design the layouts and perform timing simulations and area calculations.

Uploaded by

Muhammad Jazli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 8

ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: ____________


DEC50143 – CMOS IC DESIGN AND FABRICATION
Layout Design and Simulation of CMOS Inverter (NOT Logic
PRACTICAL WORK 2 :
Gate)
PRACTICAL WORK
DATE :
LECTURER’S NAME:
GROUP NO. :
TOTAL
STUDENT ID & NAME : MARKS
(100%)

(1) jazli

(2)

(3)

(4)

(5)

DATE SUBMIT : DATE RETURN :


1 LEARNING OUTCOMES (LO):

1. : Design the basic logic gates, digital circuits from Boolean function and integrated
circuit layout based on the knowledge of integrated circuit design methodology.

2. : Construct the layout design of CMOS circuits using layout design software based on
specific CMOS layout design rules.

3. : Demonstrate elements of environmental sustainability in implementing reduce and


reuse techniques in design parameters and design consideration through practical
work.
2 OBJECTIVES:

At the end of this practical work session, the student should be able to:
1. design the layout of :
a) Horizontal inverter layout
b) Inverter with dual contact and substrate
c) IC 4069 (IC for CMOS inverter/ NOT gate)
2. calculate the layout size/area.

3 THEORY:

The symbol and the truth table of an inverter or NOT gate:

The schematic diagram of a CMOS inverter:

PMOS is placed close to VDD to pull-up the output. NMOS is placed close to ground to pull down the
output. Both Gate terminals of PMOS and NMOS are tied together to be the input. The Drain
terminals of PMOS and NMOS are connected to become the output.

When Vin is high and equal to VDD, the NMOS transistor is ON, while the PMOS is OFF. A direct path
exists between Vout and the ground node, resulting in a steady-state value of 0V.
When the input voltage is low (0V), NMOS transistor is OFF, while PMOS transistor is in ON. A direct
path exists between VDD and Vout, resulting in a steady-state value of VDD.
4 EQUIPMENT / TOOLS:

1. PC Set
2. Microwind 2.6a software.

5 PROCEDURE:

Part 1 : Designing and simulating horizontal CMOS inverter layout.

 Open the Microwind Editor window.


 Select the Foundry file from File menu. Select “cmos012.rul” file.
 Draw the CMOS inverter layout as shown in Figure 2.1.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2
 Make sure to obey the design rules.
 Run DRC by selecting:
>Analysis>Design Rule Checker
 Save your layout.

Figure 2.1: Layout of horizontal CMOS inverter layout

 Apply a clock to the input. Click on the Clock icon, and then click on the metal at the gate.
The Clock menu appears, change the name into « input ».

 Set the value of the input pulse as the following:


Time low (tl) = 0.2 ns
Time high (th) = 0.2 ns
Rise time (tr) = Fall time (tf) = 0.001 ns

 Click OK.

 To watch the output, click on the Visible icon and then, click on the metal that connects the
Drain. Change the name into « output». Click OK. The Visible property is then sent to the
node.
 Simulate the inverter layout by selecting:
>Simulate> Run Simulation>Voltage vs Time (default) on the main menu.
The timing diagram of the inverter appear, as shown in Figure 2.2.

 Measure the optimized area of the layout. The unit is lambda 2 (2).

Figure 2.2: Timing diagram of vertical CMOS inverter layout

Theory:

The optimized area of the layout is determined by the following:


Area = Layout Width x Layout Length = 31.5 x 63 = 1984.5 2

Part 2 : Designing and simulating CMOS inverter layout with dual contact and substrate.

 Open the Microwind Editor window.


 Select the Foundry file from File menu. Select “cmos012.rul” file.
 Draw the CMOS inverter layout as shown in Figure 2.3.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2
Figure 2.3: Layout of vertical CMOS inverter layout with dual contact and substrate.

 Make sure to adhere the design rules.

 Run DRC by selecting:


>Analysis>Design Rule Checker

 Save your layout.

 Simulate the inverter layout and get the:


a) timing diagram of the inverter
b) layout area

Part 3 : Designing the layout of IC 4069 (CMOS inverter ).

 Design the layout of IC 4069 based on the CMOS IC logic gates shown in Figure 2.4.

Figure 2.4 : Internal Structure of IC 4069

 Do the DRC to ensure that your design conforms to all design rules.
 Measure the optimized area of the layout (the unit is λ 2).

6 RESULT
In your report, include the following:

1. Part 1: Horizontal CMOS Inverter


a) inverter layout.
b) Input / output timing diagram
c) layout area = _________ x _________
= ____________2
(4 marks)
2. Part 2: CMOS Inverter with dual contacts and substrate
a) inverter layout.
b) input / output timing diagram.
c) layout area = _________ x _________
= ____________2
(4 marks)
3. Part 3: IC 4069 (CMOS inverter gate IC) and its layout size.
a) IC layout
b) The optimized area of the IC layout = _________ x _________
= ____________2
(4 marks)

7 DISCUSSION

1. Explain the operation of NMOS and PMOS transistors in CMOS inverter by using a suitable
diagram.
(4 marks)

2. Make a comparison between the optimized area of the layouts in Part 1 and Part 2 and explain
your findings.
(3 marks)

3. Explain the difference between an inverter from the TTL 7400 families and from the CMOS 4000
families.
(3 marks)

8 CONCLUSION

Give TWO (2) conclusions for this practical work. (4 marks)


Part 3

You might also like