Real-Time Laboratory (FPGA)

(4th Class)

Computer and Information Engineering Department

College of Electronics Engineering
Ninevah University

2022-2023

Copyright © EECIE Department 2020. All rights reserved.

 Lab #1: Structural Modeling of Digital Systems using
Module Instantiation

OBJECTIVE
Building and developing new skills through designing and implementing logic circuits
that can be used to drive and control the functionality of different applications using
VHDL code. Thus, in this lab, you will be learning how to model and implement digital
systems using the component instantiation structure to create a neat hierarchical design.
The Xilinx Nexys4 FPGA board is used to help students understanding the basics of the
FPGAs and how they can physically implement and configure their projects (VHDL
code) on an FPGA platform.

INTRODUCTION

In digital systems, several modules or subsystems are composed to construct and perform
together the required tasks. This allows to build a large system from simpler or
predesigned components. A structural way of modeling describes a circuit in terms of
components and its interconnection. Each component is supposed to be defined earlier
(e.g., in package) and can be described as structural, a behavioral or dataflow model. At
the lowest hierarchy, each component is described as a behavioral model, using the basic
logic operators defined in VHDL. In general, structural modeling is an excellent concept
to describe complex digital systems, though a set of components in a hierarchical fashion.
In HDL, a COMPONENT, or a module, is simply a piece of conventional code (that is,
LIBRARY declarations + ENTITY + ARCHITECTURE). However, by declaring such
code as being a COMPONENT, it can then be used within another circuit, similar to
calling a function in software languages, but here it is used to employed pre-designed
hardware circuit or module to construct a larger system or subsystem.

A COMPONENT is also another way of partitioning a code and providing code sharing
and code reuse. For example, commonly used circuits, like flip-flops, multiplexers,
adders, basic gates, etc., can be placed in a LIBRARY, so any project can make use of
them without having to explicitly rewrite such codes. To use a COMPONENT, it must
first be declared. The corresponding syntaxes for calling/using a component are shown
below.

1
COMPONENT declaration:

COMPONENT component_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
...);
END COMPONENT;

COMPONENT instantiation:

label: component_name PORT MAP (port_list);

As can be seen, the syntax of the declaration is similar to that of an ENTITY; that is, the
names of the ports must be specified, along with their modes (IN, OUT, BUFFER, or
INOUT) and data types (STD_LOGIC_VECTOR, INTEGER, BOOLEAN, etc.). To
instantiate a component, a label is required, followed by the component’s name and a
PORT MAP declaration. Finally, port_list is just a list relating the ports of the actual
circuit to the ports of the pre-designed component which is being instantiated.

Example: Using component instantiation for a neat hierarchical design

To construct the circuit shown in Figure 1 below, we use the component design structure
to build the logic design.

Figure 1: Netlist (gate-level) of the logic circuit.

2
1 ---- logic circuit -----------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ----------------------------------
5 Entity comb_function IS
6 PORT (A, B, C: IN STD_LOGIC;
7 Z: OUT STD_LOGIC);
8 END comb_function;
9 ----------------------------------
10 ARCHITECTURE netlist OF comb_function IS
11------------And----------
12 Component And_2 is
13 Port( x,y : in STD_LOGIC;
14 Z : out STD_LOGIC);
15 End component;
16---------------------------
17-------Or-----------------
18 Component Or_2 is
19 Port( x,y : in STD_LOGIC;
20 Z : out STD_LOGIC);
21 End component;
22---------------------------
23---------Not--------------
24 Component Not_1 is
25 Port( x : in STD_LOGIC;
26 Z : out STD_LOGIC);
27 End component;
28---------------------------
29--------define need signals------
30 Signal p, q, r : STD_LOGIC;
31 Begin
32 G1: Not_1 port map (a, p);
33 G2: And_2 port map (p, b, q);
34 G3: And_2 port map (a, c, r);
35 G4: Or_2 port map (q, r, z);
36 End architecture netlist;

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Procedure
Part I: The purpose of this part is hardware implementation of multiplexer (4:1) circuit
by using multiplexer (2:1) as shown in Figure 2 below.

s1
s0
s1 s0
w0 0
w1 1
w0
0
multiplexed_out w1 out
1 MUX (4:1)
w2
w2 0 w3

w3 1

Figure 2: Schematic diagram of a 4-to-1 Multiplexer circuit.

1) Use component instantiation structure, write a synthesizable VHDL code to build

the circuit shown in Figure 2.

2) Check syntax errors, if exist, then synthesize your design to construct the structural
netlist (gate-level) circuit.

3) Generate the UCF file that is essential to identify the required Input/Output
pins/ports on the Xilinx Nexys4 FPGA board so that you can test the functionality
of your design.

4) Implement your design (Translate, Map, Place, and Route), then generate the
programming bitstream file.

5) Download the bit-file of the compiled circuit on the FPGA chip, test the
functionality of the circuit by toggling the switches and observing the LED.

4
Part II: The purpose of this part is hardware implementation of a comparator logic
circuit that compares two temperature values of thermostat sensors. It performs
comparison between (a & b) and provides three output indicators as follows:

• X1 à ON when a > b,
• X2 à ON when a = b, and
• X3 à ON when a < b

a>b
a=b
a<b

Figure 3: Top-level diagram of a 2-input comparator logic circuit.

Write a complete VHDL code to construct the comparator circuit, consider a and b each
is 4-bit unsigned number.

1) Check syntax errors, if exist, then synthesis your design to construct the circuit.

2) Generate the UCF file that is essential to identify the required Input/Output
pins/ports on the Xilinx Nexys4 FPGA board so that you can test the functionality
of your design.

3) Implement your design (Translate, Map, Place, and Route), then generate the
programming bitstream file.

4) Download the bit-file of the compiled circuit on the FPGA chip, test the
functionality of the circuit by toggling the switches and observing the LEDs.

5
Report and Discussion
Q1. Consider the carry ripple adder circuit shown in Figure P1. Design a FAU (full
adder unit), to be used as a COMPONENT. Then write a code for the complete
carry ripple adder, shown below, using component instantiation of FAU. Compile
your project and synthesize the circuit, then based on the summary of the ISE
software report the usage of number of hardware utilized resources from the FPGA
chip.

Figure P1: 4-bit carry ripple adder and truth table of Full Adder unit (FAU).

Q2. Figure P2 illustrates the construction of a hierarchical design. Two subcircuits (that
is, ‘‘components’’), called counter and register, are used to construct a higher level
circuit, called stop_watch. The system consists of a free-running counter, which is
reset every time the stop input is asserted. The status of the counter must be stored
in the sub-circuit register just before reset occurs. Once stop returns to ‘0’, the
counter resumes counting (from zero), while the register holds the previous count.
Design the two components of Figure P2, then instantiate them in the main code to
produce the complete stop_watch circuit.

Figure P2: Diagram of the stop_watch circuit.

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Q3. Write the required VHDL code to implement a progressive 2-digit decimal counter
(0 à 99 à 0), with external asynchronous reset plus binary-coded decimal (BCD)
to seven-segment display (SSD) conversion. Diagrams of the circuit and SSD are
shown in Figure P3. The CASE statement should be employed to determine the
output signals that will feed the SSDs.

dp

“gfedcba dp”

Figure P3: Top-level diagram of 2-digit decimal counter.

Note: the connection between the circuit and the SSD: gfedcba db (that is, the MSB
feeds the segment g, while the LSB feeds decimal point). All LEDs are active
low. For example, to display the number 1 on the 7-seqment display, you
should drive it with “1111001” and dp =’1’.