AU6395
AU6395
AU6395
AU6395
USB2.0 to SATA Bridge Controller
Copyright
Copyright 1997 - 2007. Alcor Micro, Corp. All Rights Reserved. No part of this data sheet may be reproduced, transmitted, transcribed, stored in a retrieval system or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without prior written permission from Alcor Micro, Corp.
Trademark Acknowledgements
The company and product names mentioned in this document may be the trademarks or registered trademarks of their manufacturers.
Disclaimer
Alcor Micro, Corp. reserves the right to change this product without prior notice. Alcor Micro, Corp. makes no warranty for the use of its products and bears no responsibility for any error that appears in this document. Specifications are subject to change without prior notice.
Revision History
Date
Dec 2007
Revision
1.00W
Description
Official Release
Contact Information:
Taiwan Alcor Micro, Corp. 4F, No 200 Kang Chien Rd., Nei Hu, Taipei, Taiwan, R.O.C. Phone: 886-2-8751-1984 Fax: 886-2-2659-7723 Santa Clara Office 2901 Tasman Drive, Suite 206 Santa Clara, CA 95054 USA Phone: (408) 845-9300 Fax: (408) 845-9086
<Memo>
Table of Contents
1. Introduction ............................................................ 3
1.1 Description...................................................................................3 1.2 Features........................................................................................3
2. Application Block Diagram ................................... 4 3. Pin Assignment ...................................................... 5 4. System Architecture and Reference Design ....... 11
4.1 AU6395 Block Diagram ...............................................................11
List of Figures
Figure 2.1 Block Diagram..................................................................4 Figure 3.1 AU6395-MBLPin Assignment Diagram ..........................5 Figure 3.2 AU6395-MCL Pin Assignment Diagram .........................8 Figure 4.1 AU6395 Block Diagram ...................................................11 Figure 6.1 64 LQFP Mechanical Information Diagram ....................16 Figure 6.2 48 LQFP Mechanical Information Diagram ....................17
List of Tables
Table 3.1 AU6395-MBL Pin Descriptions .........................................6 Table 3.2 AU6395-MCL Pin Descriptions .........................................9 Table 5.1 Absolute Maximum Ratings .............................................12 Table 5.2 Recommended Operating Conditions .............................12 Table 5.3 General DC Characteristics ..............................................12 Table 5.4 DC Electrical Characteristics of 3.3V I/O Cells ...............13 Table 5.5 Electrical characteristics ..................................................13 Table 5.6 Static characteristicDigital pin .....................................14 Table 5.7 Static characteristicAnalog I/O pinsDP/DM..........14 Table 5.8 Dynamic characteristicAnalog I/O pinsDP/DM.....15
ii
1. Introduction
1.1 Description
The AU6395 is a single chip controller designed for bridging USB 2.0 to SATA bus interface. It is used as the primary controller of building an external USB 2.0 hard disk or CD/DVD drives. To maximize the data throughput and achieve the best compatibility, AU6395 is equipped with Alcors proprietary automatic speed negotiation (ASN) algorithm. The ASN algorithm allows AU6395 to select optimized operating mode that device can best support a reliable data transfer. The silicon would work with the default device driver from Windows ME, Windows 2000, Windows XP and Mac OS X, however, vendor device driver provided by Alcor Micro would enable the built device working under Windows 98, Windows 2000 (SP1/SP2) and Mac OS 9.
1.2 Features
Supports USB 2.0 specification and USB Device Class Definition for Mass Storage, Bulk-Transport V1.0. Support SATA 1.5G/3.0G Speed Negotiation Support SATAII Asynchronous Signal Recovery (Hot Plug) feature. Support 480Mbps High Speed (HS) and 12Mbps Full Speed USB operation. Supports SATA specification Revision 2.5. Support ATA/ATAPI LBA48 bit addressing mode. Hardware DMA engine integrated inside for performance enhancement Works with default device driver from ME/2000/XP and Mac OS. Built in 3.3V to 1.8V Voltage Regulator. One spared LED pin for disk access indication 64-pin LQFP package 48-pin LQFP package
HD
AU6395
CD-ROM, CD-R/W DVD-ROM, VCD-R/W
3. Pin Assignment
There are two different form factor packages available to choose from. The following figure shows signal names for each pin and the table in the page after describes each pin in details.
SGNDA
SGNDA
SGNDA
64 NC GNDIO VDDIO GNDC VDDC GPI0 GPI5 GPO7 GPO6 EEPCLK EEPDAT GPO5 GPI2 GPI3 GPI6 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
63
62
61
60
59
58
57
56
55
54
53
52
51
50
SGNDA 49 48 47 46 45 44 VCO25 RESET_N GNDIO VDDIO GNDC VDDC GPI1 GPO0 GPO1 GPO2 GPO3 GPO4 SSCL SSDA GNDPLL VDDPLL 43 42 41 40 39 38 37 36 35 34 33 32 V33OUT
SVD33
SVDD
SVDD
SVDD
SVDD
SXO 30 NC
RXN
TXN
RXP
TXP
18
19
20
21
22
23
24
25
26
27
28
29
SXI 31 V5IN
NC NC
VDDU
VSSU
UXO
UXI
VS33P
DM
DP
VD33P
REXT
V18OUT
NC
GNDA
Pin Name
NC GNDIO VDDIO GNDC VDDC GPI0 GPI5 GPO7 GPO6 EEPCLK EEPDAT GPO5 GPI2 GPI3 GPI6 NC NC VDDU VSSU UXO UXI VS33P DM DP VD33P REXT V18OUT NC GNDA NC V5IN V33OUT VDDPLL GNDPLL SSDA
I/O
PWR PWR PWR PWR I I O O O I/O O I I I I/O gnd I/O vdd Core logic gnd Core logic vdd
Description
General purpose input 0 General purpose input 5 General purpose output 7 General purpose output 6 EEPROM I2C clock EEPROM I2C data General purpose output 5 General purpose input 2 General purpose input 3 General purpose input 6
PWR PWR O I PWR I/O I/O PWR I PWR PWR PWR PWR PWR PWR I/O
USB vdd USB gnd USB crystal output USB crystal input USB gnd USB DUSB D+ USB vdd USB external resistor Regulator 1.8V output Regulator gnd Regulator 5V input Regulator 3.3V output PLL vdd PLL gnd SATA I2C data
AU6395 USB2.0 to SATA Bridge Controller V1.00W
Pin #
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Pin Name
SSCL GPO4 GPO3 GPO2 GPO1 GPO0 GPI1 VDDC GNDC VDDIO GNDIO RESET_N VCO25 SGNDA SXI SXO SVDD33 SVDD SGNDA SVDD RXP RXN SGNDA SVDD TXN TXP SVDD SGNDA NC
I/O
I O O O O O I PWR PWR PWR PWR I O PWR I O PWR PWR PWR PWR I I PWR PWR O O PWR PWR SATA crystal input SATA I2C clock
Description
General purpose output 4 General purpose output 3 General purpose output 2 General purpose output 1 General purpose output 0 General purpose input 1 Core logic vdd Core logic gnd I/O vdd I/O gnd Chip reset_n PLL 25 MHz output
SATA crystal output SATA vdd SATA vdd SATA gnd SATA vdd SATA rx+ SATA rxSATA gnd SATA vdd SATA txSATA tx+ SATA vdd SATA gnd
The following figure shows signal names of each pin of the 48 LQFP package and the table in the page after describes each pin in details.
48 SGNDA 1 2
SVDD
SVDD
SVDD
SVDD
SXO
RXN
TXN 46
RXP
47
TXP
45
44
43
42
41
40
39
38
GNDIO VDDIO GNDC VDDC GPI0 GPI5 GPO7 GPO6 EEPCLK EEPDAT
3 4 5 6
34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
7 8 9
10 11 12
GPI2
VDDU
VSSU
UXO
VS33P
DM
DP
VD33P
REXT
V18OUT
GNDA
V5IN
UXI
Pin Name
SGNDA GNDIO VDDIO GNDC VDDC GPI0 GPI5 GPO7 GPO6 EEPCLK EEPDAT GPI2 VDDU VSSU UXO UXI VS33P DM DP VD33P REXT V18OUT GNDA V5IN V33OUT VDDPLL GNDPLL GPI1 VDDC GNDC VDDIO GNDIO
I/O
PWR PWR PWR PWR PWR I I O O O I/O I PWR PWR O I PWR I/O I/O PWR I PWR PWR PWR PWR PWR PWR I PWR PWR PWR PWR SATA gnd I/O gnd I/O vdd Core logic gnd Core logic vdd
Description
General purpose input 0 General purpose input 5 General purpose output 7 General purpose output 6 EEPROM I2C clock EEPROM I2C data General purpose input 2 USB vdd USB gnd USB crystal output USB crystal input USB gnd USB DUSB D+ USB vdd USB external resistor Regulator 1.8V output Regulator gnd Regulator 5V input Regulator 3.3V output PLL vdd PLL gnd General purpose input 1 Core logic vdd Core logic gnd I/O vdd I/O gnd
9
Pin #
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin Name
RESET_N VCO25 SGNDA SXI SXO SVDD33 SVDD SGNDA SVDD RXP RXN SGNDA SVDD TXN TXP SVDD
I/O
I O PWR I O PWR PWR PWR PWR I I PWR PWR O O PWR SATA crystal input chip reset_n PLL 25 MHz output
Description
SATA crystal output SATA vdd SATA vdd SATA gnd SATA vdd SATA rx+ SATA rxSATA gnd SATA vdd SATA txSATA tx+ SATA vdd
10
XCVR
USB SIE
RAM
SATA Engine
SATA
ROM
Arbitrator
1.8 V 3.3 V
PLL
5V
12MHz XTAL
11
5. Electrical Characteristics
5.1 Absolute Maximum Ratings
SYMBOL
V5IN VDDH VIN TSTG
UNITS
V V V
O
PARAMETER
Power Supply Power Supply Digital Supply Input Signal Voltage Operating Temperature
MIN
4.75 3.0 1.62 0 0
TYP
5.0 3.3 1.8 3.3
MAX
5.25 3.6 1.98 3.6 70
UNITS
V V V V
O
PARAMETER
Input current Tri-state leakage current Input capacitance Output capacitance Bi-directional buffer capacitance
CONDITIONS
No pull-up or pull-down
MIN
-10 -10
TYP
1 1 2.8 2.8 2.8
MAX
10 10
UNITS
A A F F F
12
PARAMETER
Power supply Input low voltage
CONDITIONS
3.3V I/O
Limits
MIN
3.0
TYP
3.3
MAX
3.6 0.8
UNIT
V V V
LVTTL Input high voltage Output low voltage Output high voltage Input pull-up resistance Iol=2~16mA Ioh=2~16mA PU=high, PD=low 2.4 55 40 -10 -10 75 75 1 1 110 150 10 10 2.0 0.4
V V K K A A
Input pull-down resistance PU=low, PD=high Input leakage current Tri-state output leakage current Vin= VDDHM or 0
Parameter
Analog supply Voltage Digital supply Voltage Operating supply current
Conditions
Min.
3.0 1.62
Typ.
3.3 1.8
Max. Unit
3.6 1.98 55 V V mA
V18 ICC
13
Min.
Typ.
Max.
Unit
Table 5.7 Static characteristicAnalog I/O pinsDP/DM Symbol Parameter Conditions Min. Typ. Max. Unit
USB2.0 TransceiverHS Input Levelsdifferential receiver VIDP-VIDM High speed differential measured at the 300 input sensitivity connection as application circuit High speed data signaling common mode voltage -50 range High speed squelch detection threshold High speed disconnection detection threshold Squelch detected No squelch detected Disconnection detected Disconnection not detected Output Levels 150 625 525
VHSDIFF
mV
VHSCM
500 100
mV mV mV mV mV
VHSSQ
VHSDSC
High speed idle level output voltage(differential) High speed low level output voltage(differential) High speed high level output voltage(differential) Chirp-J output voltage differential Chirp-K output voltage differential Resistance Equivalent resistance Driver output impedance used as internal chip only
mV mV mV mV mV
RDRV
14
40.5
45
49.5
VDI VCM
Termination voltage for pull-up resistor on pin 3.0 RPU USB1.1 TransceiverFS Input Levelsdifferential receiver Differential input VIDP-VIDM 0.2 sensitivity Differential common 0.8 mode voltage Input Levelssingle-ended receivers Single ended receiver 0.8 threshold Output levels Low-level output voltage High-level output voltage 0 2.8
3.6
V 2.5 V
V V V
Min.
Typ.
Max. Unit
VCRS
1.3
2.0
15
6. Mechanical Information
Figure 6.1 64 LQFP Mechanical Information Diagram
16
0.25
A1
C1 b e
A2
SYMBOLS A A1 A2 c1 D D1 E E1 e b L L1
MIN. MAX. -1.6 0.05 0.15 1.35 1.45 0.09 0.16 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.5 BSC 0.17 0.27 0.45 0.75 1 REF
1. 2.
JEDEC OUTLINE: MS-026 BBC DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS IMCLUDING MOLD MISMATCH. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm
17
7. Abbreviations
In this chapter some of the terms and abbreviations used throughout the technical reference manual are listed as follows. SIE SATA UTMI Serial Interface Engine Serial Advanced Technology Attachment USB Transceiver Macrocell Interface
18