6/8/2018

ECE4740:
Digital VLSI Design
Lecture 18: Latches and flipflops

646

Simple static storage cells

Latches

647

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Recap: regenerative property

Vi1 Vo1 Vi2 Vo2

• If the |gain| in the

even number of transient region is
cascaded inverters larger than 1, only
A A and B are stable
operation points
C

• (C is a metastable
B
operation point)
Vi1 = Vo2
648

Bistable circuits
• Cross-coupling of Vi1
two inverters results
in bistable circuit Vi2
(=two stable states)

• We want to change stored value

– Apply a trigger pulse at Vi1 or Vi2
– Width of trigger pulse must be larger than the
total propagation delay (2x inverter delay)
649

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Bistable circuits (cont’d)

• Cross-coupling of Vi1
two inverters results
in bistable circuit Vi2
(=two stable states)

• Mainly two approaches:

– Cutting feedback loop  MUX based latch
– Overpowering feedback loop  used in SRAMs

650

Positive & negative latches

in D Q out in D Q out

clk CLK clk CLK

clk clk

In In

Out Out

Out Out Out Out

stable follows In stable follows In

• Positive latch: • Negative latch:

transparent high transparent low
651
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic

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MUX–based latches
• Change stored value by cutting feedback
feedback feedback

0 1
Q Q
D 1 D 0

CLK CLK

positive latch negative latch

Q = !CLK*Q + CLK*D Q = CLK*Q + !CLK*D

transparent when CLK is high transparent when CLK is low
652

MUX latch with transmission gates

circuit is not
CLK
ratio’ed

!CLK

input sampled
D (transparent mode)

CLK
CLK
D Q !CLK

CLK feedback (hold mode)

653

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How to reduce the “clock load”

• Clock needs to drive 4 transistors (CL=4)
• Solution: pass transistors

CLK !Q • Reduced
noise margin
D Q
• Higher
leakage
currents:
threshold
drop!
!CLK  WHY?
654

Latch race problem

B
B B

clk

CLK which value of B is stored?

• Two-sided clock constraint:

– T
tpd,latch+tpd,logic+tsu,latch can be hard or
impossible to meet
– Thigh < tcd,latch+tcd,logic both constraints
655

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One solution: latch-based design

requires
inverted
CLK clock

N latch

P latch
Logic B

Logic A

• What if we (re)move Logic B?

656

Often a better solution!

CLK
N latch

P latch

Logic A

• This is a single-edge triggered flip-flop

657

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Edge-triggered bistables

Flip-flops

658

Master-slave edge-triggered flip-flop

D Q

0
1 Q CLK
1
QM
D 0
CLK CLK
CLK
Slave
Master D

CLK = 0 transparent hold QM

CLK = 01 hold transparent Q

659
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic

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MS ET FF implementation
master slave

T2 I5 T4 I6 Q
I2 I3
QM

T1 I4 T3
D I1

0
CLK
1

CLK=0  master transparent; slave hold

660

MS ET FF implementation (cont’d)
master slave

T2 I5 T4 I6 Q
I2 I3
QM

T1 I4 T3
D I1

1
CLK
0

clock load is 8!
CLK=1  master hold; slave transparent
661

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Timing properties of MS ET FF

• Assume propagation delays tpd,inv & tpd,tg

• Assume contamination delays = 0
• Assume inverter delay for !CLK = 0
662

Setup time

• Time before rising edge of CLK that D

must be valid

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Propagation delay

delay already
included in tsetup

• Time for QM to reach Q (output)

664

Hold time can be negative

• Time D must be stable after rising edge of

CLK signal If assuming that CLK
inverter has tpd=0

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How to simulate setup time

3.0 3.0
Q
2.5 2.5

2.0 QM 2.0 I 2 2 T2
1.5 1.5 Q
Volts

Volts
CLK CLK
D D
1.0 1.0
I 2 2 T2 QM
0.5 0.5

0.0 0.0

2 0.5 2 0.5
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
time (nsec) time (nsec)

• Shift input D closer to rising CLK signal

until Q output is incorrect
666
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic

How to simulate setup time (cont’d)

CLK

tsetup
D ✓

Q ?
tpd,ff tpd,ff

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How to simulate setup time (cont’d)

CLK

tsetup output can be

anything
D ✗

Q ? ?
tpd,ff tpd,ff

668

Propagation delay simulation

3 measured at 50%
level of CLK and
2.5 50% Q output

1.5
Volts

1 tpd,ff,LH tpd,ff,HL
0.5

-0.5
same procedure:0 0.5 1 1.5 2 2.5
shift input D until Time (ns)
circuit fails
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How to reduce the clock load?

• Clock load per flip-flop important: directly
affects power dissipation of clock network
• Can reduce clock load at cost of robustness
CLK !CLK
I1 I3

D T1 QM T2 Q

I2 I4
!CLK CLK

Clock load of 4! ratio’ed circuit!

670

Sizing of reduced clock-load MS FF

CLK !CLK
I1 I3

D T1 QM T2 Q

I2 I4
!CLK CLK
reverse conduction

• To switch state of master, T1 must be sized to

overpower I2 (source driver must be strong too)
• To avoid reverse conduction, I4 must be weaker
than I1  how can we build a weak inverter?

671

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For latches and flip-flops

More clock-skew issues

672

Non-ideal clocks: clock skew

CLK CLK

!CLK !CLK

ideal clocks Non-ideal clocks

clock skew

clock skew can happen due to

1-1 overlap
uneven wire lengths, capacitances,
different fan-outs, etc. 0-0 overlap

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Issue 1: race condition

CLK !CLK Q
on on
P1 P3 I3 I4 !Q
D I1 I2

P2 P4

!CLK CLK

• Direct path from D to Q during short time

when both CLK and !CLK are high (1-1
overlap)
674

Issue 2: undefined state

X=? !CLK Q
CLK
on
P1 A P3 I3 I4 !Q
D I1 I2

B P4
P2
on
!CLK CLK

• Both B and D are driving A when CLK and

!CLK are both high (1-1 overlap)

675

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Issue 3: dynamic storage

X !CLK Q
CLK
off off
P1 P3 I3 I4 !Q
D I1 I2

P2 P4
off
!CLK CLK

• When CLK and !CLK are both low (0-0

overlap) level of X stored on parasitic
capacitances (might discharge)
676

Pseudo-static two-phase ET FF
CLK1 CLK2 Q

P1 P3 I3 I4 !Q
D I1 I2

P2 P4

CLK2 CLK1
dynamic
master transparent storage
slave hold

clk1 master hold

tnon_overlap
slave transparent
clk2
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Generating a non-1-1-overlapping clock

• To completely avoid overlapping clocks 1-1

(the 0-0 case is not that critical) we need
– tools for accurate timing analysis OR
– non-overlapping clock signals

CLK
tnon_overlap
CLK1

CLK2

678

Useful for generating non-overlapping clocks

Set-reset (SR) latch

679

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SR latch basics
input high sets
opposite output high S R Q !Q
S 0 0 Q !Q memory
!Q
1 0 1 0 set

0 1 0 1 reset
Q
R 1 1 0 0 not allowed

• Similar to cross-coupled inverter pair

• Input S and R can force outputs Q and !Q
in desired state
680

SR latch basics (cont’d)

S R Q !Q
0
S 0 0 Q !Q memory
!Q
1
1 0 1 0 set

0 0 1 0 1 reset
Q
R 1 1 0 0 not allowed
0

A B !(A+B)

• Assume Q=0 and !Q=1 0 0 1

0 1 0
• Assume S=0 and R=0 1 0 0
1 1 0
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SR latch basics (cont’d)

S R Q !Q
1
S 0 0 Q !Q memory
!Q
0
1 0 1 0 set

1 0 1 0 1 reset
Q
R 1 1 0 0 not allowed
0

A B !(A+B)

• Set S=1 and keep R=0 0 0 1

0 1 0
• Then Q=1 and !Q=0 1 0 0
1 1 0
682

SR latch basics (cont’d)

S R Q !Q
0
S 0 0 Q !Q memory
!Q
1
1 0 1 0 set

0 0 1 0 1 reset
Q
R 1 1 0 0 not allowed
1

A B !(A+B)

• Set R=1 and keep S=0 0 0 1

0 1 0
• Then Q=0 and !Q=1 1 0 0
1 1 0
683

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Two-phase non-overlapping clock generator

A NOR1 CLK1

CLK
B NOR2 CLK2

CLK

A
B NOR1

CLK1
NOR2
CLK2

684

Two-phase non-overlapping clock generator

A NOR1 CLK1

CLK
B NOR2 CLK2

CLK

B
CLK1 NOR2

NOR1
CLK2

685

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Another storage cell: Clocked D latch

D
!Q

D Q
Q

CLK transparent mode CLK

CLK

hold mode 686

Ratio’ed clocked SR latch

VDD

off on
M2 M4
Q 1
0 !Q

CLK M6 M8 CLK
on
M1 M3
off
M7 R 1
0 S M5
off on

GND

• Can be used in static RAMs (SRAMs)

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Ratio’ed clocked SR latch (cont’d)

VDD

off on on off

M2 M4
Q 1 0
0 1 !Q

01 CLK M6 M8 CLK 01

on off
M1 M3
offon
0 S M5 M7 R 1
off on

GND

• Ratio’ed  M7 and M8 must succeed in

bringing Q low (overcoming M4)
688

6T CMOS SR Latch
issues with noise
margins and static
CLK CLK power consumption due
to threshold drop across
R PTs
S

CLK
CLK M2 M4
Q M6 S
we will see this M5 !Q
structure again when R
talking about SRAMs
M1 M3

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