6/8/2018

ECE4740:
Digital VLSI Design
Lecture 6: Inverter sizing

193

Very important concepts

Brief timing recap

194

1
 6/8/2018

Rise/fall times & propagation delay

propagation delay
Vin
tp = (tpHL+tpLH)/2
input 50%
waveform

t
tpHL tpLH
Vout
90% 90%

output
waveform 50%

10%
t
tf tr

195

Contamination delay
Vin contamination delay
tcd = 0.5(tcdHL+tcdLH)
input 50%
waveform

t
tcdHL tcdLH
Vout

output tcdHL and tcdLH

waveform 50% can differ

196

2
 6/8/2018

First-order analysis: extract Req

• Approximations required as CL(v) and i(v)
are non-linear and voltage v dependent

197

Use RC circuit to model tpHL

• Decay time from 100% to 50% is

• Same can be obtained for low-to-high time

• Propagation delay:

198

3
 6/8/2018

Increase both Wn and Wp!

Inverter sizing

199

Split load capacitance CL

intrinsic output
extrinsic
capacitances from
capacitances:
self-loading etc.
fan-out and wiring
(diffusion, Miller)

• Just rewrite as:

“unloaded” propagation delay effect on propagation delay caused

by extrinsic capacitances
assume that NMOS and PMOS are sized
200
such that rise and fall times are equivalent

4
 6/8/2018

Impact of sizing factor S

• Intrinsic capacitances:
• Gate resistance: capacitance of a
unit-sized device
resistance of a
unit-sized device

• Leads to:

201

An equivalent view
VDD VDD
Req=Rref/S
high
Vin Vout Vout

Cext Cint= Cref*S Cext

low

VSS VSS

• Propagation delay:
• Simplifying:

202

5
 6/8/2018

What exactly is “S”?

• The sizing factor is how much larger you
make the widths of NMOS and PMOS
– You usually keep the PMOS:NMOS ratio fixed
– Gate lengths L usually kept at the minimum

VDD

Vout
Wp S=2 corresponds to
Vin
2Wp and 2Wn
Wn
VSS
203

Impact of sizing S (cont’d)

intrinsic delay
of inverter: tp0

• Intrinsic delay of gate independent of S

– no load means no effect on propagation delay
• Making S large, eliminates effect of load
– at the cost of inverter area!
– and it will affect the load of the preceding logic! 204

6
 6/8/2018

Example: Sizing impact* on tp

3.8
x 10-11
3.6
3.4
3.2
3
2.8 self loading
2.6 (intrinsic capacitance
dominates)  not
2.4 much gain anymore
2.2
2
1 3 5 7 9 11 13 15
S
large improvement
already achieved for S=5 Image taken from:
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter5.pdf

*for a fixed load! 205

A more relevant case

Sizing a chain of inverters

206

7
 6/8/2018

Sizing a chain of inverters

• For isolated inverter: Increasing S reduces

delay but also increases input capacitance
– not very useful in practice!

• More relevant case: chain of inverters:

207

It’s a trade-off
• Sizing up an inverter reduces delay, but will
also increase its input capacitance!
• Intrinsic capacitance Cint proportional to
gate capacitance:

• is technology dependent (and about 1)

208

8
 6/8/2018

The effective fan-out f

• Delay of an inverter: a function of the ratio
between external load and its input cap!

• Effective fan out:

• The goal is to minimize the delay through

the entire inverter chain
209

minimum
Chain of N inverters
sized final load

in out
1 2 N
Cg,1 no wire CL
loads

• Delay of jth inverter:

• Total delay is:
• Assume:

• Optimality conditions:
210
Image adapted from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic

9
 6/8/2018

Optimum size of inverter

• Optimum size of each inverter is

geometric mean of neighbor’s sizes!

211

Implications

• Each inverter should be sized up by same

factor fopt compared to preceding gate

WHY?

212

10
 6/8/2018

Implications (cont’d)

• With

the minimum (total) delay is

• Simply a result of

213

Example: simple chain

in
out

1 f f2 C L= 8 C 1
C1

• F=CL/C1 has to be evenly distributed

across N=3 stages:

214

11
 6/8/2018

Optimal number of stages Nopt

• There is a trade-off
– too many stages: intrinsic delay dominates
– too few stages: effective fan-out dominates

• Has no closed-form solution 

• Solution is about 3.6 for
215

Assume no self loading

• Implies
• Solve

• Leads to so-called exponential horn

216

12
 6/8/2018

Optimum effective fan-out fopt

5 7

6
4.5
5
4
4

3.5 3

2
3
1
2.5 0
0 0.5 1 1.5 2 2.5 3
1 1.5 2 2.5 3 3.5 4 4.5 5
 f

• Choosing f larger than optimum has little

effect on delay and reduces # stages
– f=4 is common practice for
– too many stages has negative impact on delay
217
Image taken from: http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter5.pdf

Example: buffer design

N f tp
1 64 1 64 65

1 8 64 2 8 18

1 4 16 64 3 4 15

1
22.6 64 4 2.8 15.3
2.8 8

218

13
 6/8/2018

Example: size the buffers

always
Cext/Cint C1
CL=64C1

219

Example: size the buffers (cont’d)

CL=64C1
C1
buffer 2 is 3.6x larger
than buffer 1

buffer 3 is 8.8x larger

than buffer 1

220

14
 6/8/2018

Examples

Delay minimization

221

Two cases for delay minimization

in out
1 2 N
Cg,1 CL

• Known number of gates N, unknown f

– Find optimal f such that F=fN
• Known fopt, unknown N
– Find N with f as close as possible to fopt

222
Image adapted from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic

15
 6/8/2018

Example: propagation delay tp

1

Cg 1 4 16 CL
CW

223

16