UNIT I Minimization Technique

Unit No. Sr. No. Question Option 1 Option 2 Option 3 Option 4 Answer
1 The NAND gate output will be low if the two inputs
1 are 0 1 10 11 4

2 Karnaugh-map is used for the purpose of Reducing the electronic To map the given To minimize the terms in a To maximize the terms of a
1 circuits used. Boolean logic function Boolean expression given a Booean expression 3

3 If Y=AC+BC is given expression then A,B and C are Minterm Maxterms Literal None
1 called as_____ 3
4 The expression Y= AB+BC+AC is in ______ form. SOP POS Combination of SOP and None
1 POS. 1
5 For three variable combinational circuit Σm= ΣM(0,2,3,5,6) π M(0,2,3,5,6) Σm(0,2,3,5,6) πm (0,2,3,5,6)
1 (1,4,7)= ______. 2

1 6 Octate eliminates _____variables Two Four Three None 3

7 Don’t care condition (X) may be assumed to be 0 1 0 or 1 None
1 _____. 3

1 8 A+AB+ABC+ABCD+ABCDE…. = 1 A A+AB AB 2
9 The _____ is group of minterms that cannot be Essential Prime Prime Implicant Non Essential Prime None of these
1 combined with any other minterm or group Implicant Implicant 2

10 The implicates which will definitely occur in the final Prime implicant Essential prime implicant Selective prime implicants None of above
1 expression are called----- 2

11 Total number of cells in K-map of a switching 4 8 10 12 2

1 function(A,B,C) consisting of only three variables is

1 12 Quad eliminates _____variables Two Four Three None 1

13 Which of the following expressions is in the product- (A + B)(C + D) (AB)(CD) AB(CD) AB + CD
1 of-sums form? 1

14 The most suitable gate to check whether the number X-OR NAND NOR AND, OR and NOT
1 of 1’s in a digital word is even or odd is 1

15 The number of rows in the truth table of a 4- input 4 8 12 16

1 gate is, 4
 16 When grouping cells within a K-map, the cells must be 2s 1, 2, 4, 8, etc 4s 3s
1 combined in groups of ________. 2

17 In which function is each term known as min term? SOP POS Hybrid Both SOP POS
1 1
18 A NAND gate is called a universal logic element because it is used by everybody any logic function can be all the minization techniques many digital computers use
realized by NAND gates are applicable for optimum NAND gates
1 alone NAND gate realization 2

19 Which of the following expressions is in the sum-of-

1 products (SOP) form? Y = (A + B)(C+ D) Y = AB(C+CD) Y = AB + BC Y = (Ab + Bb). (A + B) 3

1 20 _____ eliminates three variables Quad Octet Pair none 2

21 The implementation of simplified sum-of-products
expressions may be easily implemented into actual logic
circuits using all universal ________ gates with little or
no increase in circuit complexity. (Select the response
1 AND/OR NAND NOR OR/AND 2
for the blank space that will BEST make the statement
true.)

22 The simplified form of the Boolean expression

1 (X+Y+XY) (X+Z) is X+Y+Z XY+YZ X+YZ XZ+Y 3

23 The output of a logic gate is 1 when all its inputs are at A NAND or a NOR An AND or an OR An OR or an X-OR An AND or a NOR
1 logic 1, the gate is either 2

24 The output of a logic gate is 1 when all its inputs are at A NAND or a NOR An AND or an OR An OR or an X-OR An AND or a NOR
1 logic 0. The gate is either 1

1 25 A+B=B+A; AB=BA represent which laws Commutative Associative Distributive Idempotence 1

26 In which function is each term known as Max term? SOP POS Hybrid Both SOP POS
1 2
27 The group of two adjacent 1's or 0's is called as quad pair octet none
1 2
28 In K-map -----grouping of of 1's is not allowed Horizontal Vertical Digonal Corner
1 3
29 In signed binary representation 0 represent ---no Positive negative odd even
1 1
30 In K map input values are ordered in---code sequence binary Gray Decimal excess 3
1 2
 UNIT II Combinational Logic Design

Unit No. Sr. No. Question Option 1 Option 2 Option 3 Option 4 Answer
1 The gates required to build a half adder are EX-OR gate and NOR
EX-OR gate and AND
2 gate EX-OR gate and OR gate Four NAND gates. 3
gate
2 In _____ circuit does not need memory. Combinational Sequential Both option 1 & option None of these
2 2 1

3 Which of the following are examples of combinational Adder Comparator Both option 1 & option None of these
2 circuit? 2 3

4 A 4:1 mux has _________ input and __________ 1,4 4,1 2,4 4,2
2 outputs. 2

5 How many data select lines are required for selecting 1 2 3 4

2 eight inputs? 3

6 NAND gates X-OR gates NOR gates

2 For checking the parity of a digital word, it is preferable 3
to use AND gates
2 7 ____ is a 4 bit comparator IC 7400 7413 7485 7483 4
8 Which of the following logic circuit takes data from a multiplexer
single source and distributes it to one Of several output
2 demultiplexer encoder decoder 2
lines?

9 Relation between no of output(n) and select lines (m) in n=2^m m=2^n n=2^(m-1) n=(2^m)-1
2 DEMUX is 1

10 What distinguishes the look-ahead-carry adder? It is slower than the It is easier to implement It is faster than a None of above
ripple-carry adder. logically than ripple-carry ripple-carry adder.
2 3
adder.

11 What is the function of an enable input on a multiplexer To apply Vcc To connect ground To active the entire To active one half of the chip
2 chip? chip 3

12 Binary to gray code converter requires___ Ex-Or gates. 1 2 3 4

2 3

2 13 DEMUX is___________________ circuit Combinational Sequential Memory Element All of that above 1
14 A decoder circuit does not have the __input Select Data Control none
2 2

2 15 Full adder having----inputs----outputs 3,2 2,3 1,2, 2,1 1

2 16 Multiplexer is known as data selector data encoder data recorder none of these 1
17 Invalid BCD convert into valid BCD by adding binary 2 4 5 6
2 no of 4

18 Full Substractor having----inputs----outputs 3,2 2,3 1,2, 2,1

2 1

19 2 3 4 5
2 2
The number of control lines for a 8 :1 multiplexer is
2 20 A BCD no can not be greater than 2 4 9 8 3
21 Comarator circuit having ---input----output 2,3 2,2, 3,2 1,1
2 1

2 22 IC 74LS153 is a ______. 4:1 mux 8:1 mux 16:1 mux Dual 4:1 mux 4
2 23 Which logic device is called distributor? demultiplexer multiplexer encoder decoder 1
24 PEO=-----it means error is present in received word 1 0 2 3
2 1

25 PEO=-----it means no error is present in received 1 0 2 3

2 word 2

26 An -----is a combinational circuit is designed to BCD adder Binary adder Digital Comparator none of these
compare the two n-bit binary words applied at its
2 input 3

27 A-----addition technique eliminates problem due to Look ahead carry adder full adder Half adder none of these
2 interstage carry delay 1

2 28 Ic 74LS138 is a ______. demultiplexer multiplexer encoder 3:8 decoder 4

29 Relation between no of Input(n) and select lines (m) in n=2^m m=2^n n=2^(m-1) n=(2^m)-1
2 MUX is 1

30 A 4:1 mux has _________ no of select input 1 2 4 6

2 2