Scribd
Upload
36 views3 pages

EXP5

The document describes an experiment to verify the excitation tables of various flip-flops including SR, D, JK, and T flip-flops. It provides the theory of operation for each type of flip-flop and includes circuit diagrams and truth tables. The experiment procedure involves building circuits using ICs and observing the output for different input combinations to verify the truth tables.

Uploaded by

jyotirmaypatel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
36 views3 pages

EXP5

The document describes an experiment to verify the excitation tables of various flip-flops including SR, D, JK, and T flip-flops. It provides the theory of operation for each type of flip-flop and includes circuit diagrams and truth tables. The experiment procedure involves building circuits using ICs and observing the output for different input combinations to verify the truth tables.

Uploaded by

jyotirmaypatel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

EXPERIMENT-5

OBJECT: Verify the excitation tables of various FLIP-FLOPS

APPARATUS REQUIRED:- IC-7400(NAND), IC-7402(NOR) General Purpose Digital


Trainer, connecting wire.

THEORY:
S-R FLIPS FLOP:-The basics flip flop is an asynchronous circuit. The storage element
employed in clocked sequential circuits are called flip flop. A S-R flip flop can be built using
NOR gate or NAND gate .It has two inputs R and S and two O/P are Q and Q . In a flip flop
the two O/Ps are complementary, If Q=1 then Q =0. A low R and low S result in inactive
state (there is no change). A low R and high S results in set state while high R and low S
results in reset state. If R and S are high sate, the O/P is indeterminate.
D FLIP FLOP:- The D flip flop is a modification of the clocked S-R flip flop. It is basically
an S-R flip flop with an inverter in the R input. The added inverter reduces the number of
inputs from two to one. Sometimes this types of flip flop called a gated D-latch.
J K Flip flop:- A JK flip flop is a refinement of the SR flip flop in that the indeterminate
state of the SR flip flop defined in the JK type. In JK flip flop, J is set and letter K is clear.
When I/P is applied to both JK simultaneously, the flip flop switches to its compliment state,
that is Q(t+1) it switches to Q = 0 and vice versa.
The J K flip flop behave like an S R flip flop except when both J and K are 1, the CP is
transmitted through Gate only.
T Flip flop:- The T flip flop is a single input version of the JK flip flop .The T flips flop
changes state with each clock pulse and hence it acts as a “toggle” switch. In J K flip flop if
J=K, the resulting flip flop is known as T flip flop.
If T=J=K=1, then Qt+1 = Q and then its acts as a toggle switch for energy clock pulse and
hence the output Qt+1 changes.
PROCEDURE:
1. Insert ICs according to the circuit diagram on the trainer board.
2. Give +5V supply to the pin 14 and ground to the pin 7 to all Ics.
3. Give inputs and CLK to the respective pins of the ICs and observe the output at output
logic.
4. Observe LEDs output.
5. Try with different combination of input.
6. Prepare truth table, observe and verify it.

CIRCUIT
DIAGRAM-
TRUTH TABLE FOR SR FLIP FLOP

OUTPUT
INPUT INPUT COMMENT
S R Q(t+1) Q (t+1)
0 0 Qt Qt Previous stage
0 1 0 1 Reset
1 0 1 0 Set
1 1 x x Indeterminate

TRUTH TABLE FOR D FLIP FLOP

Q D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1

TRUTH TABLE FOR JK FLIP FLOP:-

J K Q(t+1)
0 0 Qt
0 1 0
1 0 1
1 1 Toggled state

TRUTH TABLE FOR T FLIP FLOP:-

Q T Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0

RESULT: The truth table of S-R and D, J-K and T flip flop is verified.

PRECAUTIONS:
1. All connection should be tight.
2. After all connection of the circuit, the main supply should be ON

You might also like