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Mach 5

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Mach 5

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MACH 5 CPLD Family

Fifth Generation MACH Architecture

FEATURES
◆ High logic densities and I/Os for increased logic integration
— 128 to 512 macrocell densities
— 68 to 256 I/Os
◆ Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
◆ Performance features to fit system needs
— 5.5 ns tPD Commercial, 7.5 ns tPD Industrial
— 182 MHz fCNT
— Four programmable power/speed settings per block
◆ Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
◆ Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly™ Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
◆ Advanced E2CMOS process provides high performance, cost effective solutions

Publication# 20446 Rev: J

Amendment/0 Issue Date: April 2002
Table 1. MACH 5 Device Features 1
M5-128/1 M5-192/1 M5-256/1 M5-320 M5-384 M5-512
Feature M5LV-128 M5LV-256 M5LV-320 M5LV-384 M5LV-512
Supply Voltage (V) 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3
Macrocells 128 128 192 256 256 320 320 384 384 512 512
Maximum User I/O Pins 120 120 120 160 160 192 160 160 160 256 256
tPD (ns) 5.5 5.5 5.5 5.5 5.5 6.5 6.5 6.5 6.5 6.5 6.5
tSS (ns) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0
tCOS (ns) 4.5 4.5 4.5 4.5 4.5 5.0 5.0 5.0 5.0 5.0 5.0
fCNT (MHz) 182 182 182 182 182 167 167 167 167 167 167
Typical Static Power (mA) 35 35 45 55 55 70 70 75 75 100 100
IEEE 1149.1 Boundary Scan Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PCI-Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Note:
1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.

GENERAL DESCRIPTION
The MACH® 5 family consists of a broad range of high-density and high-I/O Complex
Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds
at high CPLD densities, low power, and supports additional features such as in-system
programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH
5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process
technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The
5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.

2 MACH 5 Family
Table 2. MACH 5 Speed Grades
Speed Grade1
Device -5 -6 -7 -10 -12 -15 -20
M5-1282 C C, I C, I C, I I
M5-128/1 C C, I C, I C, I C, I I
M5LV-128 C C,I C, I C, I I
M5-192/1 C C, I C, I C, I C, I I
M5-2562 C C, I C, I C, I I
M5-256/1 C C, I C, I C, I C, I I
M5LV-256 C C, I C, I C, I I
M5-320 C C, I C, I C, I C, I I
M5LV-320 C C, I C, I C, I C, I I
M5-384 C C, I C, I C, I C, I I
M5LV-384 C C, I C, I C, I C, I I
M5-512 C C, I C, I C, I C, I I
M5LV-512 C C, I C, I C, I C, I I

Note:
1. C = Commercial grade, I = Industrial grade
2. /1 version recommended for new designs

With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512
macrocells to support full system logic integration. Extensive routing resources ensure pinout
retention as well as high utilization. It is ideal for PAL® block device integration and a wide range
of other applications including high-speed computing, low-power applications, communications,
and embedded control. At each macrocell density point, Lattice offers several I/O and package
options to meet a wide range of design needs (Table 3).

Table 3. MACH 5 Package and I/O Options 1

M5-128/1 M5-256/1 M5-320 M5-384 M5-512
M5LV-128 M5-192/1 M5LV-256 M5LV-320 M5LV-384 M5LV-512
Supply Voltage 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3
100-pin TQFP 68 68, 74 68 68 68*, 74
100-pin PQFP 68 68* 68* 68* 68
144-pin TQFP 104 104
144-pin PQFP 104 104* 104* 104* 104*
160-pin PQFP 120 120 120 120 120 120* 120 120* 120 120* 120
208-pin PQFP 160 160 160 160 160 160 160 160
240-pin PQFP 184* 184* 184* 184* 184* 184*
256-ball BGA 192 192* 192* 192* 192* 192*
352-ball BGA 256 256

Note:
1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.

Advanced power management options allow designers to incrementally reduce power while
maintaining the level of performance needed for today’s complex designs. I/O safety features

MACH 5 Family 3
allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system
programmable through an IEEE 1149.1 Test Access Port (TAP) interface.
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block
interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the
block interconnect is called a segment. The second level of interconnect, the segment
interconnect, ties all of the segments together. The only logic difference between any two MACH
5 devices is the number of segments. Therefore, once a designer is familiar with one device,
consistent performance can be expected across the entire family. All devices have four clock pins
available which can also be used as logic inputs.
CLK
Block:
16 MCs 4

Segment:
4 Blocks

Block Interconnect

Segment Interconnect

20446G-001
Figure 1. MACH 5 Block Diagram

The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block
resembles an independent PAL device, it has superior control and logic generation capabilities.
◆ I/O cells
◆ Product-term array and Logic Allocator
◆ Macrocells
◆ Register control generator
◆ Output enable generator

I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block called local
feedback. If the I/O is used in another PAL block, the interconnect feeder assigns a block interconnect
line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment
interconnects provide connections between any two signals in a device. The block feeder assigns
block interconnect lines and local feedback lines to the PAL block inputs.

4 MACH 5 Family
2
OE Generator

Control Generator

32
Block
16

Logic Alocator
Feeder

I/Os
Macrocells
Product-term

Block Interconnect
Array
32

Local Feedback
Input Register
2
32 Path

Interconnect Feeder
20446G-002
Figure 2. PAL Block Structure

Product-Term Array and Logic Allocator

The product-term array uses the same sum-of-products architecture as PAL devices and consists of
32 inputs (plus their complements) and 64 product terms arranged in 16 clusters. A cluster is a sum-
of-products function with either 3 of 4 product terms.
Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of
three or four product terms, but a given cluster can only be steered to one macrocell (Table 4). If
only three product terms in a cluster are steered, the fourth can be used as an input to an XOR
gate for separate logic generation and/or polarity control.
The wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output
switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic
allocation scheme in the MACH 5 device allows for the implementation of large equations (up to
32 product terms) with only one pass through the logic array.

Table 4. Product Term Steering Options for PT Clusters and Macrocells

Macrocell Available Clusters Macrocell Available Clusters
M0 C0, C1, C2, C3, C4 M8 C5, C6, C7, C8, C9, C10, C11, C12
M1 C0, C1, C2, C3, C4, C5 M9 C6, C7, C8, C9, C10, C11, C12, C13
M2 C0, C1, C2, C3, C4, C5, C6 M10 C7, C8, C9, C10, C11, C12, C13, C14
M3 C0, C1, C2, C3, C4, C5, C6, C7 M11 C8, C9, C10, C11, C12, C13, C14, C15
M4 C0, C1, C2, C3, C4, C5, C6, C7 M12 C8, C9, C10, C11, C12, C13, C14, C15
M5 C1, C2, C3, C4, C5, C6, C7, C8 M13 C9, C10, C11, C12, C13, C14, C15
M6 C2, C3, C4, C5, C6, C7, C8, C9 M14 C10, C11, C12, C13, C14, C15
M7 C3, C4, C5, C6, C7, C8, C9, C10 M15 C11, C12, C13, C14, C15

MACH 5 Family 5
Macrocells
The macrocells for MACH 5 devices consist of a storage element which can be configured for
combinatorial, registered or latched operation (Figure 3). The D-type flip-flops can be configured
as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell.
Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In
order to use this option, these macrocells must be accessed via the I/O pins associated with
macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it cannot be used
for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The
I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins
for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be
used as “buried” macrocells to drive device logic via the matrix.

Macrocell

Control Bus
Logic
Allocator

5-8
Clusters/
MC
D Q

Prog. Polarity
Mode
Selection

20446G-003
Figure 3. Macrocell Diagram

Control Generator
The control generator provides four configurable clock lines and three configurable set/reset lines to
each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can
be independently selected by any flip-flop within a block. The clock lines can be configured to
provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks,
and latch enables (Figure 4). Three of the four global clocks, as well as two product-term clocks
and one sum-term clock, are available per PAL block. Positive or negative edge clocking is
available as well as advanced clocking features such as complementary and biphase clocking.
Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful
in applications such as fast data paths. A biphase clock line clocks flip-flops on both the positive
and negative edges of the clock. The configuration options for the four clock lines per PAL block
are as follows:
Clock Line 0 Options
◆ Global clock (0, 1, 2, or 3) with positive or negative edge clock enable
◆ Product-term clock (A*B*C)
◆ Sum-term clock (A+B+C)

6 MACH 5 Family
Clock Line 1 Options
◆ Global clock (0, 1, 2, or 3) with positive edge clock enable
◆ Global clock (0, 1, 2, or 3) with negative edge clock enable
◆ Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase)
Clock Line 2 Options
◆ Global clock (0, 1, 2, or 3) with clock enable
Clock Line 3 Options
◆ Complement of clock line 2 (same clock enable)
◆ Product-term clock (if clock line 2 does not use clock enable

PT (0:3)

PINCLK (0:3) MUX 4TO1

0 IN (0) MUX 2TO1 MUX 2TO1
1 IN (1) CLKIN N (0)
2 IN (2) OUT Clock Enable
CLK0
3 OUT /CLK
IN (3) PT0
U1 N (1)
F0 F1 F0 F0

PT (0:2)

PT0 SET0/RST0

MUX 4TO1
0 /CLK
IN (0) MUX 2TO1
1 CLK1
IN (1) PT1
2 CLK OUT
IN (2) OUT PT1 SET1/RST1
3 OUT
IN (3) PT1
U2 CLKEN1 /PT1(ST)
F0 F1 PT2 BIPHASE
CLKEN2 F0

MUX 2TO1
MUX 4TO1 PT2
0 PT2 SET2/RST2/LE
IN (0) OUT
1
IN (1) CLK2 /PT2
2
IN (2) OUT CLKIN
3 F0
IN (3) Clock Enable Block
U3
F0 F1 MUX
Sets/Reset
2TO1 0–2, LE
PT3
MUX 2TO1
/CLK2
CLK3
PTCLK

F0
Block
Clocks
0–3

20446G-004 20446G-005
Figure 4. Clock Generator Figure 5. Set/Reset Generator

The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for
the PAL block. Each macrocell can choose one of these three lines or choose no set/reset at all.
All three lines can be configured for product term set/reset and two of the three lines can be
configured as sum term set/reset and one of the lines can be configured as product-term or sum-
term latch enable. While the set/reset signals are generated in the control generator, whether that
signal sets or resets a flip-flop is determined within the individual macrocell. The same signal can
set one flip-flop and reset another. PT2 or /PT2 can also be used as a latch enable for macrocells
configured as latches.

MACH 5 Family 7
OE Generator
There is one output enable (OE) generator per PAL block that generates two product-term driven
output enables. Each I/O cell is simply an output buffer. Each I/O cell within the PAL block can
choose to be permanently enabled, permanently disabled, or choose one of the two product term
output enables per PAL block (Figure 6).

Output Enable
Generator

VCC

Internal Feedback

External Feedback

20446G-006
Figure 6. Output Enable Generator and I/O Cell

8 MACH 5 Family
MACH 5 TIMING MODEL
The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5
device, and at the same time, be easy to understand. This model accurately describes all
combinatorial and registered paths through the device, making a distinction between internal
feedback and external feedback. A signal uses internal feedback when it is fed back into the switch
matrix or block without having to go through the output buffer. The input register specifications
are also reported as internal feedback. When a signal is fed back into the switch matrix after having
gone through the output buffer, it is using external feedback.
The parameter, tBUF, is defined as the time it takes to go through the output buffer to the I/O pad.
If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is
followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived.
For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 5 timing model is
shown in Figure 7. Refer to the Technical Note entitled MACH 5 Timing and High Speed Design
for a more detailed discussion about the timing parameters.

(External Feedback)

(Internal Feedback)

COMB/DFF/
LATCH
tSLW
IN tS (S/A) tPDi OUT
tH (S/A) tCO (S/A) i Q tBUF
tSAL tPDLi
tHAL tGOAi
tSRR tSRi
INPUT REG/ tPL1
tBLK tPT tCES
INPUT LATCH tPL2
tSEG tPL3 tCEH
tSIR (S/A) tCO (S/A) i Q
tHIR (S/A) tPDILi tEA
tSIL tGOAi CE SR tER
tHIL tSRi
tSRR
tCES
tCEH

CE SR

PIN CLK

20446G-014
Figure 7. MACH 5 Timing Model

MACH 5 Family 9
MULTIPLE I/O AND DENSITY OPTIONS
The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers
to choose a device close to their logic density and I/O requirements, thus minimizing costs. For
the same package type, every density has the same pin-out. With proper design considerations, a
design can be moved to a higher or lower density part as required.
IEEE 1149.1 - COMPLIANT BOUNDARY SCAN TESTABILITY
Most MACH 5 devices have boundary scan registers and are compliant to the IEEE 1149.1 standard.
This allows functional testing of the circuit board on which the device is mounted through a serial
scan path that can access all critical logic nodes. Internal registers are linked internally, allowing
test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and
shifted out for verification. In addition, these devices can be linked into a board-level serial scan
path for more complete board-level testing.
IEEE 1149.1 - COMPLIANT IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of significant benefits including: rapid
prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.
All MACH 5 devices provide in-system programming (ISP) capability through their IEEE 1149.1-
compliant Boundary Scan Test Access Port. By using the IEEE 1149.1-compliant Boundary Scan
Test Access Port as the communication interface through which ISP is achieved, customers get the
benefit of a standard, well-defined interface.
MACH 5 devices can be programmed across the commercial temperature and voltage range. The
PC-based LatticePRO software facilitates in-system programming of MACH 5 devices. LatticePRO
software takes the JEDEC file output produced by design implementation software, along with
information about the Boundary Scan chain, and creates a set of vectors that are used to drive the
Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Scan chain
via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats
understood by common automated test equipment. This equipment can then be used to program
MACH 5 devices during the testing of a circuit board.
PCI COMPLIANT
MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Bus
Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are
fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to
clamp the inputs as they rise above VCC because of their 5-V input tolerant feature. MACH 5
devices provide the speed, drive, density, output enables and I/Os for the most complex PCI
designs.

10 MACH 5 Family
1
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS
Both the 3.3-V and 5-V VCC MACH 5 devices are safe for mixed supply voltage system designs.
The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they
accept inputs from other 3.3-V devices. The 3.3-V devices will accept inputs up to 5.5 V. Both the
3.3-V and 5-V versions have the same high-speed performance and provide easy-to-use mixed-
voltage design capability.
Note:
1. Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please refer to
Application Note titled “Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices”.

BUS-FRIENDLY INPUTS AND I/OS

All MACH 5 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating
two inverters in series which loop back to the input. This double inversion weakly holds the input
at its last driven logic state. While it is a good design practice to tie unused pins to a known state,
the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can
cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level
“1.” For the circuit diagram, please refer to the document entitled MACH Endurance
Characteristics on the Lattice Data Book CD-ROM or Lattice web site.
POWER MANAGEMENT
There are 4 power/speed options in each MACH 5 PAL block (Table 5). The speed and power
tradeoff can be tailored for each design. The signal speed paths in the lower-power PAL blocks
will be slower than those in the higher-power PAL blocks. This feature allows speed critical paths
to run at maximum frequency while the rest of the signal paths operate in a lower-power mode.
In large designs, there may be several different speed requirements for different portions of the
design.
Table 5. Power Levels
High Speed/High Power 100% Power
Medium High Speed/Medium High Power 67% Power
Medium Low Speed/Medium Low Power 40% Power
Low Speed/Low Power 20% Power

PROGRAMMABLE SLEW RATE

Each MACH 5 device I/O has an individually programmable output slew rate control bit. Each
output can be individually configured for the higher speed transition (3 V/ns) or for the lower
noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate
will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs
with short traces or well terminated lines, the fast slew rate can be used to achieve the highest
speed. The slew rate is adjusted independent of power.
POWER-UP RESET/SET
All flip-flops power up to a known state for predictable system initialization. If a macrocell is
configured to SET on a signal from the control generator, then that macrocell will be SET during
device power-up. If a macrocell is configured to RESET on a signal from the control generator or
is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee

MACH 5 Family 11
initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset
delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized
copying of the array configuration patterns. Once programmed, this bit defeats readback of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
Programming and verification are also defeated by the security bit. The bit can only be reset by
erasing the entire device.

12 MACH 5 Family
MACH 5 PAL BLOCK
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63
Output Enable
Output Enable

Macro I/O
M0 cell Cell
I/O

Macro
M1 cell
I/O
Cell
I/O

M2 Macro
cell I/O I/O
Cell

Macro
M3 cell I/O
Cell
I/O

0
C0 M4 Macro I/O I/O
cell Cell

C2 Macro
I/O
M5 cell
Cell
I/O

C3
C4 Macro I/O
M6 cell I/O

Logic Allocator
Cell

Switch C6 Macro I/O

Matrix M7 cell Cell
I/O

C7
C8 Macro I/O
M8 cell Cell
I/O

C9
C10 Macro I/O I/O
M9 cell Cell
C11
C12
Macro I/O
cell I/O
M10 Cell
C13
C14
Macro
I/O
M11 cell
Cell
I/O
C15
63

Macro I/O
M12 cell Cell
I/O

Macro I/O
M13 cell Cell
I/O

Macro I/O
M14 cell Cell
I/O

Macro I/O I/O

M15 cell Cell

7 16 16

Control
Generator

0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63

4
32

20446G-015
CLK

MACH 5 Family 13
BLOCK DIAGRAM — M5(LV)-128/XXX
SEGMENT 0
Block A/Macrocells 0-15 Block D/Macrocells 0-15

16 16

16 I/O Cells 16 I/O Cells

2 PT OE 2 PT OE
2 16 Control 2 16 Control
Macrocells Generator Macrocells Generator
7 7
32 64 PT 7 PT 32 64 PT 7 PT
64 x 73 64 x 73
AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator

32 32
I0, 1 Block Interconnect
2
32 32

64 x 73 64 x 73
AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator

32 64 PT 7 PT 64 PT 7 PT
32
Macrocells Control Macrocells Control
7 Generator 7 Generator
2 16 2 16
2 PT OE 2 PT OE
I/O Cells I/O Cells
16 16
16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15

CLK0
CLK1
CLK2 4 S E G M E NT I NT E R C O N N E CT
CLK3

Block A/Macrocells 0-15 Block D/Macrocells 0-15

16 16
16 I/O Cells 16 I/O Cells

32 32
I2, 3 Block Interconnect
2
32 32

64 x 73 64 x 73
AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator

32 64 PT 7 PT 64 PT 7 PT
32
Macrocells Control Macrocells Control
7 Generator 7 Generator
2 16 2 16
2 PT OE 2 PT OE

I/O Cells I/O Cells

16 16
16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15

SEGMENT 1 20446G-007

14 MACH 5 Family
SEGMENT 0 SEGMENT 2
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

16 16 16 16

16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

2 PT OE 2 PT OE 2 PT OE 2 PT OE
2 16 Control 2 16 Control 2 16 Control 2 16 Control
Macrocells Generator Macrocells Generator Macrocells Generator Macrocells Generator
7 7 7 7
32 64 PT 7 PT 32 64 PT 7 PT 32 64 PT 7 PT 32 64 PT 7 PT
64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

32 32 32 32

I0 Block Interconnect I2, I3 Block Interconnect

2
32 32 32 32

64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

32 64 PT 7 PT 64 PT 7 PT 32 64 PT 7 PT 64 PT 7 PT
32 32
Macrocells Control Macrocells Control Macrocells Control Macrocells Control
7 Generator 7 Generator 7 Generator 7 Generator
2 16 2 16 2 16 2 16
2 PT OE 2 PT OE 2 PT OE 2 PT OE
I/O Cells I/O Cells I/O Cells I/O Cells
16 16 16 16
16 16 16 16
BLOCK DIAGRAM — M5-192/XXX

Block C/Macrocells 0-15

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15

CLK0
CLK1
CLK2 4
S E G M E NT I NT E R C O N N E CT
CLK3

Block A/Macrocells 0-15 Block D/Macrocells 0-15

MACH 5 Family
16 16
16 I/O Cells 16 I/O Cells

32 32

I1 Block Interconnect

32 32

64 x 73 64 x 73
AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator

32 64 PT 7 PT 64 PT 7 PT
32
Macrocells Control Macrocells Control
7 Generator 7 Generator
2 16 2 16
2 PT OE 2 PT OE

I/O Cells I/O Cells

16 16
16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15

SEGMENT 1

20446G-008

15
16
SEGMENT 0 SEGMENT 3
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

16 16 16 16

16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

32 32 32 32

I0 Block Interconnect I3 Block Interconnect

32 32 32 32

64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

Block C/Macrocells 0-15

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15
BLOCK DIAGRAM — M5(LV)-256/XXX

CLK0
CLK1
CLK2 4 S E G M E NT I NT E R C O N N E CT
CLK3

Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

MACH 5 Family
16 16 16 16

16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

32 32 32 32
I1 Block Interconnect I2 Block Interconnect

32 32 32 32

64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

I/O Cells I/O Cells I/O Cells I/O Cells

16 16 16 16
16 16 16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15

SEGMENT 1 SEGMENT 2

20446G-009
SEGMENT 0 SEGMENT 4
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

16 16 16 16

16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

32 32 32 32
I0 Block Interconnect Block Interconnect

32 32 32 32

64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

32 64 PT 7 PT 64 PT 7 PT 64 PT 7 PT 64 PT 7 PT
32 32 32
Macrocells Control Macrocells Control Macrocells Control Macrocells Control
7 Generator 7 Generator 7 Generator 7 Generator
2 16 2 16 2 16 2 16
2 PT OE 2 PT OE 2 PT OE 2 PT OE
I/O Cells I/O Cells I/O Cells I/O Cells
16 16 16 16
16 16 16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15
BLOCK DIAGRAM — M5(LV)-320/XXX

CLK0
CLK1
CLK2 4 S E G M E NT I NT E R C O N N E CT
CLK3

Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

MACH 5 Family
16 16 16 16 16 16
16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

2 PT OE 2 PT OE 2 PT OE 2 PT OE 2 PT OE 2 PT OE
2 16 Control 2 16 Control 2 16 Control 2 16 Control 2 16 Control 2 16 Control
Macrocells Generator Macrocells Generator Macrocells Generator Macrocells Generator Macrocells Generator Macrocells Generator
7 7 7 7 7 7
32 64 PT 7 PT 32 64 PT 7 PT 32 64 PT 7 PT 32 64 PT 7 PT 32 64 PT 7 PT 32 64 PT 7 PT
64 x 73 64 x 73 64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

32 32 32 32 32 32

I1 Block Interconnect I2 Block Interconnect I3 Block Interconnect

32 32 32 32 32 32

64 x 73 64 x 73 64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

32 64 PT 7 PT 64 PT 7 PT 32 64 PT 7 PT 64 PT 7 PT 32 64 PT 7 PT 64 PT 7 PT
32 32 32
Macrocells Control Macrocells Control Macrocells Control Macrocells Control Macrocells Control Macrocells Control
7 Generator 7 Generator 7 Generator 7 Generator 7 Generator 7 Generator
2 16 2 16 2 16 2 16 2 16 2 16
2 PT OE 2 PT OE 2 PT OE 2 PT OE 2 PT OE 2 PT OE

I/O Cells I/O Cells I/O Cells I/O Cells I/O Cells I/O Cells
16 16 16 16 16 16
16 16 16 16 16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15

SEGMENT 1 SEGMENT 2 SEGMENT 3

20446G-010

17
18
SEGMENT 0 SEGMENT 5 SEGMENT 4
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

16 16 16 16 16 16
16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

32 32 32 32 32 32
I0 Block Interconnect I3 Block Interconnect Block Interconnect

32 32 32 32 32 32

32 64 PT 7 PT 64 PT 7 PT 64 PT 7 PT 64 PT 7 PT 64 PT 7 PT 64 PT 7 PT
32 32 32 32 32
Macrocells Control Macrocells Control Macrocells Control Macrocells Control Macrocells Control Macrocells Control
7 Generator 7 Generator 7 Generator 7 Generator 7 Generator 7 Generator
2 16 2 16 2 16 2 16 2 16 2 16
2 PT OE 2 PT OE 2 PT OE 2 PT OE 2 PT OE 2 PT OE
I/O Cells I/O Cells I/O Cells I/O Cells I/O Cells I/O Cells
16 16 16 16 16 16
16 16 16 16 16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15
BLOCK DIAGRAM — M5(LV)-384/XXX

CLK0
CLK1
CLK2 4 S E G M E NT I NT E R C O N N E CT
CLK3

Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

MACH 5 Family
16 16 16 16 16 16
16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

32 32 32 32 32 32

I1 Block Interconnect Block Interconnect I2 Block Interconnect

32 32 32 32 32 32

I/O Cells I/O Cells I/O Cells I/O Cells I/O Cells I/O Cells
16 16 16 16 16 16
16 16 16 16 16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15

SEGMENT 1 SEGMENT 2 SEGMENT 3

20446G-011
SEGMENT 0 SEGMENT 7
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

16 16 16 16

16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

32 32 32 32
I0 Block Interconnect Block Interconnect

32 32 32 32

64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15
BLOCK DIAGRAM — M5(LV)-512/XXX

CLK0
CLK1
CLK2 4 S E G M E NT
CLK3
Continued

Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

MACH 5 Family
16 16 16 16

16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

32 32 32 32
I1 Block Interconnect Block Interconnect

32 32 32 32

64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

I/O Cells I/O Cells I/O Cells I/O Cells

16 16 16 16
16 16 16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15

20446G-012
SEGMENT 1 SEGMENT 2

19
20
SEGMENT 6 SEGMENT 5
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

16 16 16 16

16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

32 32 32 32

Block Interconnect I3 Block Interconnect

32 32 32 32

64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15
BLOCK DIAGRAM — M5(LV)-512/XXX

I NT E R C O N N E CT

Continued
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15

MACH 5 Family
16 16 16 16

16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells

32 32 32 32
Block Interconnect I2 Block Interconnect

32 32 32 32

64 x 73 64 x 73 64 x 73 64 x 73
AND Logic Array AND Logic Array AND Logic Array AND Logic Array
and Logic Allocator and Logic Allocator and Logic Allocator and Logic Allocator

I/O Cells I/O Cells I/O Cells I/O Cells

16 16 16 16
16 16 16 16

Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block B/Macrocells 0-15 Block C/Macrocells 0-15

20446G-013
SEGMENT 3 SEGMENT 4
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES
M5 Commercial (C) Devices
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature (TA)
Device Junction Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C
Temperature (Note 1) . . . . . . . . . . . +130°C or +150°C Supply Voltage (VCC)
Supply Voltage with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
with Respect to Ground . . . . . . . . . . . -0.5 V to +7.0 V
Industrial (I) Devices
DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V
Ambient Temperature (TA)
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C
Latchup Current (-40°C to +85°C) . . . . . . . . . . 200 mA Supply Voltage (VCC)
Str esses above those listed under Absolute Maximum with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Ratings may cause permanent device failure. Functionality at Operating ranges define those limits between which the
or above these limits is not implied. Exposure to Absolute functionality of the device is guaranteed.
Maximum Ratings for extended periods may affect device
reliability.

5-V DC CHARACTERISITICS OVER OPERATING RANGES

Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
Output HIGH Voltage IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V
(For M5-128/1, M5-192/1, M5-256/1, M5-320,
M5-384, M5-512 Devices) IOH = -100 µA, VCC = Max, VIN = VIH or VIL 3.3 3.6 V
VOH
Output HIGH Voltage IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V
(For M5-128, M5-192, M5-256 Devices) IOH = -2.5 mA, VCC = 5.25 V, VIN = VIH or VIL 3.6 V
VOL Output LOW Voltage (Note 2) IOL = +16 mA, VCC = Min, VIN = VIH or VIL 0.5 V
Guaranteed Input Logical HIGH Voltage for all Inputs
VIH Input HIGH Voltage 2.0 V
(Note 3)
Guaranteed Input Logical LOW Voltage for all Inputs
VIL Input LOW Voltage 0.8 V
(Note 3)
IIH Input HIGH Leakage Current VIN = 5.25, VCC = Max (Note 4) 10 µA
IIL Input LOW Leakage Current VIN = 0, VCC = Max (Note 4) -10 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25, VCC = Max, VIN = VIH or VIL (Note 4) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0, VCC = Max, VIN = VIH or VIL (Note 4) -10 µA
ISC Output Short-Circuit Current VOUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 5) -30 -180 mA

Note:
1. 150° for M5-128, M5-192 and M5-256 devices. 130° for M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384 and M5-512 devices.
2. Total IOL between ground pins should not exceed 64 mA.
3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included.
4. I/O pin leakage is the worst case of IIL and IOZL or IIH and IOZH.
5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.

MACH 5 Family 21
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES
M5LV Commercial (C) Devices
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature (TA)
Device Junction Temperature . . . . . . . . . . . . . +130°C Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C

Supply Voltage Supply Voltage (VCC)

with Respect to Ground . . . . . . . . . . . -0.5 V to +4.5 V with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V

DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Industrial (I) Devices

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C
Latchup Current (-40°C to +85°C) . . . . . . . . . . 200 mA
Str esses above those listed under Absolute Maximum Supply Voltage (VCC)
Ratings may cause permanent device failure. Functionality at with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V
or above these limits is not implied. Exposure to Absolute Operating ranges define those limits between which the
Maximum Ratings for extended periods may affect device functionality of the device is guaranteed.
reliability.

3.3-V DC CHARACTERISITICS OVER OPERATING RANGES

Parameter
Symbol Parameter Description Test Description Min Max Unit
VCC = Min IOH = -100 µA VCC -0.2 V
VOH Output HIGH Voltage
VIN = VIH or VIL IOH = 3.2 mA 2.4 V
VCC = Min IOL = 100 µA 0.2 V
VOL Output LOW Voltage
VIN = VIH or VIL IOL = 16 mA (Note 1) 0.5 V
VIH Input HIGH Voltage VOUT ≥ VOH Min or VOUT ≤ VOL Max (Note 2) 2.0 5.5 V
VIL Input LOW Voltage VOUT ≥ VOH Min or VOUT ≤ VOL Max (Note 2) -0.3 0.8 V
IIH Input HIGH Leakage Current VIN = 3.6, VCC = Max (Note 3) 10 µA
IIL Input LOW Leakage Current VIN = 0, VCC = Max (Note 3) -10 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 3.6, VCC = Max, VIN = VIH or VIL (Note 3) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0, VCC = Max, VIN = VIH or VIL (Note 3) -10 µA
ISC Output Short-Circuit Current VOUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 4) -15 -160 mA

Notes:
1. Total IOL between ground pins should not exceed 64 mA.
2. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included.
3. I/O pin leakage is the worst case of IIL and IOZL or IIH and IOZH.
4. Not more than one output should be shorted at one time. Duration of the short-circuit should not exceed one second.

22 MACH 5 Family
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1
-5 -6 -7 -10 -12 -15 -20
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Combinatorial Delay:
Internal combinatorial propagation
tPDi 3.5 4.5 5.5 8.0 10.0 13.0 18.0 ns
delay
tPD Combinatorial propagation delay 5.5 6.5 7.5 10.0 12.0 15.0 20.0 ns
Registered Delays:
tSS Synchronous clock setup time 3.0 3.0 4.0 5.0 6.0 8.0 10.0 ns
tSA Asynchronous clock setup time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns
tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns
tHA Asynchronous clock hold time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns
tCOSi Synchronous clock to internal output 2.5 3.0 4.0 5.0 6.0 8.0 10.0 ns
tCOS Synchronous clock to output 4.5 5.0 6.0 7.0 8.0 10.0 12.0 ns
tCOAi Asynchronous clock to internal output 6.0 6.0 8.0 10.0 13.0 15.0 18.0 ns
tCOA Asynchronous clock to output 8.0 8.0 10.0 12.0 15.0 17.0 20.0 ns
Latched Delays:
tSAL Latch setup time 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns
tHAL Latch hold time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns
tPDLi Transparent latch internal 6.0 7.0 7.0 8.0 9.0 10.0 10.0 ns
Propagation delay through transparent
tPDL 8.0 9.0 9.0 10.0 11.0 12.0 12.0 ns
latch
tGOAi Gate to internal output 7.0 8.0 8.0 9.0 10.0 11.0 12.0 ns
tGOA Gate to output 9.0 10.0 10.0 11.0 12.0 13.0 14.0 ns
Input Register Delays:
Input register setup time using a
tSIRS 2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns
synchronous clock
Input register setup time using an
tSIRA 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns
asynchronous clock
Input register hold time using a
tHIRS 3.0 3.0 3.0 4.0 4.0 4.0 4.0 ns
synchronous clock
Input register hold time using an
tHIRA 6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns
asynchronous clock
Input Latch Delays:
tSIL Input latch setup time 2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns
tHIL Input latch hold time 6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns
tPDILi Transparent input latch 5.0 5.0 5.5 6.0 6.0 6.0 6.0 ns
Output Delays:
tBUF Output buffer delay 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns
tSLW Slow slew rate delay 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns
tEA Output enable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns
tER Output disable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns

MACH 5 Family 23
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5 -6 -7 -10 -12 -15 -20
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Power Delays:
4.0 4.0 4.0 4.0 4.0 4.0
tPL1 Power level 1 delay (Note 2) 4.0 ns
(5.0) (5.0) (5.0) (5.0) (5.0) (5.0)
6.0 6.0 6.0 6.0 6.0 6.0
tPL2 Power level 2 delay (Note 2) 6.0 ns
(9.0) (9.0) (9.0) (9.0) (9.0) (9.0)
9.0 9.0 9.0 9.0 9.0 9.0
tPL3 Power level 3 delay (Note 2) 9.0 ns
(17.5) (17.5) (17.5) (17.5) (17.5) (17.5)

Additional Cluster Delay:

tPT Product term cluster delay 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns
Interconnect Delays:
tBLK Block interconnect delay 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns
tSEG Segment interconnect delay 4.5 4.5 5.0 6.0 6.0 6.0 6.0 ns
Reset and Preset Delays:
Asynchronous reset or preset to internal
tSRi 6.0 8.0 8.0 10.0 12.0 14.0 16.0 ns
register output
Asynchronous reset or preset to register
tSR 8.0 10.0 10.0 12.0 14.0 16.0 18.0 ns
output
tSRR Reset and set register recovery time 5.5 7.5 7.5 8.0 9.0 10.0 11.0 ns
tSRW Asynchronous reset or preset width 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns
Clock Enable Delays:
tCES Clock enable setup time 4.0 5.0 5.0 6.0 7.0 7.0 8.0 ns
tCEH Clock enable hold time 3.0 4.0 4.0 5.0 6.0 6.0 7.0 ns
Width:
tWLS Global clock width low (Note 3) 2.5 3.0 3.0 4.0 5.0 6.0 6.0 ns
tWHS Global clock width high (Note 3) 2.5 3.0 3.0 4.0 5.0 6.0 6.0 ns
tWLA Product term clock width low 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns
tWHA Product term clock width high 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns
Gate width low (for low transparent) or
tGWA 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns
high (for high transparent)
tWIR Input register clock width low or high 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns

24 MACH 5 Family
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5 -6 -7 -10 -12 -15 -20
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Frequency:
External feedback, PAL block level. Min
133 125 100 83.3 71.4 55.6 45.5 MHz
of 1/(tWLS + tWHS) or 1/(tSS + tCOS)
Internal feedback, PAL block level. Min
fMAX 182 167 125 100 83.3 62.5 50.0 MHz
of 1/(tWLS + tWHS) or 1/(tSS +tCOSi)
No feedback PAL block level. Min of
200 167 167 125 100 83.3 83.3 MHz
1/(tWLS + tWHS) or 1/(tSS + tHS)
External feedback, PAL block level. Min
91 91 71.4 58.8 47.6 41.7 35.7 MHz
of 1/(tWLA + tWHA) or 1/(tSA + tCOA)
Internal feedback, PAL block level. Min
fMAXA 111 111 83.3 66.7 52.6 45.5 38.5 MHz
of 1/(tWLA + tWHA) or 1/(tSA +tCOAi)
No feedback, PAL block level. Min of
167 125 125 100 83.3 71.4 62.5 MHz
1/(tWLA + tWHA) or 1/(tSA + tHA)
Maximum input register frequency
fMAXI 167 125 125 100 83.3 71.4 62.5 MHz
1/(tSIRS+tHIRS) or 1/(2 x tWICW)

Notes:
1. See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site.
2. Numbers in parentheses are for M5-128, M5-192, M5-256.
3. If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (fMAX/2).

MACH 5 Family 25
CAPACITANCE1
Parameter
Parameter Symbol Description Test conditions Typ Unit
CIN I/CLK pin VIN =2.0 V 3.3 V or 5 V, 25º C, 1 MHz 12 pF
CI/O I/O pin VOUT =2.0 V 3.3 V or 5 V, 25º C, 1 MHz 10 pF

1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
these parameters may be affected.

ICC vs. FREQUENCY

These curves represent the typical power consumption for a particular device at system frequency.
The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and
exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type
register. Power/Speed are optimized to obtain the highest counter frequency and the lowest
power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high
power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to
lowest power. For a more detailed discussion about MACH 5 power consumption, refer to the
application note entitled MACH 5 Power in the Application Notes section on the Lattice Data Book
CD-ROM or Lattice web site.
ICC CURVES AT HIGH /LOW POWER MODES
VCC = 5 V or 3.3 V, TA = 25º C
700 M5(LV)-512 high power

600
M5(LV)-384 high power

500
M5(LV)-320 high power

M5-256/1 and
400
M5LV-25 high power
ICC (mA)

300
M5-192/1 high power
M5-128/1 and M5LV-128 high power
200 M5(LV)-512 low power
M5(LV)-384 low power
M5(LV)-320 low power
M5-256/1 and M5LV-256 low power
100 M5-192/1 low power
M5-128/1 and M5LV-128 low power
0
0

100

110

120

130

140

150

Frequency (MHz) 20446G-048

Figure 8. ICC Curves at High/Low Power Modes

26 MACH 5 Family
VCC = 5 V, TA = 25º C

700

M5-256 high power

600

500 M5-192 high power

400
ICC (mA)

M5-128 high power

300

200
M5-256 low power
M5-192 low power
100 M5-128 low power

0
0

100

110

120

130

140

150
Frequency (MHz) 20446G-049

Figure 9. ICC Curves at High/Low Power Modes

MACH 5 Family 27
100-PIN PQFP CONNECTION DIAGRAM
Top View
100-Pin PQFP (68 I/O)

M5-128 M5-128

0D11
0D12
0D13
0A13
0A12
0A11

0D2
0D3
0D4
0D7
0D8
0A8
0A7
0A4
0A3
0A2
M5LV-128* M5LV-128*

0A7
0A6
0A5
0A4
0A3
0A2
0A1
0A0

2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
M5-192* M5-192*

0A7
0A6
0A5
0A4
0A3
0A2
0A1
0A0

3A0
3A1
3A2
3A3
3A4
3A5
3A6
3A7
M5-256* M5-256*
M5LV-256 M5LV-256

I/O67
I/O66
I/O65
I/O64
I/O63
I/O62
I/O61
I/O60

I/O59
I/O58
I/O57
I/O56
I/O55
I/O54
I/O53
I/O52
GND
GND
VCC

VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
GND 1 80 GND
GND 2 79 GND
TDI 3 78 TDO
0A14 0A12 0A12 I/O0 4 77 I/O51 3A12 2A12 0D14
0B13 0B13 0B13 I/O1 5 76 I/O50 3B13 2B13 0C13
0B12 0B12 0B12 I/O2 6 75 I/O49 3B12 2B12 0C12
0B11 0B11 0B11 I/O3 7 74 I/O48 3B11 2B11 0C11
0B8 0B8 0B8 I/O4 8 73 I/O47 3B8 2B8 0C8
0B7 0B7 0B7 I/O5 9 72 I/O46 3B7 2B7 0C7
0B4 0B4 0B4 I/O6 10 71 I/O45 3B4 2B4 0C4
0B3 0B3 0B3 I/O7 11 70 I/O44 3B3 2B3 0C3
0B2 0B2 0B2 I/O8 12 69 I/O43 3B2 2B2 0C2
I0/CLK0 13 68 I3/CLK3
VCC 14 67 GND
VCC 15 66 GND
GND 16 65 VCC
GND 17 64 VCC
I1/CLK1 18 63 I2/CLK2
1B2 1B2 1B2 I/O9 19 62 I/O42 2B2 2C2 1C2
1B3 1B3 1B3 I/O10 20 61 I/O41 2B3 2C3 1C3
1B4 1B4 1B4 I/O11 21 60 I/O40 2B4 2C4 1C4
1B7 1B7 1B7 I/O12 22 59 I/O39 2B7 2C7 1C7
1B8 1B8 1B8 I/O13 23 58 I/O38 2B8 2C8 1C8
1B11 1B11 1B11 I/O14 24 57 I/O37 2B11 2C11 1C11
1B12 1B12 1B12 I/O15 25 56 I/O36 2B12 2C12 1C12
1B13 1B13 1B13 I/O16 26 55 I/O35 2B13 2C13 1C13
1A14 1A12 1A12 I/O17 27 54 I/O34 2A12 2D12 1D14
TCK 28 53 TMS
GND 29 52 GND
GND 30 51 GND
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
VCC
GND
GND
VCC
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33

M5-256* M5-256*
1A7
1A6
1A5
1A4
1A3
1A2
1A1
1A0

2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7

M5LV-256 M5LV-256
1A7
1A6
1A5
1A4
1A3
1A2
1A1
1A0

2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7

M5-192* M5-192*
1A13
1A12
1A11
1A8
1A7
1A4
1A3
1A2

1D2
1D3
1D4
1D7
1D8
1D11
1D12
1D13

M5-128 M5-128
M5LV-128* M5LV-128*

*Package obsolete, contact factory.

20446G-016

Pin Designations
CLK = Clock VCC = Supply Voltage 3 D 15
GND = Ground TDI = Test Data In
I = Input TCK = Test Clock Macrocell (0-15)
I/O = Input/Output TMS = Test Mode Select PAL Block (A-D)
NC = No Connect TDO = Test Data Out Segment (0-3)

28 MACH 5 Family
100-PIN TQFP CONNECTION DIAGRAM – 68 I/O
Top View
100-Pin TQFP (68 I/O)

0D11
0D12
0D13
0A13
0A12
0A11
M5-128 M5-128

0D2
0D3
0D4
0D7
0D8
0A8
0A7
0A4
0A3
0A2
M5LV-128 M5LV-128

0A7
0A6
0A5
0A4
0A3
0A2
0A1
0A0

2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
M5-192 M5-192

M5-256 M5-256

0A7
0A6
0A5
0A4
0A3
0A2
0A1
0A0

3A0
3A1
3A2
3A3
3A4
3A5
3A6
3A7
M5LV-256* M5LV-256*

I/O67
I/O66
I/O65
I/O64
I/O63
I/O62
I/O61
I/O60

I/O59
I/O58
I/O57
I/O56
I/O55
I/O54
I/O53
I/O52
GND
GND

GND
GND

GND
VCC

VCC
NC

NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TDI 1 75 GND
0A14 0A12 0A12 I/O0 2 74 TDO
0B13 0B13 0B13 I/O1 3 73 I/O51 3A12 2A12 0D14
0B12 0B12 0B12 I/O2 4 72 I/O50 3B13 2B13 0C13
0B11 0B11 0B11 I/O3 5 71 I/O49 3B12 2B12 0C12
0B8 0B8 0B8 I/O4 6 70 I/O48 3B11 2B11 0C11
0B7 0B7 0B7 I/O5 7 69 I/O47 3B8 2B8 0C8
0B4 0B4 0B4 I/O6 8 68 I/O46 3B7 2B7 0C7
0B3 0B3 0B3 I/O7 9 67 I/O45 3B4 2B4 0C4
0B2 0B2 0B2 I/O8 10 66 I/O44 3B3 2B3 0C3
I0/CLK0 11 65 I/O43 3B2 2B2 0C2
VCC 12 64 I3/CLK3
GND 13 63 GND
GND 14 62 VCC
I1/CLK1 15 61 I2/CLK2
1B2 1B2 1B2 I/O9 16 60 I/O42 2B2 2C2 1C2
1B3 1B3 1B3 I/O10 17 59 I/O41 2B3 2C3 1C3
1B4 1B4 1B4 I/O11 18 58 I/O40 2B4 2C4 1C4
1B7 1B7 1B7 I/O12 19 57 I/O39 2B7 2C7 1C7
1B8 1B8 1B8 I/O13 20 56 I/O38 2B8 2C8 1C8
1B11 1B11 1B11 I/O14 21 55 I/O37 2B11 2C11 1C11
1B12 1B12 1B12 I/O15 22 54 I/O36 2B12 2C12 1C12
1B13 1B13 1B13 I/O16 23 53 I/O35 2B13 2C13 1C13
1A14 1A12 1A12 I/O17 24 52 I/O34 2A12 2D12 1D14
TCK 25 51 TMS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50GND
GND
GND
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
NC
VCC
GND
GND
VCC
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
GND
1A7
1A6
1A5
1A4
1A3
1A2
1A1
1A0

2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7

M5-256 M5-256
M5LV-256* M5LV-256*
1A7
1A6
1A5
1A4
1A3
1A2
1A1
1A0

2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7

M5-192 M5-192
1A13
1A12
1A11
1A8
1A7
1A4
1A3
1A2

1D2
1D3
1D4
1D7
1D8
1D11
1D12
1D13

M5-128 M5-128
M5LV-128 M5LV-128
*Package obsolete, contact factory.

20446G-017

MACH 5 Family 29
100-PIN TQFP CONNECTION DIAGRAM – 74 I/O
Top View
100-Pin TQFP (74 I/O)

0D11
0D12
0D13
0A13
0A12
0A11
0A10
M5LV-128 M5LV-128

0D1
0D2
0D3
0D4
0D7
0D8
0A9
0A8
0A7
0A4
0A3
0A2
0D11
0D12

3D12
M5LV-256 M5LV-256

0A7
0A6
0A5
0A4
0A3
0A2
0A1
0A0

3A0
3A1
3A2
3A3
3A4
3A5
3A6
3A7
I/O73
I/O72
I/O71
I/O70
I/O69
I/O68
I/O67
I/O66
I/O65
I/O64

I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
I/O55
GND

GND
GND

GND
VCC

VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TDI 1 75 GND
0A14 0A12 I/O0 2 74 TDO
0B13 0B13 I/O1 3 73 I/O54 3A12 0D14
0B12 0B12 I/O2 4 72 I/O53 3B13 0C13
0B11 0B11 I/O3 5 71 I/O52 3B12 0C12
0B8 0B8 I/O4 6 70 I/O51 3B11 0C11
0B7 0B7 I/O5 7 69 I/O50 3B8 0C8
0B4 0B4 I/O6 8 68 I/O49 3B7 0C7
0B3 0B3 I/O7 9 67 I/O48 3B4 0C4
0B2 0B2 I/O8 10 66 I/O47 3B3 0C3
I0/CLK0 11 65 I/O46 3B2 0C2
VCC 12 64 I3/CLK3
GND 13 63 GND
GND 14 62 VCC
I1/CLK1 15 61 I2/CLK2
1B2 1B2 I/O9 16 60 I/O45 2B2 1C2
1B3 1B3 I/O10 17 59 I/O44 2B3 1C3
1B4 1B4 I/O11 18 58 I/O43 2B4 1C4
1B7 1B7 I/O12 19 57 I/O42 2B7 1C7
1B8 1B8 I/O13 20 56 I/O41 2B8 1C8
1B11 1B11 I/O14 21 55 I/O40 2B11 1C11
1B12 1B12 I/O15 22 54 I/O39 2B12 1C12
1B13 1B13 I/O16 23 53 I/O38 2B13 1C13
1A14 1A12 I/O17 24 52 I/O37 2A12 1D14
TCK 25 51 TMS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50 GND
GND
1A13 1A7 I/O18
1A12 1A6 I/O19
1A11 1A5 I/O20
1A10 1A4 I/O21
1A8 1A3 I/O22
1A7 1A2 I/O23
1A4 1A1 I/O24
1A3 1A0 I/O25
1A2 1D11 I/O26
1A1 1D12 1/O27
VCC
GND
GND
VCC
1D2 2D12 I/O28
1D3 2A0 I/O29
1D4 2A1 I/O30
1D7 2A2 I/O31
1D8 2A3 I/O32
1D10 2A4 I/O33
1D11 2A5 I/O34
1D12 2A6 I/O35
1D13 2A7 1/O36

M5LV-256 M5LV-256

M5LV-128 M5LV-128

20446G-018

30 MACH 5 Family
144-PIN PQFP CONNECTION DIAGRAM
Top View
144-Pin PQFP

0D10
0D11
0D12
0D13
0A13
0A12
0A11
M5-128 M5-128

0D0
0D1
0D2
0D3
0D4
0D5

0D6
0D7
0D8
A10
0A8
0A7
0A6

0A5
0A4
0A3
0A2
0A1
0A0
M5LV-128* M5LV-128*

0D11
0D12
0D13
0A11
0A10

2A10
2A11
M5-192* M5-192*

0D2
0D3
0D4
0D7

0D8
0A8
0A7
0A6
0A5
0A4

0A3
0A2

2A2
2A3

2A4
2A5
2A6
2A7
2A8
0D11
0D12

3D12
3D11
M5-256* M5-256*

0D3
0D4
0D7
0D8

3D8
3D7
3D4
3D3
0A7
0A6
0A5
0A4
0A3
0A2
0A1

3A1
3A2
3A3
3A4
3A5
3A6
3A7
M5LV-256* M5LV-256*

I/O103
I/O102
I/O101
I/O100
I/O99
I/O98
I/O97

I/O96
I/O95
I/O94
I/O93
I/O92
I/O91

I/O90
I/O89
I/O88
I/O87
I/O86
I/O85

I/O84
I/O83
I/O82
I/O81
I/O80
I/O79
I/O78
GND

GND

GND
GND

GND

GND
VCC

VCC

VCC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
TDI 1 108 TDO
0A14 0A12 0A8 I/O0 2 107 I/O77 3A8 2A12 0D14
0B13 0A13 0A9 I/O1 3 106 I/O76 3A9 2A13 0C13
0B12 0A14 0A10 I/O2 4 105 I/O75 3A10 2A14 0C12
0B11 0B13 0A11 I/O3 5 104 I/O74 3A11 2B13 0C11
0B10 0B12 0A12 I/O4 6 103 I/O73 3A12 2B12 0C10
GND 7 102 GND
0B8 0B11 0B13 I/O5 8 101 I/O72 3B13 2B11 0C8
0B7 0B8 0B12 I/O6 9 100 I/O71 3B12 2B8 0C7
0B6 0B5 0B11 I/O7 10 99 I/O70 3B11 2B5 0C6
0B5 0B4 0B8 I/O8 11 98 I/O69 3B8 2B4 0C5
GND 12 97 GND
0B4 0B3 0B5 I/O9 13 96 I/O68 3B5 2B3 0C4
0B3 0B2 0B4 I/O10 14 95 I/O67 3B4 2B2 0C3
0B2 0B1 0B3 I/O11 15 94 I/O66 3B3 2B1 0C2
0B1 0B0 0B2 I/O12 16 93 I/O65 3B2 2B0 0C1
I0/CLK0 17 92 I3/CLK3
VCC 18 91 GND
GND 19 90 VCC
I1/CLK1 20 89 I2/CLK2
1B1 1B0 1B2 I/O13 21 88 I/O64 2B2 2C0 1C1
1B2 1B1 1B3 I/O14 22 87 I/O63 2B3 2C1 1C2
1B3 1B2 1B4 I/O15 23 86 I/O62 2B4 2C2 1C3
1B4 1B3 1B5 I/O16 24 85 I/O61 2B5 2C3 1C4
GND 25 84 GND
1B5 1B4 1B8 I/O17 26 83 I/O60 2B8 2C4 1C5
1B6 1B5 1B11 I/O18 27 82 I/O59 2B11 2C5 1C6
1B7 1B8 1B12 I/O19 28 81 I/O58 2B12 2C8 1C7
1B8 1B11 1B13 I/O20 29 80 I/O57 2B13 2C11 1C8
GND 30 79 GND
1B10 1B12 1A12 I/O21 31 78 I/O56 2A12 2C12 1C10
1B11 1B13 1A11 I/O22 32 77 I/O55 2A11 2C13 1C11
1B12 1A14 1A10 I/O23 33 76 I/O54 2A10 2D14 1C12
1B13 1A13 1A9 I/O24 34 75 I/O53 2A9 2D13 1C13
1A14 1A12 1A8 I/O25 35 74 I/O52 2A8 2D12 1D14
TCK 36 73 TMS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
GND
VCC
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
GND
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
VCC
GND
GND
VCC
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
GND
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
VCC
GND
1A7
1A6
1A5
1A4
1A3
1A2
1A1

1D3
1D4
1D7
1D8
1D11
1D12

2D12
2D11
2D8
2D7
2D4
2D3

2A1
2A2
2A3
2A4
2A5
2A6
2A7

M5-256* M5-256*
M5LV-256* M5LV-256*
1A11
1A10
1A8
1A7
1A6
1A5
1A4

1A3
1A2
1D2
1D3
1D4
1D7

1D8
1D11
1D12
1D13
2D2
2D3

2D4
2D5
2D6
2D7
2D8
2D10
2D11

M5-192* M5-192*
1A13
1A12
1A11
1A10
1A8
1A7
1A6

1A5
1A4
1A3
1A2
1A1
1A0

1D0
1D1
1D2
1D3
1D4
1D5

1D6
1D7
1D8
1D10
1D11
1D12
1D13

M5-128 M5-128
M5LV-128* M5LV-128*
*Package obsolete, contact factory.

20446G-019

MACH 5 Family 31
144-PIN TQFP CONNECTION DIAGRAM
Top View
144-Pin TQFP

0D10
0D11
0D12
0D13
0A13
0A12
0A11
M5LV-128 M5LV-128

0D0
0D1
0D2
0D3
0D4
0D5

0D6
0D7
0D8
A10
0A8
0A7
0A6

0A5
0A4
0A3
0A2
0A1
0A0
0D11
0D12

3D12
3D11
M5LV-256 M5LV-256

0D3
0D4
0D7
0D8

3D8
3D7
3D4
3D3
0A7
0A6
0A5
0A4
0A3
0A2
0A1

3A1
3A2
3A3
3A4
3A5
3A6
3A7
I/O103
I/O102
I/O101
I/O100
I/O99
I/O98
I/O97

I/O96
I/O95
I/O94
I/O93
I/O92
I/O91

I/O90
I/O89
I/O88
I/O87
I/O86
I/O85

I/O84
I/O83
I/O82
I/O81
I/O80
I/O79
I/O78
GND

GND

GND
GND

GND

GND
VCC

VCC

VCC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
TDI 1 108 TDO
0A14 0A8 I/O0 2 107 I/O77 3A8 0D14
0B13 0A9 I/O1 3 106 I/O76 3A9 0C13
0B12 0A10 I/O2 4 105 I/O75 3A10 0C12
0B11 0A11 I/O3 5 104 I/O74 3A11 0C11
0B10 0A12 I/O4 6 103 I/O73 3A12 0C10
GND 7 102 GND
0B8 0B13 I/O5 8 101 I/O72 3B13 0C8
0B7 0B12 I/O6 9 100 I/O71 3B12 0C7
0B6 0B11 I/O7 10 99 I/O70 3B11 0C6
0B5 0B8 I/O8 11 98 I/O69 3B8 0C5
GND 12 97 GND
0B4 0B5 I/O9 13 96 I/O68 3B5 0C4
0B3 0B4 I/O10 14 95 I/O67 3B4 0C3
0B2 0B3 I/O11 15 94 I/O66 3B3 0C2
0B1 0B2 I/O12 16 93 I/O65 3B2 0C1
I0/CLK0 17 92 I3/CLK3
VCC 18 91 GND
GND 19 90 VCC
I1/CLK1 20 89 I2/CLK2
1B1 1B2 I/O13 21 88 I/O64 2B2 1C1
1B2 1B3 I/O14 22 87 I/O63 2B3 1C2
1B3 1B4 I/O15 23 86 I/O62 2B4 1C3
1B4 1B5 I/O16 24 85 I/O61 2B5 1C4
GND 25 84 GND
1B5 1B8 I/O17 26 83 I/O60 2B8 1C5
1B6 1B11 I/O18 27 82 I/O59 2B11 1C6
1B7 1B12 I/O19 28 81 I/O58 2B12 1C7
1B8 1B13 I/O20 29 80 I/O57 2B13 1C8
GND 30 79 GND
1B10 1A12 I/O21 31 78 I/O56 2A12 1C10
1B11 1A11 I/O22 32 77 I/O55 2A11 1C11
1B12 1A10 I/O23 33 76 I/O54 2A10 1C12
1B13 1A9 I/O24 34 75 I/O53 2A9 1C13
1A14 1A8 I/O25 35 74 I/O52 2A8 1D14
TCK 36 73 TMS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
GND
VCC
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
GND
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
VCC
GND
GND
VCC
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
GND
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
VCC
GND
1A7
1A6
1A5
1A4
1A3
1A2
1A1

1D3
1D4
1D7
1D8
1D11
1D12

2D12
2D11
2D8
2D7
2D4
2D3

2A1
2A2
2A3
2A4
2A5
2A6
2A7

M5LV-256 M5LV-256
1A13
1A12
1A11
1A10
1A8
1A7
1A6

1A5
1A4
1A3
1A2
1A1
1A0

1D0
1D1
1D2
1D3
1D4
1D5

1D6
1D7
1D8
1D10
1D11
1D12
1D13

M5LV-128 M5LV-128

20446G-020
Pin Designations
CLK = Clock VCC = Supply Voltage 3 D 15
GND = Ground TDI = Test Data In
I = Input TCK = Test Clock Macrocell (0-15)
I/O = Input/Output TMS = Test Mode Select PAL Block (A-D)
NC = No Connect TDO = Test Data Out Segment (0-3)

32 MACH 5 Family
160-PIN PQFP CONNECTION DIAGRAM
Top View
160-Pin PQFP (128, 192, 256 Macrocells)

M5-128 M5-128

0D10
0D11
0D12
0D13
0A13
0A12
0A11
0A10

0D0
0D1
0D2
0D3
0D4
0D5

0D6
0D7
0D8
0D9
0A9
0A8
0A7
0A6

0A5
0A4
0A3
0A2
0A1
0A0
M5LV-128 M5LV-128

0D11
0D12
0D13
0A11
0A10

2A10
2A11
M5-192 M5-192

0D2
0D3
0D4
0D7

0D8
0A9
0A8
0A7
0A6
0A5
0A4

0A3
0A2

2A2
2A3

2A4
2A5
2A6
2A7
2A8
2A9
0D11
0D12

3D12
3D11
M5-256 M5-256

0D3
0D4
0D7
0D8

3D8
3D7
3D4
3D3
0A7
0A6
0A5
0A4
0A3
0A2
0A1
0A0

3A0
3A1
3A2
3A3
3A4
3A5
3A6
3A7
M5LV-256 M5LV-256

I/O119
I/O118
I/O117
I/O116
I/O115
I/O114
I/O113
I/O112

I/O111
I/O110
I/O109
I/O108
I/O107
I/O106

I/O105
I/O104
I/O103
I/O102
I/O101
I/O100

I/O99
I/O98
I/O97
I/O96
I/O95
I/O94
I/O93
I/O92
GND

GND

GND
GND

GND

GND
VCC

VCC

VCC
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
TDI 1 120 TDO
0A14 0A12 0A8 I/O0 2 119 I/O91 3A8 2A12 0D14
0A15 0A13 0A9 I/O1 3 118 I/O90 3A9 2A13 0D15
0B14 0A14 0A10 I/O2 4 117 I/O89 3A10 2A14 0C14
0B13 0A15 0A11 I/O3 5 116 I/O88 3A11 2A15 0C13
0B12 0B15 0A12 I/O4 6 115 I/O87 3A12 2B15 0C12
0B11 0B14 0A13 I/O5 7 114 I/O86 3A13 2B14 0C11
0B10 0B13 0A14 I/O6 8 113 I/O85 3A14 2B13 0C10
0B9 0B12 0A15 I/O7 9 112 I/O84 3A15 2B12 0C9
GND 10 111 GND
0B8 0B11 0B13 I/O8 11 110 I/O83 3B13 2B11 0C8
0B7 0B8 0B12 I/O9 12 109 I/O82 3B12 2B8 0C7
0B6 0B5 0B11 I/O10 13 108 I/O81 3B11 2B5 0C6
0B5 0B4 0B8 I/O11 14 107 I/O80 3B8 2B4 0C5
0B4 0B3 0B5 I/O12 15 106 I/O79 3B5 2B3 0C4
0B3 0B2 0B4 I/O13 16 105 I/O78 3B4 2B2 0C3
0B2 0B1 0B3 I/O14 17 104 I/O77 3B3 2B1 0C2
0B1 0B0 0B2 I/O15 18 103 I/O76 3B2 2B0 0C1
I0/CLK0 19 102 I3/CLK3
VCC 20 101 GND
GND 21 100 VCC
I1/CLK1 22 99 I2/CLK2
1B1 1B0 1B2 I/O16 23 98 I/O75 2B2 2C0 1C1
1B2 1B1 1B3 I/O17 24 97 I/O74 2B3 2C1 1C2
1B3 1B2 1B4 I/O18 25 96 I/O73 2B4 2C2 1C3
1B4 1B3 1B5 I/O19 26 95 I/O72 2B5 2C3 1C4
1B5 1B4 1B8 I/O20 27 94 I/O71 2B8 2C4 1C5
1B6 1B5 1B11 I/O21 28 93 I/O70 2B11 2C5 1C6
1B7 1B8 1B12 I/O22 29 92 I/O69 2B12 2C8 1C7
1B8 1B11 1B13 I/O23 30 91 I/O68 2B13 2C11 1C8
GND 31 90 GND
1B9 1B12 1A15 I/O24 32 89 I/O67 2A15 2C12 1C9
1B10 1B13 1A14 I/O25 33 88 I/O66 2A14 2C13 1C10
1B11 1B14 1A13 I/O26 34 87 I/O65 2A13 2C14 1C11
1B12 1B15 1A12 I/O27 35 86 I/O64 2A12 2C15 1C12
1B13 1A15 1A11 I/O28 36 85 I/O63 2A11 2D15 1C13
1B14 1A14 1A10 I/O29 37 84 I/O62 2A10 2D14 1C14
1A15 1A13 1A9 I/O30 38 83 I/O61 2A9 2D13 1D15
1A14 1A12 1A8 I/O31 39 82 I/O60 2A8 2D12 1D14
TCK 40 81 TMS
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
VCC
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
VCC
GND
GND
VCC
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
VCC
GND
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
VCC
GND
1A7
1A6
1A5
1A4
1A3
1A2
1A1
1A0

1D3
1D4
1D7
1D8
1D11
1D12

2D12
2D11
2D8
2D7
2D4
2D3

2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7

M5-256 M5-256
M5LV-256 M5LV-256
1A11
1A10
1A9
1A8
1A7
1A6
1A5
1A4

1A3
1A2
1D2
1D3
1D4
1D7

1D8
1D11
1D12
1D13
2D2
2D3

2D4
2D5
2D6
2D7
2D8
2D9
2D10
2D11

M5-192 M5-192
1A13
1A12
1A11
1A10
1A9
1A8
1A7
1A6

1A5
1A4
1A3
1A2
1A1
1A0

1D0
1D1
1D2
1D3
1D4
1D5

1D6
1D7
1D8
1D9
1D10
1D11
1D12
1D13

M5-128 M5-128
M5LV-128 M5LV-128

20446G-021

MACH 5 Family 33
160-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM
Top View
160-Pin PQFP (320, 384, 512 Macrocells)

M5-320* M5-320*

0B11
0B12
0B13

4A12
4A11

4B11
4B12

3B13
3B12
3B11
0B2
0B3
0B4
0B7
0B8

4A8
4A7
4A4
4A3

4B3
4B4
4B7
4B8

3B8
3B7
3B4
3B3
3B2
M5LV-320 M5LV-320

0B11
0B12
0B13

5A12
5A11

5B11
5B12

4B13
4B12
4B11
M5-384* M5-384*

0B2
0B3
0B4
0B7
0B8

5A8
5A7
5A4
5A3

5B3
5B4
5B7
5B8

4B8
4B7
4B4
4B3
4B2
M5LV-384 M5LV-384

7A13
7A12
7A11

7B11
7B12

6B12
6B11

6A11
6A12
6A13
M5-512* M5-512*

7A8
7A7
7A4
7A3
7A2

7B3
7B4
7B7
7B8

6B8
6B7
6B4
6B3

6A2
6A3
6A4
6A7
6A8
M5LV-512 M5LV-512

I/O119
I/O118
I/O117
I/O116
I/O115
I/O114
I/O113
I/O112

I/O111
I/O110
I/O109
I/O108
I/O107
I/O106

I/O105
I/O104
I/O103
I/O102
I/O101
I/O100

I/O99
I/O98
I/O97
I/O96
I/O95
I/O94
I/O93
I/O92
GND

GND

GND
GND

GND

GND
VCC

VCC

VCC
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
TDI 1 120 TDO
0A2 0A2 0A2 I/O0 2 119 I/O91 5A2 4A2 3A2
0A3 0A3 0A3 I/O1 3 118 I/O90 5A3 4A3 3A3
0A4 0A4 0A4 I/O2 4 117 I/O89 5A4 4A4 3A4
0A7 0A7 0A7 I/O3 5 116 I/O88 5A7 4A7 3A7
0A8 0A8 0A8 I/O4 6 115 I/O87 5A8 4A8 3A8
0A11 0A11 0A11 I/O5 7 114 I/O86 5A11 4A11 3A11
0A12 0A12 0A12 I/O6 8 113 I/O85 5A12 4A12 3A12
0A13 0A13 0A13 I/O7 9 112 I/O84 5A13 4A13 3A13
GND 10 111 GND
0D13 0D13 0D13 I/O8 11 110 I/O83 5D13 4D13 3D13
0D12 0D12 0D12 I/O9 12 109 I/O82 5D12 4D12 3D12
0D11 0D11 0D11 I/O10 13 108 I/O81 5D11 4D11 3D11
0D8 0D8 0D8 I/O11 14 107 I/O80 5D8 4D8 3D8
0D7 0D7 0D7 I/O12 15 106 I/O79 5D7 4D7 3D7
0D4 0D4 0D4 I/O13 16 105 I/O78 5D4 4D4 3D4
0D3 0D3 0D3 I/O14 17 104 I/O77 5D3 4D3 3D3
0D2 0D2 0D2 I/O15 18 103 I/O76 5D2 4D2 3D2
I0/CLK0 19 102 I3/CLK3
VCC 20 101 GND
GND 21 100 VCC
I1/CLK1 22 99 I2/CLK2
1D2 1D2 1D2 I/O16 23 98 I/O75 4D2 3D2 2D2
1D3 1D3 1D3 I/O17 24 97 I/O74 4D3 3D3 2D3
1D4 1D4 1D4 I/O18 25 96 I/O73 4D4 3D4 2D4
1D7 1D7 1D7 I/O19 26 95 I/O72 4D7 3D7 2D7
1D8 1D8 1D8 I/O20 27 94 I/O71 4D8 3D8 2D8
1D11 1D11 1D11 I/O21 28 93 I/O70 4D11 3D11 2D11
1D12 1D12 1D12 I/O22 29 92 I/O69 4D12 3D12 2D12
1D13 1D13 1D13 I/O23 30 91 I/O68 4D13 3D13 2D13
GND 31 90 GND
1A15 1A13 1A13 I/O24 32 89 I/O67 4A13 3A13 2A15
1A14 1A12 1A12 I/O25 33 88 I/O66 4A12 3A12 2A14
1A13 1A11 1A11 I/O26 34 87 I/O65 4A11 3A11 2A13
1A12 1A8 1A8 I/O27 35 86 I/O64 4A8 3A8 2A12
1A11 1A7 1A7 I/O28 36 85 I/O63 4A7 3A7 2A11
1A10 1A4 1A4 I/O29 37 84 I/O62 4A4 3A4 2A10
1A9 1A3 1A3 I/O30 38 83 I/O61 4A3 3A3 2A9
1A8 1A2 1A2 I/O31 39 82 I/O60 4A2 3A2 2A8
TCK 40 81 TMS
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
VCC
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
VCC
GND
GND
VCC
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
VCC
GND
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
VCC
GND
2A13
2A12
2A11
2A8
2A7
2A4
2A3
2A2

2B3
2B4
2B7
2B8
2B11
2B12

3B12
3B11
3B8
3B7
3B4
3B3

3A2
3A3
3A4
3A7
3A8
3A11
3A12
3A13

M5-512* M5-512*
M5LV-512 M5LV-512
1B2
1B3
1B4
1B7
1B8
1B11
1B12
1B13

2A12
2A11
2A8
2A7
2A4
2A3

2B3
2B4
2B7
2B8
2B11
2B12

3B13
3B12
3B11
3B8
3B7
3B4
3B3
3B2

M5-384* M5-384*
M5LV-384 M5LV-384
1A7
1A6
1A5
1A4
1A3
1A2
1A1
1A0

1B3
1B4
1B7
1B8
1B11
1B12

2B12
2B11
2B8
2B7
2B4
2B3

2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7

M5-320* M5-320*
M5LV-320 M5LV-320
*Package obsolete, contact factory.

20446G-022
Pin Designations
CLK = Clock VCC = Supply Voltage 7 D 15
GND = Ground TDI = Test Data In
I = Input TCK = Test Clock Macrocell (0-15)
I/O = Input/Output TMS = Test Mode Select PAL Block (A-D)
NC = No Connect TDO = Test Data Out Segment (0-7)

34 MACH 5 Family
208-PIN PQFP CONNECTION DIAGRAM
Top View
208-Pin PQFP (256 Macrocells)

0D10
0D11
0D12
0D13

3D13
3D12
3D11
3D10
M5-256 M5-256

0D2
0D3
0D4
0D5
0D6
0D7
0D8
0D9

3D9
3D8
3D7
3D6
3D5
3D4
3D3
3D2
0A7
0A6
0A5
0A4
0A3
0A2
0A1
0A0

3A0
3A1
3A2
3A3
3A4
3A5
3A6
3A7
M5LV-256 M5LV-256

I/O159
I/O158
I/O157
I/O156
I/O155
I/O154
I/O153
I/O152

I/O151
I/O150
I/O149
I/O148
I/O147
I/O146
I/O145
I/O144

I/O143
I/O142
I/O141
I/O140

I/O139
I/O138
I/O137
I/O136

I/O135
I/O134
I/O133
I/O132
I/O131
I/O130
I/O129
I/O128

I/O127
I/O126
I/O125
I/O124
I/O123
I/O122
I/O121
I/O120
GND

GND

GND
GND

GND

GND
VCC

VCC

VCC
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
TDI 1 156 TDO
0A8 I/O0 2 155 I/O119 3A8
0A9 I/O1 3 154 I/O118 3A9
0A10 I/O2 4 153 I/O117 3A10
0A11 I/O3 5 152 I/O116 3A11
0A12 I/O4 6 151 I/O115 2A12
0A13 I/O5 7 150 I/O114 3A13
0A14 I/O6 8 149 I/O113 3A14
0A15 I/O7 9 148 I/O112 3A15
VCC 10 147 VCC
GND 11 146 GND
0B13 I/O8 12 145 I/O111 3B13
0B12 I/O9 13 144 I/O110 3B12
0B11 I/O10 14 143 I/O109 3B11
0B10 I/O11 15 142 I/O108 3B10
0B9 I/O12 16 141 I/O107 3B9
0B8 I/O13 17 140 I/O106 3B8
0B7 I/O14 18 139 I/O105 3B7
0B6 I/O15 19 138 I/O104 3B6
GND 20 137 GND
0B5 I/O16 21 136 I/O103 3B5
0B4 I/O17 22 135 I/O102 3B4
0B3 I/O18 23 134 I/O101 3B3
0B2 I/O19 24 133 I/O100 3B2
I0/CLK0 25 132 I3/CLK3
VCC 26 131 GND
GND 27 130 VCC
I1/CLK1 28 129 I2/CLK2
1B2 I/O20 29 128 I/O99 2B2
1B3 I/O21 30 127 I/O98 2B3
1B4 I/O22 31 126 I/O97 2B4
1B5 I/O23 32 125 I/O96 2B5
GND 33 124 GND
1B6 I/O24 34 123 I/O95 2B6
1B7 I/O25 35 122 I/O94 2B7
1B8 I/O26 36 121 I/O93 2B8
1B9 I/O27 37 120 I/O92 2B9
1B10 I/O28 38 119 I/O91 2B10
1B11 I/O29 39 118 I/O90 2B11
1B12 I/O30 40 117 I/O89 2B12
1B13 I/O31 41 116 I/O88 2B13
GND 42 115 GND
VCC 43 114 VCC
1A15 I/O32 44 113 I/O87 2A15
1A14 I/O33 45 112 I/O86 2A14
1A13 I/O34 46 111 I/O85 2A13
1A12 I/O35 47 110 I/O84 2A12
1A11 I/O36 48 109 I/O83 2A11
1A10 I/O37 49 108 I/O82 2A10
1A9 I/O38 50 107 I/O81 2A9
1A8 I/O39 51 106 I/O80 2A8
TCK 52 100 105 TMS
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
GND
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
GND
VCC
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
GND
I/O56
I/O57
I/O58
I/O59
VCC
GND
GND
VCC
I/O60
I/O61
I/O62
I/O63
GND
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
VCC
GND
I/O72
I/O73
I/O74
I/O75
I/O76
I/O77
I/O78
I/O79
GND
1A7
1A6
1A5
1A4
1A3
1A2
1A1
1A0

1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9

1D10
1D11
1D12
1D13

2D13
2D12
2D11
2D10

2D9
2D8
2D7
2D6
2D5
2D4
2D3
2D2

2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7

M5-256 M5-256
M5LV-256 M5LV-256

20446G-023

MACH 5 Family 35
208-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM
Top View
208-Pin PQFP (320, 384, 512 Macrocells)

0B11
0B12
0B13

4A15
4A14
4A13
4A12
4A11
4A10

4B10
4B11
4B12
4B13
4B14
4B15

3B13
3B12
3B11
M5-320 M5-320

0B2
0B3
0B4
0B7
0B8

4A9
4A8

4A7
4A4
4A3
4A2

4B2
4B3
4B4
4B7

4B8
4B9

3B8
3B7
3B4
3B3
3B2
M5LV-320 M5LV-320

M5-384 M5-384

0B11
0B12
0B13

5A15
5A14
5A13
5A12
5A11
5A10

5B10
5B11
5B12
5B13
5B14
5B15

4B13
4B12
4B11
0B2
0B3
0B4
0B7
0B8

5A9
5A8

5A7
5A4
5A3
5A2

5B2
5B3
5B4
5B7

5B8
5B9

4B8
4B7
4B4
4B3
4B2
M5LV-384 M5LV-384

7A13
7A12
7A11

7B11
7B12
7B13

6B13
6B12
6B11

6A11
6A12
6A13
M5-512 M5-512

7A8
7A7
7A4
7A3
7A2

7B0
7B1
7B2
7B3
7B4
7B5
7B6
7B7

7B8

6B8

6B7
6B6
6B5
6B4
6B3
6B2
6B1
6B0

6A2
6A3
6A4
6A7
6A8
M5LV-512 M5LV-512

I/O159
I/O158
I/O157
I/O156
I/O155
I/O154
I/O153
I/O152

I/O151
I/O150
I/O149
I/O148
I/O147
I/O146
I/O145
I/O144

I/O143
I/O142
I/O141
I/O140

I/O139
I/O138
I/O137
I/O136

I/O135
I/O134
I/O133
I/O132
I/O131
I/O130
I/O129
I/O128

I/O127
I/O126
I/O125
I/O124
I/O123
I/O122
I/O121
I/O120
GND

GND

GND
GND

GND

GND
VCC

VCC

VCC
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
TDI 1 156 TDO
0A2 0A2 0A2 I/O0 2 155 I/O119 5A2 4A2 3A2
0A3 0A3 0A3 I/O1 3 154 I/O118 5A3 4A3 3A3
0A4 0A4 0A4 I/O2 4 153 I/O117 5A4 4A4 3A4
0A7 0A7 0A7 I/O3 5 152 I/O116 5A7 4A7 3A7
0A8 0A8 0A8 I/O4 6 151 I/O115 5A8 4A8 3A8
0A11 0A11 0A11 I/O5 7 150 I/O114 5A11 4A11 3A11
0A12 0A12 0A12 I/O6 8 149 I/O113 5A12 4A12 3A12
0A13 0A13 0A13 I/O7 9 148 I/O112 5A13 4A13 3A13
VCC 10 147 VCC
GND 11 146 GND
0D15 0D15 0D15 I/O8 12 145 I/O111 5D15 4D15 3D15
0D14 0D14 0D14 I/O9 13 144 I/O110 5D14 4D14 3D14
0D13 0D13 0D13 I/O10 14 143 I/O109 5D13 4D13 3D13
0D12 0D12 0D12 I/O11 15 142 I/O108 5D12 4D12 3D12
0D11 0D11 0D11 I/O12 16 141 I/O107 5D11 4D11 3D11
0D10 0D10 0D10 I/O13 17 140 I/O106 5D10 4D10 3D10
0D9 0D9 0D9 I/O14 18 139 I/O105 5D9 4D9 3D9
0D8 0D8 0D8 I/O15 19 138 I/O104 5D8 4D8 3D8
GND 20 137 GND
0D7 0D7 0D7 I/O16 21 136 I/O103 5D7 4D7 3D7
0D4 0D4 0D4 I/O17 22 135 I/O102 5D4 4D4 3D4
0D3 0D3 0D3 I/O18 23 134 I/O101 5D3 4D3 3D3
0D2 0D2 0D2 I/O19 24 133 I/O100 5D2 4D2 3D2
I0/CLK0 25 132 I3/CLK3
VCC 26 131 GND
GND 27 130 VCC
I1/CLK1 28 129 I2/CLK2
1D2 1D2 1D2 I/O20 29 128 I/O99 4D2 3D2 2D2
1D3 1D3 1D3 I/O21 30 127 I/O98 4D3 3D3 2D3
1D4 1D4 1D4 I/O22 31 126 I/O97 4D4 3D4 2D4
1D7 1D7 1D7 I/O23 32 125 I/O96 4D7 3D7 2D7
GND 33 124 GND
1D8 1D8 1D8 I/O24 34 123 I/O95 4D8 3D8 2D8
1D9 1D9 1D9 I/O25 35 122 I/O94 4D9 3D9 2D9
1D10 1D10 1D10 I/O26 36 121 I/O93 4D10 3D10 2D10
1D11 1D11 1D11 I/O27 37 120 I/O92 4D11 3D11 2D11
1D12 1D12 1D12 I/O28 38 119 I/O91 4D12 3D12 2D12
1D13 1D13 1D13 I/O29 39 118 I/O90 4D13 3D13 2D13
1D14 1D14 1D14 I/O30 40 117 I/O89 4D14 3D14 2D14
1D15 1D15 1D15 I/O31 41 116 I/O88 4D15 3D15 2D15
GND 42 115 GND
VCC 43 114 VCC
1A15 1A13 1A13 I/O32 44 113 I/O87 4A13 3A13 2A15
1A14 1A12 1A12 I/O33 45 112 I/O86 4A12 3A12 2A14
1A13 1A11 1A11 I/O34 46 111 I/O85 4A11 3A11 2A13
1A12 1A8 1A8 I/O35 47 110 I/O84 4A8 3A8 2A12
1A11 1A7 1A7 I/O36 48 109 I/O83 4A7 3A7 2A11
1A10 1A4 1A4 I/O37 49 108 I/O82 4A4 3A4 2A10
1A9 1A3 1A3 I/O38 50 107 I/O81 4A3 3A3 2A9
1A8 1A2 1A2 I/O39 51 106 I/O80 4A2 3A2 2A8
TCK 52 105 TMS
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
GND
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
GND
VCC
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
GND
I/O56
I/O57
I/O58
I/O59
VCC
GND
GND
VCC
I/O60
I/O61
I/O62
I/O63
GND
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
VCC
GND
I/O72
I/O73
I/O74
I/O75
I/O76
I/O77
I/O78
I/O79
GND

M5-512 M5-512
2A13
2A12
2A11
2A8
2A7
2A4
2A3
2A2

2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7

2B8
2B11
2B12
2B13

3B13
3B12
3B11
3B8

3B7
3B6
3B5
3B4
3B3
3B2
3B1
3B0

3A2
3A3
3A4
3A7
3A8
3A11
3A12
3A13

M5LV-512 M5LV-512
1B2
1B3
1B4
1B7
1B8
1B11
1B12
1B13

2A15
2A14
2A13
2A12
2A11
2A10
2A9
2A8

2A7
2A4
2A3
2A2

2B2
2B3
2B4
2B7

2B8
2B9
2B10
2B11
2B12
2B13
2B14
2B15

3B13
3B12
3B11
3B8
3B7
3B4
3B3
3B2

M5-384 M5-384
M5LV-384 M5LV-384
1A7
1A6
1A5
1A4
1A3
1A2
1A1
1A0

1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7

1B8
1B11
1B12
1B13

2B13
2B12
2B11
2B8

2B7
2B6
2B5
2B4
2B3
2B2
2B1
2B0

2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7

M5-320 M5-320
M5LV-320 M5LV-320

20446G-024

Pin Designations
CLK = Clock VCC = Supply Voltage 7 D 15
GND = Ground TDI = Test Data In
I = Input TCK = Test Clock Macrocell (0-15)
I/O = Input/Output TMS = Test Mode Select PAL Block (A-D)
NC = No Connect TDO = Test Data Out Segment (0-7)

36 MACH 5 Family
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A GND I/O11 GND I/O44 I/O58 GND I/O70 I/O76 GND GND GND GND I/O108 I/O116 GND I/O128 I/O134 GND GND GND A

B GND I/O12 I/O28 I/O45 I/O59 I/O64 I/O71 I/O77 I/O84 I/O90 I/O96 I/O102 I/O109 I/O117 I/O122 I/O129 I/O135 I/O148 I/O164 GND B

C I/O0 I/O13 VCC I/O46 I/O60 I/O65 I/O72 I/O78 I/O85 I/O91 I/O97 I/O103 I/O110 I/O118 I/O123 I/O130 I/O136 VCC I/O165 I/O181 C

D I/O1 I/O14 I/O29 VCC VCC I/O66 VCC I/O79 I/O86 I/O92 I/O98 I/O104 I/O111 VCC I/O124 VCC VCC I/O149 I/O166 I/O182 D
Bottom View (I/O Pin-outs)

E I/O2 I/O15 I/O30 TDI TDO I/O150 I/O167 I/O183 E

I
GND I/O16 I/O31 I/O47 I/O137 I/O151 I/O168 GND

NC
F F

I/O

VCC
TDI
CLK

TMS
TCK

TDO
GND
G I/O3 I/O17 I/O32 VCC VCC I/O152 I/O169 I/O184 G

=
=
=
=
=
=
=
=
=
H GND I/O18 I/O33 I/O48 = I/O138 I/O153 I/O170 GND H

Input
J I/O4 I/O19 I/O34 I/O49 I/O139 I/O154 I/O171 I/O185 J
Clock
Pin Designations

Ground

K GND IO/CLK0 I/O35 I/O50 I/O140 I/O155 I3/CLK3 I/O186 K

Test Clock
No Connect

Test Data In
Input/Output
I1/CLK1 I2/CLK2

Test Data Out

L I/O5 I/O36 I/O51 I/O141 I/O156 GND L
Supply Voltage

Test Mode Select

256-Ball BGA

M I/O6 I/O20 I/O37 I/O52 I/O142 I/O157 I/O172 I/O187 M

MACH 5 Family
N GND I/O21 I/O38 I/O53 I/O143 I/O158 I/O173 GND N

P I/O7 I/O22 I/O39 VCC VCC I/O159 I/O174 I/O188 P

256-BALL BGA CONNECTION DIAGRAM — M5-320

R GND I/O23 I/O40 I/O54 I/O144 I/O160 I/O175 GND R

T I/O8 I/O24 I/O41 TCK TMS I/O161 I/O176 I/O189 T

U I/O9 I/O25 I/O42 VCC VCC I/O67 VCC I/O80 I/O87 I/O93 I/O99 I/O105 I/O112 VCC I/O125 VCC VCC I/O162 I/O177 I/O190 U

V I/O10 I/O26 VCC I/O55 I/O61 I/O68 I/O73 I/O81 I/O88 I/O94 I/O100 I/O106 I/O113 I/O119 I/O126 I/O131 I/O145 VCC I/O178 I/O191 V

W GND I/O27 I/O43 I/O56 I/O62 I/O69 I/O74 I/O82 I/O89 I/O95 I/O101 I/O107 I/O114 I/O120 I/O127 I/O132 I/O146 I/O163 I/O179 GND W

Y GND GND GND I/O57 I/O63 GND I/O75 I/O83 GND GND GND GND I/O115 I/O121 GND I/O133 I/O147 GND I/O180 GND Y

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

37
20446G-026
38
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A GND 0B2 GND 0B13 4A14 GND 4A8 4A4 GND GND GND GND 4B4 4B8 GND 4B14 3B13 GND GND GND A

B GND 0A3 0B8 0B11 4A15 4A11 4A10 4A6 4A3 4A0 4B0 4B3 4B6 4B10 4B11 4B15 3B11 3B8 3B2 GND B

C 0D15 0A8 VCC 0B3 0B4 0B12 4A13 4A9 4A5 4A1 4B1 4B5 4B9 4B13 3B12 3B4 3B3 VCC 3A3 3A11 C

D 0D13 0A11 0A2 VCC VCC 0B7 VCC 4A12 4A7 4A2 4B2 4B7 4B12 VCC 3B7 VCC VCC 3A2 3A8 3D15 D

E 0D10 0A13 0A4 TDI TDO 3A4 3A13 3D12 E

4
F GND 0D12 0A12 0A7 3A7 3A12 3D13 GND F

NC
I/O

VCC
TDI
CLK

TMS
TCK

TDO
GND
G 0D7 0D8 0D14 3D14 3D9 3D7 G
Bottom View (Macrocell Association)

VCC VCC

D
=
=
=
=
=
=
=
=
=
=

H GND 0D4 0D9 0D11 3D11 3D10 3D8 GND H

15
J 0D2 0D3 0D5 0D6 3D6 3D5 3D4 3D3 J
Input
Clock
Pin Designations

Ground

K GND IO/CLK0 0D0 0D1 3D1 3D0 I3/CLK3 3D2 K

Test Clock
No Connect

Test Data In
Input/Output

L 1D2 I1/CLK1 1D0 1D1 2D1 2D0 I2/CLK2 GND L

256-Ball BGA

Test Data Out

Supply Voltage

MACH 5 Family
Test Mode Select
M 1D3 1D4 1D5 1D6 2D6 2D5 2D3 2D2 M

N GND 1D8 1D10 1D11 2D11 2D9 2D4 GND N

Segment (0-4)
256-BALL BGA CONNECTION DIAGRAM — M5-320

P 1D7 1D9 1D14 2D14 2D8 2D7 P

Macrocell (0-15)
VCC VCC

PAL Block (A-D)

R GND 1D13 1A14 1A11 2A11 2A14 2D12 GND R

T 1D12 1A15 1A10 TCK TMS 2A10 2A15 2D10 T

U 1D15 1A12 1A8 VCC VCC 1A4 VCC 1B3 1B8 1B13 2B13 2B8 2B3 VCC 2A4 VCC VCC 2A8 2A13 2D13 U

V 1A13 1A9 VCC 1A6 1A5 1A1 1B2 1B6 1B10 1B14 2B14 2B10 2B6 2B2 2A1 2A5 2A6 VCC 2A12 2D15 V

W GND 1A7 1A3 1A2 1B0 1B4 1B5 1B9 1B12 1B15 2B15 2B12 2B9 2B5 2B4 2B0 2A2 2A3 2A9 GND W

Y GND GND GND 1A0 1B1 GND 1B7 1B11 GND GND GND GND 2B11 2B7 GND 2B1 2A0 GND 2A7 GND Y

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

20446G-029
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A NC GND NC I/O51 GND I/O73 I/O80 I/O87 GND I/O101 NC I/O114 GND I/O128 I/O134 I/O142 GND I/O156 I/O162 GND NC GND NC GND NC NC A

B NC GND NC I/O52 I/O68 I/O74 I/O81 I/O88 I/O95 I/O102 I/O107 I/O115 I/O122 I/O129 I/O135 I/O143 I/O150 I/O157 I/O163 I/O169 I/O176 I/O183 I/O188 GND NC NC B

C GND I/O11 TDI I/O53 I/O69 I/O75 I/O82 I/O89 I/O96 I/O103 I/O108 I/O116 I/O123 I/O130 I/O136 I/O144 I/O151 I/O158 I/O164 I/O170 I/O177 I/O184 NC NC NC NC C

D I/O0 I/O12 I/O32 VCC I/O70 I/O76 I/O83 I/O90 VCC I/O104 I/O109 I/O117 VCC I/O131 I/O137 I/O145 VCC I/O159 I/O165 I/O171 I/O178 VCC TDO I/O205 I/O224 GND D

E NC I/O13 I/O33 I/O54 I/O189 I/O206 I/O225 NC E

F GND I/O14 I/O34 I/O55 I/O190 I/O207 I/O226 I/O245 F

G I/O1 I/O15 I/O35 VCC I/O191 I/O208 I/O227 GND G

Bottom View (I/O Pin-outs)

H I/O2 I/O16 I/O36 I/O56 VCC I/O209 I/O228 I/O246 H

J GND I/O17 I/O37 VCC I/O192 I/O210 I/O229 I/O247 J

K I/O3 I/O18 I/O38 I/O57 VCC I/O211 I/O230 GND K

NC
I/O

VCC
TDI
CLK
I/O4 I/O19 I/O39 I/O58 I/O193 I/O212 I/O231 I/O248

TMS
TCK
L L

TDO
GND

=
=
=
=
=
=
=
=
=
=
M I/O5 I/O20 I/O40 I/O59 I/O194 I/O213 I/O232 I/O249 M

N GND I/O21 I0/CLK0 VCC I/O195 I/O214 I/O233 I3/CLK3 N

Input
Clock
Pin Designations

P I1/CLK1 I/O22 I/O41 I/O60 VCC I2CLK2 I/O234 GND P

Ground
352-Ball BGA

Test Clock
R I/O6 I/O23 I/O42 I/O61 I/O196 I/O215 I/O235 I/O250 R

MACH 5 Family
No Connect

Test Data In
Input/Output

Test Data Out

Supply Voltage
T I/O7 I/O24 I/O43 I/O62 I/O197 I/O216 I/O236 I/O251 T

Test Mode Select

U GND I/O25 I/O44 VCC I/O198 I/O217 I/O237 I/O252 U

V I/O8 I/O26 I/O45 I/O63 VCC I/O218 I/O238 GND V

W I/O9 I/O27 I/O46 VCC I/O199 I/O219 I/O239 I/O253 W

Y GND I/O28 I/O47 I/O64 VCC I/O220 I/O240 I/O254 Y

AA I/O10 I/O29 I/O48 I/O65 I/O200 I/O221 I/O241 GND AA

352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512

20446G-030
AB NC I/O30 I/O49 I/O66 I/O201 I/O222 I/O242 NC AB

AC GND I/O31 I/O50 TCK VCC I/O77 I/O84 I/O91 I/O97 VCC I/O110 I/O118 I/O124 VCC I/O138 I/O146 I/O152 VCC I/O166 I/O172 I/O179 I/O185 VCC I/O223 I/O243 I/O255 AC

AD NC NC NC NC I/O71 I/O78 I/O85 I/O92 I/O98 I/O105 I/O111 I/O119 I/O125 I/O132 I/O139 I/O147 I/O153 I/O160 I/O167 I/O173 I/O180 I/O186 I/O202 TMS I/O244 GND AD

AE NC NC GND I/O67 I/O72 I/O79 I/O86 I/O93 I/O99 I/O106 I/O112 I/O120 I/O126 I/O133 I/O140 I/O148 I/O154 I/O161 I/O168 I/O174 I/O181 I/O187 I/O203 NC GND NC AE

AF NC NC GND NC GND NC GND I/O94 I/O100 GND I/O113 I/O121 I/O127 GND I/O141 I/O149 I/O155 GND NC I/O175 I/O182 GND I/O204 NC GND NC AF

39
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
40
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A NC GND NC 7A10 GND 7A5 7A0 7B1 GND 7B7 NC 7B14 GND 6B14 6B10 6B6 GND 6B1 6A1 GND NC GND NC GND NC NC A

B NC GND NC 7A13 7A9 7A6 7A2 7B0 7B3 7B6 7B10 7B13 7B15 6B13 6B9 6B5 6B2 6A0 6A4 6A6 6A9 6A12 6A14 GND NC NC B

C GND 0A1 TDI 7A14 7A11 7A7 7A3 7A1 7B2 7B5 7B9 7B12 6B15 6B12 6B8 6B4 6B0 6A2 6A5 6A8 6A10 6A13 NC NC NC NC C

D 0A6 0A3 0A2 VCC 7A15 7A12 7A8 7A4 VCC 7B4 7B8 7B11 VCC 6B11 6B7 6B3 VCC 6A3 6A7 6A11 6A15 VCC TDO 5A1 5A2 GND D

E NC 0A8 0A5 0A0 5A0 5A4 5A5 NC E

F GND 0A9 0A7 0A4 5A3 5A7 5A9 5A12 F

G 0A13 0A12 0A10 VCC 5A6 5A8 5A14 GND G

H 0D15 0A15 0A14 0A11 VCC 5A10 5A15 5D15 H

I
J GND 0D13 0D14 VCC 5A11 5A13 5D13 5D11 J

7
NC
I/O

VCC
TDI
CLK

TMS
TCK

TDO
GND
K 0D9 0D10 0D11 0D12 VCC 5D14 5D10 GND K

D
=
=
=
=
=
=
=
=
=
=
Bottom View (Macrocell Association)

L 0D5 0D6 0D7 0D8 5D12 5D9 5D8 5D6 L

15
M 0D1 0D2 0D4 0D3 5D7 5D5 5D4 5D3 M
Input
Clock
Pin Designations

Ground

N GND 0D0 I0/CLK0 VCC 5D2 5D1 5D0 I3/CLK3 N

Test Clock
No Connect

Test Data In
P I1/CLK1 1D0 1D1 1D2 VCC I2/CLK2 4D0 GND P
Input/Output

Test Data Out

Supply Voltage
352-Ball BGA

Test Mode Select

R 1D3 1D4 1D5 1D7 4D3 4D4 4D2 4D1 R

MACH 5 Family
T 1D6 1D8 1D9 1D12 4D8 4D7 4D6 4D5 T

Segment (0-7)
U GND 1D10 1D14 VCC 4D12 4D11 4D10 4D9 U

Macrocell (0-15)
PAL Block (A-D)
V 1D11 1D13 1A13 1A11 VCC 4D14 4D13 GND V

W 1D15 1A15 1A10 VCC 4A11 4A14 4A15 4D15 W

Y GND 1A14 1A8 1A6 VCC 4A10 4A12 4A13 Y

AA 1A12 1A9 1A7 1A3 4A4 4A7 4A9 GND AA

352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512

AB NC 1A5 1A4 1A0 4A0 4A5 4A8 NC AB

20446G-031
AC GND 1A2 1A1 TCK VCC 2A15 2A11 2A7 2A3 VCC 2B3 2B7 2B11 VCC 3B11 3B7 3B3 VCC 3A2 3A6 3A10 3A14 VCC 4A2 4A3 4A6 AC

AD NC NC NC NC 2A13 2A10 2A8 2A5 2A2 2B0 2B4 2B8 2B12 2B15 3B12 3B8 3B4 3B1 3A1 3A4 3A8 3A11 3A15 TMS 4A1 GND AD

AE NC NC GND 2A14 2A12 2A9 2A6 2A4 2A0 2B2 2B5 2B9 2B13 3B15 3B13 3B9 3B5 3B2 3B0 3A3 3A7 3A9 3A13 NC GND NC AE

AF NC NC GND NC GND NC GND 2A1 2B1 GND 2B6 2B10 2B14 GND 3B14 3B10 3B6 GND NC 3A0 3A5 GND 3A12 NC GND NC AF

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
5V M5 ORDERING INFORMATION1,2
Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
.
M5- 512 /256 -7 SA C

PROGRAMMING DESIGNATOR
FAMILY TYPE
Blank = Initial Algorithm
M5- = MACH 5 (5-V VCC)
/1 = First Revision

MACROCELL DENSITY OPERATING CONDITIONS

128 = 128 Macrocells C = Commercial (0°C to +70°C)
192 = 192 Macrocells I = Industrial (-40°C to +85°C)
256 = 256 Macrocells
PACKAGE TYPE
320 = 320 Macrocells
Y = Plastic Quad Flat Pack (PQFP)
384 = 384 Macrocells
V = Thin Quad Flat Pack (TQFP)
512 = 512 Macrocells
SA = Ball Grid Array (BGA)
I/Os
/68 = 68 I/Os in 100-pin PQFP or TQFP
/104 = 104 I/Os in 144-pin PQFP or TQFP
/120 = 120 I/Os in 160-pin PQFP SPEED
/160 = 160 I/Os in 208-pin PQFP -5 = 5.5 ns tPD
/192 = 192 I/Os in 256-ball BGA -6 = 6.5 ns tPD
/256 = 256 I/Os in 352-ball BGA -7 = 7.5 ns tPD
-10 = 10 ns tPD
-12 = 12 ns tPD
Note: -15 = 15 ns tPD
1. See below for valid device/package combinations. -20 = 20 ns tPD
2. M5-128/1, M5-192/1 and M5-256/1 recommended for new designs.
.

Valid Combinations Valid Combinations

M5-128/68 YC, VC, YI, VI M5-320/160 YC, YI
Commercial:
M5-128/104 YC, YI M5-320/192 SAC, SAI,
-6, -7, -10, -12, -15
M5-128/120 Commercial: YC, YI M5-384/160 YC, YI
Industrial:
M5-192/68 -5, -7, -10, -12, -15 VC, VI M5-512/160 YC, YI
-7, -10, -12, -15, -20
M5-192/120 Industrial: YC, YI M5-512/256 SAC, SAI
M5-256/68 -7, -10, -12, -15, -20 VC, VI
Valid Combinations
M5-256/120 YC, YI
Valid Combinations list configurations planned to be
M5-256/160 YC, YI supported in volume for this device. Consult the local Lattice
sales of fice to confir m availability of specific valid
Device Marking combinations and to check on newly released combinations.
Actual device marking differs from the ordering part number
(OPN). All MACH devices are dual-marked with both
Commercial and Industrial grades. The Industrial grade is
slower, i.e., M5-512/256-7AC-10AI.

MACH 5 Family 41
3.3V M5LV ORDERING INFORMATION1
Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.

M5LV- 512 /256 -7 SA C

FAMILY TYPE OPERATING CONDITIONS

M5LV- = MACH 5 Low Voltage (3.3-V VCC) C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)

MACROCELL DENSITY PACKAGE TYPE

128 = 128 Macrocells Y = Plastic Quad Flat Pack (PQFP)
256 = 256 Macrocells V = Thin Quad Flat Pack (TQFP)
320 = 320 Macrocells SA = Ball Grid Array (BGA)
384 = 384 Macrocells
512 = 512 Macrocells

I/Os
/68 = 68 I/Os in 100-pin PQFP or TQFP SPEED
/74 = 74 I/Os in 100-pin TQFP -5 = 5.5 ns tPD
/104 = 104 I/Os in 144-pin PQFP or TQFP -6 = 6.5 ns tPD
/120 = 120 I/Os in 160-pin PQFP -7 = 7.5 ns tPD
/160 = 160 I/Os in 208-pin PQFP -10 = 10 ns tPD
/256 = 256 I/Os in 352-ball BGA -12 = 12 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
Note:
1. See below for valid device/package combinations.

Valid Combinations Valid Combinations

M5LV-128/68 VC, VI M5LV-320/120 YC, YI
M5LV-128/74 VC, VI M5LV-320/160 Commercial: YC, YI
M5LV-128/104 VC, VI M5LV-384/120 -6, -7, -10, -12, -15 YC, YI
Commercial:
M5LV-128/120 -5, -7, -10, -12 YC, YI M5LV-384/160 YC, YI
Industrial:
M5LV-256/68 YC, YI M5LV-512/120 YC, YI
-10, -12, -15, -20
M5LV-256/74 Industrial: VC, VI M5LV-512/160 YC, YI
M5LV-256/104 -7, -10, -12, -15 VC, VI M5LV-512/256 SAC, SAI
M5LV-256/120 YC, YI
Valid Combinations
M5LV-256/160 YC, YI
Valid Combinations list configurations planned to be
Device Marking supported in volume for this device. Consult the local Lattice
sales of fice to confir m availability of specific valid
Actual device marking differs from the ordering part number combinations and to check on newly released combinations.
(OPN). All MACH devices are dual-marked with both
Commercial and Industrial grades. The Industrial grade is
slower, i.e., M5LV-512/256-7AC-10AI.

42 MACH 5 Family

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