Central Processing Unit 1

Central Processing Unit

 Introduction

 General Register Organization

 Stack Organization

 Instruction Formats

 Addressing Modes

 Data Transfer and Manipulation

 Program Control and Program Interrupt

 Reduced Instruction Set Computer

Central Processing Unit 2

Major Components of CPU

• Storage Components
Registers
Flags

• Execution (Processing) Components

Arithmetic Logic Unit(ALU)
Arithmetic calculations, Logical computations, Shifts/Rotates

• Transfer Components
Bus

• Control Components
Control Unit
Central Processing Unit 3

Register

In Basic Computer, there is only one general purpose register, the
Accumulator (AC)

In modern CPUs, there are many general purpose registers

It is advantageous to have many registers

•Transfer between registers within the processor are relatively fast

•Going “off the processor” to access memory is much slower

Important:
How many registers will be the best ?
Central Processing Unit 4

General Register Organization

Clock Input

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8 A bus B bus
decoder

SELD
OPR ALU

Output
Central Processing Unit 5

Operation of ControlUnit
The control unit
Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1  R2 + R3
[1] MUX A selector (SELA): BUS A  R2
[2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1  Out Bus
3 3 3 5
Control Word SELA SELB SELD OPR

Binary
Encoding of register selection fields Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
Central Processing Unit 6

ALU Control
Encoding of ALU operations OPR
Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

Examples of ALU Microoperations

Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1  R2  R3 R2 R3 R1 SUB 010 011 001 00101
R4  R4  R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 - R7 TSFA 001 000 111 00000
Output  R2 R2 - None TSFA 010 000 000 00000
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 - R4 SHLA 100 000 100 11000
R5  0 R5 R5 R5 XOR 101 101 101 01100
Central Processing Unit 7

Stack Organization

Stack
 Very useful feature for nested subroutines, nested interrupt services
 Also efficient for arithmetic expression evaluation
 Storage which can be accessed in LIFO
 Pointer: SP
 Only PUSH and POP operations are applicable

Stack Organization
Register Stack Organization
Memory Stack Organization
Central Processing Unit 8

Register Stack Organization

63
Flags
FULL EMPTY

Stack pointer 4
SP C 3
6 bits B 2
A 1
Push, Pop operations 0
DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */

PUSH POP
SP SP + 1 DR M[SP]
M[SP] DR SP SP  1
If (SP = 0) then (FULL 1) If (SP = 0) then (EMPTY 1)
EMPTY 0 FULL 0
Central Processing Unit 9

Memory Stack Organization

1000
Memory with Program, Data, Program
PC (instructions)
and Stack Segments
Data
AR (operands)

SP 3000
stack
3997
3998
3999
4000
4001
- A portion of memory is used as a stack with a
processor register as a stack pointer

- PUSH: SP  SP - 1
M[SP]  DR
- POP: DR  M[SP]
SP  SP + 1
- Most computers do not provide hardware to check stack overflow (full
stack) or underflow (empty stack)  must be done in software
Central Processing Unit 10

Reverse Polish Notation

• Arithmetic Expressions: A + B
A+B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack
manipulation
• Evaluation of Arithmetic Expressions
Any arithmetic expression can be expressed in parenthesis-free Polish notation,
including reverse Polish notation

(3 * 4) + (5 * 6)  34*56*+

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +
Central Processing Unit 11

Processor Organization
• In general, most processors are organized in one of 3 ways

– Single register (Accumulator) organization

• Basic Computer is a good example
• Accumulator is the only general purpose register

– General register organization

• Used by most modern computer processors
• Any of the registers can be used as the source or destination for
computer operations

– Stack organization
• All operations are done using the hardware stack
• For example, an OR instruction will pop the two top elements from the
stack, do a logical OR on them, and push the result on the stack
Central Processing Unit 12

Instruction Format
• Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor register(s)
Mode field - determines how the address field is to be interpreted (to
get effective address or the operand)
•The number of address fields in the instruction format depends on the
internal organization of CPU
•The three most common CPU organizations:
Single accumulator organization:
ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */ TOS: Top Of Stack
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
ADD
Central Processing Unit 13

Zero Address Instruction

• Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D)*/
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */
Central Processing Unit 14

One Address Instruction

• One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :

LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
Central Processing Unit 15

Three & Two Address Instruction

•Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

•Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1  M[A] */

ADD R1, B /* R1  R1 + M[B] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
Central Processing Unit 16

Addressing Mode
Addressing Modes
- Specifies a rule for interpreting or modifying the address field of the
instruction (before the operand is actually referenced)
-Variety of addressing modes
- to give programming flexibility to the user
- to use the bits in the address field of the instruction efficiently
1. Implied Mode
- Address of the operands are specified implicitly in the definition of the
instruction
- No need to specify address in the instruction
- EA = AC
- Examples from Basic Computer - CLA, CME, INP
2. Immediate Mode
- Instead of specifying the address of the operand, operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
Central Processing Unit 17

Addressing Mode

3. Register Mode
- Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing

4. Register Indirect Mode

- Instruction specifies a register which contains the memory address of the
operand
- Saving instruction bits since register address is shorter than the memory address
- Slower to acquire an operand than both the register addressing or memory
addressing

5. Autoincrement or Autodecrement Mode

- When the address in the register is used to access memory, the value in the
register is incremented or decremented by 1 automatically
Central Processing Unit 18

Addressing Mode
6. Direct Address Mode

- Instruction specifies the memory address which can be used directly to access
the memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a large physical memory space

7. Indirect Addressing Mode

- The address field of an instruction specifies the address of a memory location that
contains the address of the operand
-When the abbreviated address is used large physical memory can be addressed
with a relatively small number of bits
- Slow to acquire an operand because of an additional memory access
Central Processing Unit 19

Addressing Mode
8. Relative Addressing Modes
- The Address fields of an instruction specifies the part of the address (abbreviated
address) which can be used along with a designated register to calculate the
address of the operand
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of address bits
- EA = f(IR(address), R), R is sometimes implied

-3 different Relative Addressing Modes depending on R;

PC Relative Addressing Mode (R = PC)

- EA = PC + IR(address)
Indexed Addressing Mode (R = IX, where IX: Index Register)
- EA = IX + IR(address)
Base Register Addressing Mode
(R = BAR, where BAR: Base Address Register)
- EA = BAR + IR(address)
Central Processing Unit 20

Addressing Mode - Example

Address Memory
200 Load to AC Mode
PC = 200 201
Address = 500
202 Next instruction
R1 = 400

399 450
XR = 100
400 700

AC
500 800

600 900

Addressing Effective Content 702 325

Mode Address of AC
Immediate operand 201 /* AC  500 */ 500
Direct address 500 /* AC  (500) */ 800 800 300
Indirect address 800 /* AC  ((500)) */ 300
Relative address 702 /* AC  (PC+500) */ 325
Indexed address 600 /* AC  (XR+500) */ 900
Register - /* AC  R1 */ 400
Register indirect 400 /* AC  (R1) */ 700
Autoincrement 400 /* AC  (R1)+ */ 700
Autodecrement 399 /* AC  -(R) */ 450
 DATA TRANSFER INSTRUCTIONS
Typical Data Transfer Instructions
Name Mnemonic
Load LD Transfer from memory to accumulator
Store ST Transfer from accumulator into memory
Move MOV Transfer from one CPU register to another, CPU register to memory, two memory words
Exchange XCH Swaps information between two registers or a register and memory word
Input IN Transfer data among processor register and I/O terminals
Output OUT Transfer data among processor register and I/O terminals
Push PUSH Transfer data among processor register and a memory stack
Pop POP Transfer data among processor register and a memory stack

Data Transfer Instructions with Different Addressing Modes

Assembly
Mode Convention Register Transfer
Direct address LD ADR AC M[ADR]
Assembly Language Convention
Indirect address LD @ADR AC  M[M[ADR]] ADR = Address
Relative address LD $ADR AC  M[PC + ADR] NBR = Number or Operand
Immediate operand LD #NBR AC  NBR X = index register
Index addressing LD ADR(X) AC  M[ADR + XR] R1 = Processor register
Register LD R1 AC  R1 AC = Accumulator
Register indirect LD (R1) AC  M[R1] @ = indirect address
Autoincrement LD (R1)+ AC  M[R1], R1  R1 + 1 $ = address relative to PC
Autodecrement LD -(R1) R1  R1 - 1, AC  M[R1] # = operand in an immediate mode instruction
DATA MANIPULATION INSTRUCTIONS
Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
Arithmetic Instructions
Name Mnemonic
Increment INC ADDI: Add two binary integer numbers
Decrement DEC
Add ADD ADDF: ADDI: Add two floating point numbers
Subtract SUB
Multiply MUL ADDD: ADDI: Add two decimal numbers in BCD
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG

Logical and Bit Manipulation Instructions Shift Instructions

Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interrupt EI
Disable interrupt DI
Instruction code format of shift
instruction
 OP REG TYPE RL COUNT
 OP: operation code field
 REG: register address that specifies location of operand
 TYPE: 2-Bit: specifies four different types of shifts
 RL:1-bit: specify shift right or left
 COUNT: k-bit field specifying upto 2K-1 shifts
Central Processing Unit 24

Program Control Instruction

+1
In-Line Sequencing (Next instruction is fetched from the
next adjacent location in the memory)
PC

Address from other source; Current Instruction, Stack, etc;

Branch, Conditional Branch, Subroutine, etc

• Program Control Instructions

Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RTN
Compare(by  ) CMP
Test(by AND) TST * CMP and TST instructions do not retain their
results of operations (  and AND, resp.).
They only set or clear certain Flags.
Central Processing Unit 25

Flag, Processor Status Word

• In Basic Computer, the processor had several (status) flags – 1 bit value that
indicated various information about the processor’s state – E, FGI, FGO, I,
IEN, R
• In some processors, flags like these are often combined into a register – the
processor status register (PSR); sometimes called a processor status word
(PSW)
• Common flags in PSW are
– C (Carry): Set to 1 if carry out of the ALU is 1 i.e. end carry C8 is 1.
– S (Sign): The MSB bit of the ALU’s output: Set to 1if F7 is 1. Status Flag Circuit
– Z (Zero): Set to 1 if the ALU’s output is all 0’s.
– V (Overflow): Set to 1 if there is an overflow A B
8 8
c7
c8 8-bit ALU
F7 - F0
V Z S C
F7
Check for 8
zero output
F
Central Processing Unit 26

Conditional Branch Instruction

Mnemonic Branch condition Tested condition
BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
Unsigned compare conditions (A - B)
BHI Branch if higher A>B
BHE Branch if higher or equal AB
BLO Branch if lower A<B
BLOE Branch if lower or equal AB
BE Branch if equal A=B
BNE Branch if not equal AB
Signed compare conditions (A - B)
BGT Branch if greater than A>B
BGE Branch if greater or equal AB
BLT Branch if less than A<B
BLE Branch if less or equal AB
BE Branch if equal A=B
BNE Branch if not equal AB
Central Processing Unit 27

Subroutine Call and Return

Call subroutine
• Subroutine Call
Jump to subroutine
Branch to subroutine
Branch and save return address

• Two Most Important Operations are Implied;

* Branch to the beginning of the Subroutine

- Same as the Branch or Conditional Branch

* Save the Return Address to get the address of the location in the Calling Program upon
exit from the Subroutine

• Locations for storing Return Address

• Fixed Location in the subroutine (Memory)

• Fixed Location in memory CALL
• In a processor Register Decrement stack pointer
SP  SP - 1
• In memory stack Push content of PC onto stack
M[SP]  PC
- most efficient way Transfer control to subroutine
PC  EA

RTN
PC  M[SP] Pop stack and transfer to PC
SP  SP + 1 Increment stack pointer
Central Processing Unit 28

Program Interrupt
Types of Interrupts
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device → Data transfer request or Data transfer complete
- Timing Device → Timeout
- Power Failure
- Operator

Internal interrupts (traps)

Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation

Software Interrupts
Both External and Internal Interrupts are initiated by the computer HW.
Software Interrupts are initiated by the executing an instruction.
- Supervisor Call 1. Switching from a user mode to the supervisor mode
2. Allows to execute a certain class of operations
which are not allowed in the user mode
Central Processing Unit 29

Interrupt Procedure

Interrupt Procedure and Subroutine Call

- The interrupt is usually initiated by an internal or an external signal rather than
from the execution of an instruction (except for the software interrupt)

- The address of the interrupt service program is determined by the hardware rather
than from the address field of an instruction

- An interrupt procedure usually stores all the information necessary to define the
state of CPU rather than storing only the PC.

The state of the CPU is determined from:

 Content of the PC
 Content of all processor registers
 Content of status bits
Many ways of saving the CPU state
depending on the CPU architectures
Central Processing Unit 30

RISC – Reduced Instruction Set Computers

• In the late ‘70s and early ‘80s there was a reaction to the shortcomings
of the CISC style of processors
• Reduced Instruction Set Computers (RISC) were proposed as an
alternative
• The underlying idea behind RISC processors is to simplify the
instruction set and reduce instruction execution time

• RISC processors often feature:

– Few instructions
– Few addressing modes
– Only load and store instructions access memory
– All other operations are done using on-processor registers
– Fixed length instructions
– Single cycle execution of instructions
– The control unit is hardwired
Central Processing Unit 31

RISC – Reduced Instruction Set Computers

• Since all but the load and store instructions use only registers for
operands, only a few addressing modes are needed
• By having all instructions the same length, reading them in is easy and
fast
• The fetch and decode stages are simple
• The instruction and address formats are designed to be easy to decode
• Unlike the variable length CISC instructions, the opcode and register
fields of RISC instructions can be decoded simultaneously
• The control logic of a RISC processor is designed to be simple and fast
• The control logic is simple because of the small number of instructions
and the simple addressing modes
Central Processing Unit 32

CISC
Arguments Advanced at that time
• Richer instruction sets would simplify compilers
• Richer instruction sets would alleviate the software crisis
– move as much functions to the hardware as possible
• Richer instruction sets would improve architecture quality

CISC
• These computers with many instructions and addressing modes came
to be known as Complex Instruction Set Computers (CISC)

• One goal for CISC machines was to have a machine language

instruction to match each high-level language statement type
Central Processing Unit 33

Complex Instruction Set Computers

• Another characteristic of CISC computers is that they have instructions

that act directly on memory addresses
– For example,
ADD L1, L2, L3
that takes the contents of M[L1] adds it to the contents of M[L2] and stores the result in
location M[L3]
• An instruction like this takes three memory access cycles to execute
• That makes for a potentially very long instruction execution cycle
• The problems with CISC computers are

– The complexity of the design may slow down the processor,

– The complexity of the design may result in costly errors in the processor design and
implementation,
– Many of the instructions and addressing modes are used rarely, if ever
Central Processing Unit 34

Summary : Criticism On CISC

High Performance General Purpose Instructions

- Complex Instruction
→ Format, Length, Addressing Modes
→ Complicated instruction cycle control due to the complex decoding HW
and decoding process

- Multiple memory cycle instructions

→ Operations on memory data
→ Multiple memory accesses/instruction

- Microprogrammed control is necessity

→ Microprogram control storage takes substantial portion of CPU chip area
→ Semantic Gap is large between machine instruction and microinstruction

- General purpose instruction set includes all the features required by

individually different applications
→ When any one application is running, all the features required by the other
applications are extra burden to the application
NEXT: Additional for reference only
 RISC: REDUCED INSTRUCTION SET
COMPUTERS
Historical Background
IBM System/360, 1964
- The real beginning of modern computer architecture
- Distinction between Architecture and Implementation
- Architecture: The abstract structure of a computer
seen by an assembly-language programmer

Compiler -program
High-Level Instruction
Language Hardware
Set
Architecture Implementation

Continuing growth in semiconductor memory and microprogramming

-> A much richer and complicated instruction sets
=> CISC(Complex Instruction Set Computer)
- Arguments advanced at that time
Richer instruction sets would simplify compilers
Richer instruction sets would alleviate the software crisis
- move as much functions to the hardware as possible
- close Semantic Gap between machine language
and the high-level language
Richer instruction sets would improve the architecture quality
36
COMPLEX INSTRUCTION SET COMPUTERS: CISC

High Performance General Purpose Instructions

Characteristics of CISC:
1. A large number of instructions (from 100-250 usually)
2. Some instructions that performs a certain tasks are not used frequently.
3. Many addressing modes are used (5 to 20)
4. Variable length instruction format.
5. Instructions that manipulate operands in memory.

37
 PHYLOSOPHY OF RISC

Reduce the semantic gap between

machine instruction and microinstruction
1-Cycle instruction
Most of the instructions complete their execution
in 1 CPU clock cycle - like a microoperation
* Functions of the instruction (contrast to CISC)
- Very simple functions
- Very simple instruction format
- Similar to microinstructions
=> No need for microprogrammed control
* Register-Register Instructions
- Avoid memory reference instructions except
Load and Store instructions
- Most of the operands can be found in the
registers instead of main memory
=> Shorter instructions
=> Uniform instruction cycle
=> Requirement of large number of registers
* Employ instruction pipeline
38
 CHARACTERISTICS OF RISC
Common RISC Characteristics
- Operations are register-to-register, with only LOAD and
STORE accessing memory
- The operations and addressing modes are reduced
Instruction formats are simple

39
 CHARACTERISTICS OF RISC
RISC Characteristics
- Relatively few instructions
- Relatively few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction format
- Single-cycle instruction format
- Hardwired rather than microprogrammed control

More RISC Characteristics

-A relatively large numbers of registers in the processor unit.
-Efficient instruction pipeline
-Compiler support: provides efficient translation of high-level language
programs into machine language programs.
Advantages of RISC
- VLSI Realization
- Computing Speed
- Design Costs and Reliability
- High Level Language Support

40