2019 5th International Conference for Convergence in Technology (I2CT)

Pune, India. Mar 29-31, 2019

Error Detection and Correction Capability for

BCH Encoder using VHDL

Shreya D. Potey1, Piyush M. Dhande2

1
PG (M. Tech.) Electronics & Communication
1
Department of Electronics & Telecommunication, D.M.I.E.T.R. Sawangi (Meghe), Wardha, India
1
[email protected]
2
Asst. Professor, Department of Electronics & Telecommunication,
D.M.I.E.T.R. Sawangi (Meghe), Wardha, India
2
[email protected]

Abstract— The BCH code is the essential class of multiple- II. BASIC of BCH CODE
error-correcting linear cyclic code. In actuality, Bose-
Chaudhuri-Hocqunghem code is an abstraction of the cyclic The BCH code is the essential part of the multiple -
hamming code for multiple-error correction. The finding of error-correcting linear cyclic code. In 1959, A.
errors made by noise during transmission from the sender to Hocquenghem and in 1960, R. C. Bose and D. K. Ray-
the recipient is called as Error Detection. The finding of Chaudhari invented Binary codes which are called as BCH
errors and renewal of the original data is called as Error code. An accurate control above the multiple symbol errors
Correction. The error can be detected and corrected for the correctable in the code is a central feature of Bose-
fixed value of n and k. So that, the system efficiency and Chaudhuri-Hocqunghem code. Especially, multiple bit
correcting capability are lower. In this paper, we are errors can be corrected by designing binary Bose-
implementing a system in which we can detect and correct the Chaudhuri-Hocqunghem codes [18]. BCH code depends on
flexible block length and message length. When the input data Galois field arithmetic which includes describing the
is applied to Galois field, the generator matrix H is binary actions over finite collections of an element [5].
performing the XOR operation with bits of the input register Bose-Chaudhuri-Hocqunghem code is the subclass of
and formed the output. cyclic codes. In order to give good error correction
capability, we have to specify the roots of the generator
Keywords— BCH (Bose-Chaudhari-Hocqenghem) code, polynomials. BCH code can identify and overcome the
BCH Encoder, BCH Decoder, VHDL, LFSR, Galois Field, BER error up to ‘t’ arbitrary errors per code words because every
(Bit Error Rate)
BCH code has ‘t’ error correcting code. BCH code has the
following factors:
I. INTRODUCTION Block length: n=2m-1
Number of message bits: k≥ n-mt
Nowadays, the fastest growing area in the field of
communication is Wireless Communication. Whenever the Minimum distance: dmin≥2t+1
communication takes place, the data need to be transmitted
through the sender to the recipient. The error is such a Here ‘n’ is the block length and ‘k’ is the message
situation in which output information is not similar to the length. The above factor can correct the ‘t’ errors or fewer
input information. When digital signals are transmitted error. The generator polynomial of this code is identified in
from sender to the recipient, some errors can introduce in respect of its roots from the Galois field GF(2m) [11].
the signals because of noise interference. That means a 0
bit may change to 1 or vice versa [16]. The significant data A. Galois Field
will be lost because of the data error A field having just a finite number of components is
In a communication system, detecting the error during known as Galois Field. Another name of the Galois field is
the transmission process of data through the sender to the the Finite field. Galois field is a special case of a finite
recipient is called error detection. For the detection of field. This field can perform many operations like addition,
error, we can use some redundancy codes. These subtraction, multiplication, division and satisfy certain
redundancy codes are then added to the data during basic rules.
transmission, such codes are termed as “Error detecting A field in which the number of the elements is the type
codes” [17]. pn. in the pn, ‘p’ refer as prime number and ‘n’ refer as
Error Correction Code is a procedure of put in parity positive integer, is termed as the Galois field, such a field is
bits into real data in order to recover the message by the represented by GF(pn) .
receiver. We need error correcting code for good
conveying message over a noisy way that has an improper B. Encoding of BCH Code
BER as well as SNR is lower. Reed-Solomon codes, Golay BCH code is a subset of cyclic codes, the organized
codes, Cyclic Hamming code, BCH codes, Goppa codes method of encoding is related to the method of binary
are used in error correction code. [5]. The computational coding. For the BCH code, the generating polynomial is:
complexity of Reed-Solomon encoder and decoder is high,
but the complexity of BCH code is low. g(X)= g0+g1X+g2X2+………+g2t-1X2t-1+X2t

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 The number of parity bits is equivalent to the degree of In [12] author has designed a (15, 7) BCH encoder and
generator polynomial. Since the degree 2t is equal to the decoder. By utilizing the algorithms, two errors have been
generator polynomial, there must be precisely 2t successive acknowledged and adjusted in the BCH code which worked
powers of α that is the roots of the polynomial. Message at the single cycle. The result showed the area and delay
polynomial m(X) can be transferred into the leftmost n-k were reduced [12].
stages of a code word register and then tacking on a parity
polynomial p(X) [5]. The author in [1] proposed a new method for
compressing the LUT and reduces the requirement that was
C. LFSR compared to prior design. The throughput of the decoder
The LFSR is used in the innovative digital was greater and the area has been reduced by 19% for
communication scheme and it is similar to all the BCH (1023, 993) BCH code over GF(210) [1].
code design.
The linear function of individual bits is commonly used Sweta Thakur, Tabassum Nasrat and Soumyasree Bera
exclusive-or (XOR). LFSR is a shift register whose input [15] studied the performance of two channel coding
bit is determined through the XOR of some bits. techniques, i.e., BCH and Reed Solomon. Using the
MATLAB software the process of simulation has been
Following is the design operation of Encoder Linear done. Here, compared the BER and the SNR value of the
Feedback Shift Register: BCH and Reed Solomon code, also compared the uncoded
1. For the clock cycle 1 to k, the original message bits are and coded transmission. The result was similar in both
transferred without changing its form, and the linear software and hardware [15].
feedback shift register calculates the parity.
IV. PROBLEM FORMULATION AND PROPOSED
2. For cycle k+1 to n, the generated parity bits in the linear WORK
feedback shift register are transmitted and the feedback in
the LFSR is switch off. In the existing work, BCH and Reed-Solomon encoder
and decoder has been developed. In the current work fixed
block length and message length code are decoded as well
III. LITERATURE REVIEW as the fixed error correcting capability (t) are calculated.
In [6] and [8] paper authors proposed method designed This result showed the improvement in speed and
the BCH encoder on FPGA for (15, k) using an AWGN utilization of the device. Also, channel coding techniques,
channel with the numerous error correcting code. encoding and decoding methods are studied.
Considered (15, 11, 1), (15, 7, 2), and (15, 5, 3) BCH
encoder for error correction according to the highest degree
of a polynomial. Here encoder of (15, 5, 3) was more
beneficial than the remaining, because of the necessity of
speed. When the noise corrupted the original data the BCH
encoder was corrected 3 errors at the receiver side [6], [8].
Sahana C*, V Anandi [2] presented a binary encoding
of (255, 215, 5) for the simulation of encoder also
Syndrome computation. The message bits of 215 were Fig. 1 Block Diagram of the BCH Code
encrypted and any 5-bit error was detected from the 255-bit
code word. LFSR was used for the encoder process and The proposed work is to implement the variable length
Finite field polynomial multiplication was used for the BCH encoder and decoder using VHDL. At the sender
calculation of syndrome [2]. side, the data streams are encrypted by adding some
In [3] the author studied the encoding and the decoding additional bits with message bits called as parity bits. The
process of RS code and the error probability for the Reed- message bits composed with parity bits named as a
Solomon code. For large block length, the error probability ‘Codeword’.
of the RS code showed that the BER operation was
improved and for lower SNR, BER performance was poor
[3].
Samir Jasim Mohammed [10] designed and simulated
BCH encoder codes of (31, 26, 1), (31, 21, 2), (31, 16, 3),
(31, 11, 5) and (31, 6, 7) utilizing Xilinx-ISE 10.1 and
enforced in FPGA. Here, a 31-bit size code word was used
Fig. 2 Block Diagram of BCH Encoder
in this implementation. The (31, k) BCH encoder was
properly examined and compared. The BCH encoder code In our work, the input data is applied to the Galois
(31, 6) occupied a greater area than the other codes. The field. In this, we have a generator polynomial (H) which
results showed the system works well [10]. contains the details of the bits to be XOR for the code. The
In [11] at the time of corrupting the actual data, the given generator polynomial is n*k size, in which we can
binary BCH code (15, 11, 3) and (63, 39, 4) were corrected find out ‘n’ number of results. We have used LFSR
3-bit error and four-error on the output side respectively. architecture for the execution of BCH encoder. For
Here, iterative algorithm was used to identify the location polynomial division, we can use Linear Feedback Shift
of the error. Due to this, the speed and utilization of the Register. Based on this H matrix, we XOR the bits of the
device were improved [11]. input register and produced the output.

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 V. SIMULATION AND RESULTS

The design waveform of BCH encoder is depicted as

below:
Input for fig. 3 is “10101", “01010”, “11010” and
applied to the encoder then we get the result in the form of
following waveform.

Fig. 7: BCH Encoder (18, 9)

VI. CONCLUSION

In a communication system, error detection is the

operation of finding the faults that are present in the data
broadcast from sender to the receiver. To improve the
reliability of the binary transmission system, error
Fig. 3: BCH Encoder (10, 5) Correction Codes are vital. The proposed work is to
implement the variable length BCH encoder and decoder
The input of the BCH encoder (12, 6) is “110101”, using VHDL. When the input data is applied to Galois
“010110”, “110100” and we get the waveform as depicted field, the generator matrix H is performed the XOR
below in fig. 3.
operation with bits of the input register and formed the
output. If we are given n-bits of input to the encoder then
we get doubles of input-bits at the output due to the
generator polynomial. For the further work we are starting
to go through the BCH decoder, then that work may
improve the throughput of the system and the system can
be efficient.

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Fig. 4: BCH Encoder (12, 6)
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