Unit-2

Combinational Logic Design

-Mrs. Radhika V. Kulkarni

Assistant Professor, Dept. of Information Technology,
Pune Institute of Computer Technology, Pune.

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second Edition.
 DISCLAIMER
This presentation is created as a reference material for
the students of SE-IT, PICT (AY 2022-23 Sem-1).
It is restricted only for the internal use and any circulation
is strictly prohibited.

RVK-LDCO-Unit-1 2
 Syllabus
• Design using SSI chips: Code converters, Half- Adder, Full Adder, Half
Subtractor, Full Subtractor, n bit Binary adder.
• Introduction to MSI chips: Multiplexer (IC 74153), Demultiplexer (IC
74138), Decoder (74238) Encoder (IC 74147), Binary adder (IC 7483)
• Design using MSI chips: BCD adder & subtractor using IC 7483,
Implementation of logic functions using IC 74153 & 74138.
• Case Study: Use of combinational logic design in 7 segment display
interface

RVK-LDCO-2.1 3
 Contents
2.1-Combinational SSI Circuits-Adder

2.2-Combinational SSI Circuits-Subtractor

2.1-Combinational MSI Circuits-BCD Adder

2.1-Combinational MSI Circuits-BCD Subtractor

2.5-Combinational MSI Circuits- Multiplexers & Demultiplexers

2.5-Combinational MSI Circuits- Decoders & Encoders

2.7- Combinational MSI Circuits- Code Converters

RVK-LDCO-Unit-1 4
 2.1 Combinational SSI Circuits-
Adder

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third
Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second
Edition.
 Combinational Logic Circuits
• The term "combinational" comes to us from mathematics which
means an unordered set where nobody cares which order the
items came in.

• With combinational logic, the circuit always produces the same

output solely by a given set of inputs , regardless of the order the
inputs are changed.
– If there are m outputs and n inputs then there are m Boolean functions,
one describing each outputs

• A combinational circuit is made of logic gates and it does not

store any information (i.e. memoryless).
– There are circuits which depend on inputs and previous outputs. These
circuits are called sequential logic where we will discuss in later chapter

• Combinational logic circuits are important components of digital

systems.
RVK-LDCO-2.1 6
Combinational vs. Sequential Logic

(a) Combinational (b) Sequential

Output = F (In) Output = F (In, Previous In)

RVK-LDCO-2.1 7
 Designing Combinational Circuits
• In general we have to do following steps:
1. From the specifications of the circuit, determine the required
number of inputs and outputs and assign a letter symbol to
each

2. Derive the truth table that defines the relationship between

inputs and outputs

3. Obtain the simplified Boolean functions for each output as a

function of the input variables

4. Draw the logic diagram

5. Verify the correctness of the design

RVK-LDCO-2.1 8
 Arithmetic Circuits
• Arithmetic circuits are the ones which perform
arithmetic calculations on binary numbers like
addition, subtraction, multiplication, and division etc.

• Arithmetic circuits can be built using logic circuits and

they are excellent examples of combinational logic
design
– Adder, Subtractor etc.
– We will build arithmetic circuits by using the design
procedure as stated previously

RVK-LDCO-2.1 9
 Adder
• Adders are the basic building blocks of all arithmetic circuits.

• Adders add two binary numbers and give out sum and carry as
output.

• In modern computers adders reside in the arithmetic and logic

unit (ALU) where other operations are performed.

• Basically we have two types of adders:

1. Half Adder
2. Full Adder

RVK-LDCO-2.1 10
Half Adder
 Half Adder
• Adding two single-bit binary values, X, Y produces a sum S bit and
a carry out C-out bit.

• This operation is called half addition and the circuit to realize it is

called a half adder.
Half Adder Truth Table S(X,Y) = ∑m(1,2)
Inputs Outputs S = XY + X Y
S = XÅY
X Y S C-out
0 0 0 0 C-out(X,Y) = ∑m(3)
0 1 1 0 C-out = XY
1 0 1 0
X
1 1 0 1 Sum S
Y

RVK-LDCO-2.1
C-out 12
Full Adder
 Full Adder
• Adding two single-bit binary
values, X, Y with a carry input bit
C-in produces a sum bit S and a
carry out C-out bit.C

The S function is the three-bit XOR function

(Odd Function): S = X Å Y Å (C-in)

C-out = XC-in + YC-in+ XY

RVK-LDCO-2.1 14
Full Adder Circuit using XOR and Basic
Gates

• Logical Implementation

RVK-LDCO-2.1 15
 Full Adder implemented by Two Half
Adders and an OR Gate
• A ‘Full Adder’ can also be implemented using two half adders
and an ‘OR’ Gate as follows:
The sum S = X Å Y Å (C-in)
The carry out
C _ out = XY + XC _ in + YC_ in
= XY + C _ in ( X + Y )
= XY + C _ in ( X + Y )( X + X )(Y + Y )
= XY + C _ in ( X + Y )( XY + X Y + X Y + X Y )
= XY + C _ in ( XY + X Y + X Y )
= XY + C _ in XY + C _ in ( X Y + X Y )
= XY (1 + C _ in ) + C _ in ( X Y + X Y )
= XY + C _ in ( X ⊕ Y )

RVK-LDCO-2.1 16
 Full Adder implemented by Two Half Adders and
an OR Gate (Cont.)
• Therefore S = X ⊕ Y ⊕ C _ in and C _ out = XY + C _ in ( X ⊕ Y )
HA1 HA2

X
Y S

C-in
C-out

C-in S2 S

HA2 • Block diagram

X S1 C2
representation of a full
C-out
adder using two half adders
HA1

Y C1
RVK-LDCO-2.1 17
 Adding Two Binary Numbers
• We want to add two 4-bit binary numbers.

• We use a series of half and full adders.

• Since there is no carry into the first stage, we

can use a half adder there.

• For each other stage we use a full adder and

just carry in from the previous stage.

• The carry out at the end indicates that the

sum is too large to be represented by 4 bits
RVK-LDCO-2.1 18
4-bit Parallel Adder IC7483
 Parallel Adder IC
• As shown in the pin layout diagram, the IC 7483
– Accepts two 4-digit numbers A4A3A2A1, B4B3B2B1 and a carry-in Ci as inputs
– Produces a 4-digit sum output S4S3S2S1 and a carry-out Co
– If the SUM of the two inputs plus the carry-in is between 0 and 15, the SUM
appears in the S outputs and the carry-out is '0‘
– If the SUM is between 16 and 31, carry-out C0 becomes ‘1‘ and the S outputs
are 16 less than the SUM.

A4 A3 A2 A1 B4 B3 B2 B1
• Example (not using 2’s complement)
– A4A3A2A1 = 0111, B4B3B2B1 = 1010, Ci = 1 Co 74283 Ci
– So, result should be 10010 =(18)10 S4 S3 S2 S1

– As expected, the ICs produces

Co = 1 and S4S3S2S1 = 0010

RVK-LDCO-2.1 20
 Cascading the 74283 ICs
• A 74283 IC only accept 4-bits Boolean variables at its input.

• So, how to do addition which involve 5-bits or more?

• Find another suitable IC! Or, by cascading 74283 Ics

• To add two 8 bit numbers X8X7X6X5X4X3X2X1 and Y8Y7Y6Y5Y4Y3Y2Y1 ,

connect two 74283 as below

X8 X7 X6 X5 Y8 Y7 Y6 Y5 X4 X3 X2 X1 Y4 Y3 Y2 Y1
A4 A3 A2 A1 B4 B3 B2 B1 A4 A3 A2 A1 B4 B3 B2 B1

Co 74283 Ci Co 74283 Ci
S4 S3 S2 S1 S4 S3 S2 S1

2nd stage RVK-LDCO-2.1

1st stage 21
produce MSB produce LSB
 2.1.1 Look-ahead Carry Adder

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third
Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second
Edition.
 Faster Circuits
• Three ways of improving the speed of circuits:
– Use better technology (eg. ECL faster than TTL gates) but
• Faster technology is more expensive, needs more power, lower-level
of integrations

– Use gate-level designs to two-level circuits! (use sum-of-

products/product-of-sums) but
• Complicated designs for large circuits
• Product/sum terms need MANY inputs!

– Use clever look-ahead techniques but

• There are additional costs (hopefully reasonable).
 Look-ahead Carry Adder
• Consider the FA, where intermediate
signals are labelled as Pi and Gi: Xi Pi
Pi = Xi Å Yi Yi Si
Gi = Xi ·Yi Gi
Ci+1

• The outputs Ci+1, Si, in terms of Pi, Gi and Ci

Ci are:
Si = Pi Å Ci … (1)
Ci+1 = Gi + Pi·Ci … (2)

• Looking at equation (2):

Gi = Xi ·Yi is a carry generator signal, and
Pi = Xi Å Yi is a carry propagator signal.
 Look-ahead Carry Adder(Cont..)
• For 4-bit ripple-carry adder, the equations for the four carry
signals are:
Ci+1 = Gi + Pi·Ci
Ci+2 = Gi+1 + Pi+1·Ci+1
Ci+3 = Gi+2 + Pi+2·Ci+2
Ci+4 = Gi+3 + Pi+3·Ci+3

Ci
n These formulae are Pi
Ci+1
deeply nested, as Gi
shown here for Ci+2:
Pi+1
Ci+2
Gi+1

4-level circuit for Ci+2 = Gi+1 +Pi+1.Ci+1

 LOOK-AHEAD CARRY ADDER (3/6)

• Nested formulae/gates cause more propagation delay.

• Reduce delay by expanding and flattening the formulae for
carries. Example, for Ci+2:
Ci+2 = Gi+1 + Pi+1·Ci+1
= Gi+1 + Pi+1·(Gi + Pi·Ci)
= Gi+1 + Pi+1·Gi + Pi+1·Pi·Ci

• New faster circuit for Ci+2:

Ci
Pi
Pi+
1
Gi Ci+2
Pi+
1
Gi+1
 LOOK-AHEAD CARRY ADDER (4/6)

• Other carry signals can be similarly flattened:

Ci+3 = Gi+2 + Pi+2·Ci+2
= Gi+2 + Pi+2·(Gi+1 + Pi+1·Gi + Pi+1·Pi·Ci)
= Gi+2 + Pi+2·Gi+1 + Pi+2·Pi+1·Gi + Pi+2·Pi+1·Pi·Ci
Ci+4= Gi+3 + Pi+3·Ci+3
= Gi+3 + Pi+3·(Gi+2 + Pi+2·Gi+1 + Pi+2·Pi+1·Gi + Pi+2·Pi+1·Pi·Ci)
= Gi+3 + Pi+3·Gi+2 + Pi+3·Pi+2·Gi+1 + Pi+3·Pi+2·Pi+1·Gi +
Pi+3·Pi+2·Pi+1·Pi·Ci

• Note that formulae gets longer with higher carries.

• Also, all carries are two-level sum-of-products expressions,
in terms of the generate signals Gs, the propagate signals
Ps, and the first carry-in Ci.
 LOOK-AHEAD CARRY ADDER (5/6)

• We employ look-
ahead formula in this
lookahead-carry adder
circuit:
 LOOK-AHEAD CARRY ADDER (6/6)

• The 74182 IC chip

allows faster
lookahead adder to be
built.
• Assuming gate delay is
t, maximum
propagation delay for
circuit is hence 4t
– t to get generate and
propagate signals
– 2t to get the carries
– t for the sum signals
 2.2 Combinational SSI Circuits-
Subtractor

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third
Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second
Edition.
 Subtraction
• If we want to do subtraction, the
circuit is very similar to half adder.
• Looking at the truth table for A – B
the only difference between a half
adder and a half subtractor is the
borrow
• In order to perform this
subtraction a digit has to
be borrowed from the next
highest column of the
subtraction
• When it borrows, it gets a 2
and the operation then
becomes 2 - 1 = 1
• The Borrow output is set to
indicate that borrow
RVK-LDCO-2.2 operation is required 31
 Half Subtractor
• Subtracting a single-bit binary value Y from another X (i.e. X - Y)
produces a difference bit D and a borrow out bit B-out
• This operation is called half subtraction and the circuit to realize it is
called a half subtractor.
D(X,Y) = S (1,2)
D(X,Y) = X'Y + XY'
D = XÅY

B-out(X,Y) = S (1)
B-out = X'Y

Difference
X
D
Y

Symbol
B-out

RVK-LDCO-2.2 32
 Half Subtractor Circuit
• Again, we shall represent the half subtractor using a box.

• Since the two inputs of a subtractor are different, we indicate the

subtrahend with a ‘-’

RVK-LDCO-2.2 33
 Full Subtrator
• Subtracting two single-bit
binary values, Y, B-in from a
single-bit value X produces a
difference bit D and a borrow
out B-out bit.
• This is called full subtraction. D = X Å Y Å (B-in)

B-out = X'Y + X'(B-in) + Y(B-in)

= X'Y + B-in(X Å Y)'
Note: D= X – Y – B-in
(In the same way as we did with the full adder)
D(X,Y, B-in) = S (1,2,4,7)
RVK-LDCO-2.2 34
B-out(X, Y, B-in) = S (1,2,3,7)
 Full Subtractor Circuit Implementation

X-OR gate
implementation Full subtractor using two half
of half subtractor subtractors and an OR gate

HS1 HS2
X
Y X
Y D
B_in Difference (D)

Y
B_out
B_in
X B_out

B_in Text

Y
B_in
RVK-LDCO-2.2 35
 2.3 Combinational MSI
Circuits- BCD Adder

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third
Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second
Edition.
 BCD Adder
• When the sum of two digits is less than or equal to 9 then the
ordinary 4-bit adder can be used.

• But if the sum of two digits is greater than 9 or if a carry is

generated then a correction ( decimal no. 6) must be added “i.e
adding 0110”.

• We need to design a circuit that is capable of doing the correct

addition

RVK-LDCO-2.3 37
 Examples :
1. CASE I : Sum £ 9 & carry = 0.

• Add BCD digits 3 & 4

1. 0011
+0100
---------
0 1 1 1 -- No Carry and Sum< 9

• Answer is valid BCD number = (7)BCD & so addition of 0110 is not

added.

RVK-LDCO-2.3 38
 Examples :
2. CASE II : Sum > 9 & carry = 0.
• Add BCD digits 6 & 5
1. 0110
+0101
-----------
1 0 1 1 -- No Carry, but Sum>9
• Invalid BCD (since sum > 9) so 0110 is to be added
2. 1011
+0110
-----------
10001
(1 1)BCD

• Valid BCD result = (11)BCD

RVK-LDCO-2.3 39
 Examples :
3. CASE III : Sum £ 9 & carry = 1.
• Add BCD digits 9 & 9
1. 1001
+ 1001
-----------
1 0 0 1 0 -- Carry=1, but Sum< 9
• Invalid BCD ( since Carry = 1 ) so 0110 is to be added
2. 1 0 0 1 0
+ 0110
------------
1 1000
(1 8)BCD
• Valid BCD result = (18)BCD
RVK-LDCO-2.3 40
 Design of BCD Adder
• Consider the addition of two decimal digits in BCD, together with an input
carry from a previous stage.

• Since each input BCD digit does not exceed 9, the output sum cannot be
greater than 9 + 9 + 1 = 19, the 1 in the sum being an input carry.

• If we apply two BCD digits to a 4-bit binary adder, then the adder will form
the sum in binary and produce a result that ranges from 0 through 19.

• These Binary sums and its corresponding BCD sums are listed in Table A.

• When the binary sum £ 1001, the corresponding BCD number is identical
èNo conversion is needed.

• When the binary sum > 1001, we obtain an invalid BCD representation.
The addition of binary 6 (0110) to the binary sum converts it to the correct
BCD representation and also produces an output carry as required.
RVK-LDCO-2.3 41
 Table A:
Binary sums
and its
corresponding
BCD sums

RVK-LDCO-2.3 42
 Derivation of BCD Adder
• Referring to the table entries, it is obvious that a correction is
needed in the following conditions:
1. Whenever the binary sum has an output carry Z4 = 1 (sums >15).
2. The other six combinations from 1010 through 1111 (sums from 10
to 15) i.e. whenever Z3=1 and either Z2 or Z1 or both are 1.

• The condition for a correction and an output carry X can be

expressed by the Boolean Function:
X = Z4 + Z3 ( Z2 + Z1)
• So, whenever X = 1 we should add a correction of 0110 to the
sum.

RVK-LDCO-2.3 43
 Design of BCD Adder Using IC 7483
• To execute first step i. e. binary addition of two 4-bit numbers we
will use IC 7483 ( with Cin = 0 ), which is 4-bit binary adder.

• We need to design a digital circuit which will sense sum & carry of IC
7483 & if sum exceeds 9 or carry = 1, this digital circuit will produce
high output (X=1 )otherwise its output will be zero (X=0 ).

• If this output is high (X=1) then the correction of 0110 is added to

the sum using another IC7483.

RVK-LDCO-2.3 44
Ex1. 5+3
Inputs:[A]=0101, [B]= 0011, C0=0 0011

0101
0 1 0 0 0

0 0
0

1000
0

1 0 0 0
RVK-LDCO-2.3 0000 45
Ex2. 7+6
Inputs:[A]= 0111, [B]= 0110, C0=0
0110

0111
0 1 1 0 1

1 1
1
1101
1
0 0 1 1

RVK-LDCO-2.3 0110 46
 Cascading BCD Adders
• The previous circuit is used for adding only two decimal digits in
BCD. E.g. 7 + 6 = 13.

• For adding numbers with several digits, a separate BCD adder for
each digit position must be used.

• For example:
BCD Adder BCD Adder
2 4 7
+ 5 3 8
----------------------------
?

BCD Adder

RVK-LDCO-2.3 47
Cascading BCD Adders

RVK-LDCO-2.3 48
 BCD Addition Example
Q. Determine the inputs and the outputs when the above
circuit is used to add 538 to 247. Assume a CARRY IN =
0.

Solution:
– Represent the decimal numbers in BCD
247 = 0010 0100 0111
538 = 0101 0011 1000
– Put these numbers in registers [A] and [B]
[A] = 0010 0100 0111
[B] = 0101 0011 1000

RVK-LDCO-2.3 49
 BCD Addition Example (cont..)

0 0 1 0 0 1 0 0 0 1 1 1
0 0 1
0
0111 1000 0101

0 1 0 1 0 0 1 1 1 0 0 0

Sol= ( 0 0111 1000 0101)BCD = (785)10

RVK-LDCO-2.3 50
 2.4 Combinational MSI
Circuits- BCD Subtractor

-Mrs. Radhika V. Kulkarni

Assistant Professor, Dept. of Information Technology,
Pune Institute of Computer Technology, Pune.

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third Edition.
2. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second Edition.
 BCD Subtractor
• Rules for BCD subtraction :
1. Find 9’s complement of the subtrahend.
a) To find 9’s complement first find 1’s complement of subtrahend.
b) Add (10)10 i.e. (1010)2 to it.
2. Add 9’s complement of the subtrahend to the minuend using
BCD rules of addition.
3. After BCD addition if carry out of MSB is 0, result is negative
expressed in 9’s complement form to get it in natural form find
9’s complement of the LSB of the result.
4. But after BCD addition if carry out of MSB is 1 it indicates that
result is positive expressed in natural form & add ( 1 )10 i. e. (
0001 )2 to it.

RVK-LDCO-2.4 52
 Examples :
1. CASE I : Carry = 1, Answer is positive.
• Subtract BCD digit 2 from 8. i.e. (8-2)

1. 9’s complement of subtrahend (2)10 i.e. (0010)2 :

a) 1’s complement of (2)10 = (1 1 0 1)2
b) Add (10)10 i.e. (1010)2

1101 1’s complement of (2)10

+ 1010 (10)10
---------
1 0111 (discard carry).
Hence 9’s complement of subtrahend (2)10 i.e. (0010)2 = (0111)2
RVK-LDCO-2.4 53
 Ex: 1. CASE I : Carry = 1, Answer is positive (cont..)
2. Add 9’s complement of the subtrahend to the minuend using BCD addition rules

1000 (8)10
+0 1 1 1 9’s comp. of (2)10
----------
1 1 1 1 --No carry, but Sum>9
Invalid BCD so (0110)2 is added
1111
+ 0110
----------
10101

3. Since carry out of MSB after BCD addition is 1, answer is positive expressed in natural form &
to get final answer carry is added at the end.
0101
+ 1 Add End Around Carry (EAC)
-----------
0110 Final Answer: (8-2)10 =(6)10

RVK-LDCO-2.4 54
 Examples :
2. CASE II : Carry = 0, Answer is negative.
Ex. 1 Subtract BCD digit 9 from 6. i.e. (6-9)

1. 9’s complement of subtrahend (9)10 i.e. (1001)2 :

a) 1’s complement of (9)10 = (0 1 1 0)2
b) Add (10)10 i.e. (1010)2

0110 1’s complement of (9)10

+ 1010 (10)10
---------
1 0000 (discard carry).
Hence 9’s complement of subtrahend (9)10 i.e. (1001)2 = (0000)2
RVK-LDCO-2.4 55
 Ex: 1. CASE II : Carry = 0, Answer is negative(cont..)
2. Add 9’s complement of the subtrahend to the minuend using BCD addition rules
0110 (6)10
+ 0000 9’s comp. of (9)10
----------
0 1 1 0 --No carry, Sum< 9 àValid BCD

3. Since carry out of MSB after BCD addition is 0, answer is negative expressed in 9’s
compliment form & to get final answer, 9’s compliment of answer is taken.
9’s complement of the answer 0110:
a) 1’s complement of answer 1001
b) add (1010)2 + 1010
----------
10011 (discard carry).
Final Answer: (6-9)10 = -(3)10

RVK-LDCO-2.4 56
 Ex: 2. CASE II : Carry = 0, Answer is negative

Ex. 2 Subtract BCD digit 9 from 8. i.e. (8-9)

1. 9’s complement of subtrahend (9)10 i.e. (1001)2 :

a) 1’s complement of (9)10 = (0 1 1 0)2
b) Add (10)10 i.e. (1010)2

0110 1’s complement of (9)10

+ 1010 (10)10
---------
1 0000 (discard carry).
Hence 9’s complement of subtrahend (9)10 i.e. (1001)2 = (0000)2
RVK-LDCO-2.4 57
 Ex: 2. CASE II : Carry = 0, Answer is negative(cont..)
2. Add 9’s complement of the subtrahend to the minuend using BCD addition rules
1000 (8)10
+ 0000 9’s comp. of (9)10
----------
1 0 0 0 --No carry, Sum< 9 àValid BCD

3. Since carry out of MSB after BCD addition is 0, answer is negative expressed in 9’s
compliment form & to get final answer, 9’s compliment of answer is taken.
9’s complement of the answer 1000:
a) 1’s complement of answer 0111
b) add (1010)2 + 1010
----------
10001 (discard carry).
Final Answer: (8-9)10 = -(1)10

RVK-LDCO-2.4 58
 Design of BCD Subtractor
1. To execute first step i. e. to find 9’s compliment of subtrahend
a) First we find 1’s compliment of subtrahend.
b) Then add (10)10 i.e. (1010)2 to 1’s compliment of subtrahend.
We use inverter to get 1’s compliment of subtrahend. Since subtrahend is 4 bit
we need 4 inverters and to add this to (1010)2, 4 bit binary adder IC 7483 is
used.
2. Circuit for BCD addition of 9’s compliment of subtrahend and
minuend:
We will use already designed BCD adder
3. Circuit to get answer in correct form:
– If carry out of MSB after BCD addition is 0, answer is negative expressed in
9’s compliment form & to get answer in correct form we have to find 9’s
compliment of the result.
– If carry out of MSB after BCD addition is 1, answer is positive expressed in
natural form & to get final answer carry is added to the earlier answer.
RVK-LDCO-2.4 59
Logic
Dia-
gram

RVK-LDCO-2.4 60
 Subtrahend
0 0 1 0

Ex. 8-2 (10)10

1 0 1 0
1 1 0 1 1’s complement

(1000)2
1 01 1 1
- (0010)2 9’s complement of
subtrahend
Minuend 1 0 0 0 0 1 1 1

Final Answer: 1
(8-2)10 = +(6)10 0 1 1 1 1
0
00 10 00 10
1
1

1 0 1 0 1

1 (10)10
0 1 1 0 1 1 1 1
0 0 0 0 0 1 0 1

0 1 0 1 1 0 Final Ans.
1 0 1 0 1 0
RVK-LDCO-2.4 61
 Subtrahend
1 0 0 1

Ex. 6-9 (10)10

1 0 1 0
0 1 1 0 1’s complement

(0110)2
1 0 0 0 0
- (1001)2 9’s complement of
subtrahend
Minuend 0 1 1 0 0 0 0 0

Final Answer: 0
(6-9)10 = -(3)10 0 0 1 1 0
1
01 11 11 01
0
0

1 1 0 0 1

0 (10)10
0 0 0 0 0 1 1 0
1 0 1 0 1 0 0 1

0 1 0 0 0 1 1 Final Ans.
0 1 1 0 1
RVK-LDCO-2.4 62
 2.5 Combinational MSI Circuits-
Multiplexers & Demultiplexers

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second Edition.
 Multiplexers and De-Multiplexers
• A multiplexer or mux selects one data line from two or more input
lines and routes data from the selected line to the output. The
particular data line that is selected is determined by the select
inputs.

• A demultiplexer or demux performs the opposite function from a

MUX. It switches data from one input line to two or more data
lines depending on the select inputs.

RVK-LDCO-2.5 64
Multiplexers
 Multiplexers
• A multiplexer is a device which has
– A number of input lines
– A number of selection lines
– One output line

• It steers one of 2n inputs to a single output line, using n

selection lines. Also known as a data selector.

2n:1
inputs : Multiplexer output

...

select
RVK-LDCO-2.5 66
 Multiplexers (cont..)
• Truth table for a 4-to-1 multiplexer:

I0 I1 I2 I3 S1 S0 Y S1 S0 Y
d0 d1 d2 d3 0 0 d0 0 0 I0
d0 d1 d2 d3 0 1 d1 0 1 I1
d0 d1 d2 d3 1 0 d2 1 0 I2
d0 d1 d2 d3 1 1 d3 1 1 I3

Inputs Inputs
I0 0 I0
I1 4:1 I1
1 4:1
MUX Y
I2 2 Y Y I2 mux
I3 3 I3 Output
S1 S0 Output
S1 S0
Select Select
inputs inputs
RVK-LDCO-2.5 67
 Multiplexers (cont..)
• Output of multiplexer is S1 S0 Y
0 0 I0
“sum of the (product of data lines and selection lines)” 0 1 I1
1 0 I2
1 1 I3
• Example: Output of a 4-to-1 multiplexer is:
Y = S1’ S0’ I0 + S1’ S0 I1 + S1 S0’ I2 + S1 S0 I3
I0
• 4-to-1 multiplexer circuit:
I1
Y
I2

I3

RVK-LDCO-2.5 68
S1 S0
 Multiplexers (cont..)
• Truth table of 4:1 multiplexer with
strobe input:
• A strobe(or enable) input (G) helps in cascading.
• It is generally active-low which means it performs
its intended operation when it is LOW.

• Output of a 4:1 multiplexer with active- low strobe(enable)is:

• 4:1 multiplexer circuit

with strobe input using
NAND gates:

RVK-LDCO-2.5 69
 Multiplexers (cont..)
• An application:

• Helps to share a single communication line among a number

of devices.
• At any time, only one source and one destination can use the
communication line.

RVK-LDCO-2.5 70
 Combinational Logic Design Using
Multiplexers
• Multiplexers offer the following advantages:
– Simplification of a logic expression is not needed.
– It minimizes IC package count.
– Logic design is simplified

• Available multiplexer ICs:

RVK-LDCO-2.5 71
Cascading of Multiplexers
 Multiplexer IC Package
• Some IC packages have a few multiplexers in each package (chip).
The selection and enable inputs are common to all multiplexers
within the package.
A0
Y0
A1
Y1
A2
Y2
A3
Y3
B0
B1 E’ S Output Y
B2 1 X all 0’s
0 0 select A
B3 0 1 select B
S
(select)
E'
(enable) Quadruple 2:1 multiplexer
RVK-LDCO-2.5 73
 Larger Multiplexers
• Larger multiplexers can be constructed from smaller ones.

• An 8:1 multiplexer can be constructed from smaller multiplexers

like this (note placement of selector lines):

I0
I1 4:1
I2
S2 S1 S0 Y
MUX
I3 0 0 0 I0
2:1
0 0 1 I1
S1 S0 MUX Y 0 1 0 I2
I4 0 1 1 I3
I5 4:1 1 0 0 I4
I6 MUX 1 0 1 I5
S2
I7 1 1 0 I6
1 1 1 I7
S1 S0
RVK-LDCO-2.5 74
 Larger Multiplexers (cont..)
• An 8:1 multiplexer can be constructed from smaller multiplexers:
S2 S1 S0 Y
I0
I1 I0 I1 I2 0 0 0 I0
4:1
I2 MUX 0 0 1 I1
I3
I0 I1 I6 0 1 0 I2
2:1
S1 S0 MUX Y 0 1 1 I3
I4 1 0 0 I4
I5 4:1 I4 I5 I6 1 0 1 I5
I6 MUX
I7
S2 1 1 0 I6
1 1 1 I7
S1 S0

• When S2S1S0 = 000

• When S2S1S0 = 001
• When S2S1S0 = 110
RVK-LDCO-2.5 75
 Larger Multiplexers (cont..)
• Another implementation of an 8-to-1 multiplexer using smaller
multiplexers:

S2 S1 S0 Y
When
I0 2:1 0 0 0 I0
S2S1S0 = 000
I1 MUX 0 0 1 I1
0 1 0 I2
I0
I2 2:1 S0 0 1 1 I3
I3 MUX 1 0 0 I4
I2
I0 1 0 1 I5
4:1 1 1 0 I6
S0 MUX Y
1 1 1 I7
I4 2:1 I4
I5 MUX
S2 S1
I6
S0 I6 2:1
I7 MUX Q: Can we use only 2:1 multiplexers?
S0
RVK-LDCO-2.5 76
 Larger Multiplexers (cont..)

• A 16-to-1 multiplexer
can be constructed from
five 4-to-1 multiplexers:

RVK-LDCO-2.5 77
 Standard MSI Multiplexer
• 74151A 8-to-1 multiplexer:

(a) Package configuration (b) Function table.

RVK-LDCO-2.5 78
 Standard MSI Multiplexer(cont..)
• 74151A 8-to-1 multiplexer:

(c)

(c) Logic diagram (d) Generic logic symbol e) IEEE standard logic symbol
Source: The TTL Data Book Volume 2. Texas Instruments
RVK-LDCO-2.5 Inc.,1985. 79
 Implementing Boolean
Functions Using Multiplexer
 Implementing Functions Using Multiplexer
• Boolean functions can be implemented using multiplexers.
• To implement a Boolean function of n input variables, a 2n-to-1
multiplexer with n selection lines is needed.
• Design procedure is as follows:
1. Express a Boolean function in sum-of-minterms form and identify a decimal
number corresponding to each minterm in the expression.
Example: F(A,B,C) = A'×B'×C + A'×B×C + A×B'×C + A×B×C'
= S m(1,3,5,6)
2. Connect n variables to the n selection lines.
3. Input lines corresponding to minterms in the expression are connected to logic
‘1’ and all other input lines are connected to logic ‘0’.

RVK-LDCO-2.5 81
 Example 1: Implementing Functions Using
Multiplexer
Ex.1 F(A,B,C) = S m(1,3,5,6)
Sol.
• Since there are 3 variables, a multiplexer with 3 select lines is
needed.
• Hence 23-to-1 (8:1) multiplexer is used.

This method works because:

Output = m0×I0 + m1×I1 + m2×I2 + m3×I3
+ m4×I4 + m5×I5 + m6×I6 + m7×I7

Supplying ‘1’ to I1,I3,I5,I6 , and ‘0’ to the

rest:
Output = m1 + m3 + m5 + m6
RVK-LDCO-2.5 82
 Implementation Using Smaller Multiplexer
• Earlier, we saw how a 2n-to-1 multiplexer can be used to
implement a Boolean function of n (input) variables.

• However, we can use a single smaller 2(n-1)-to-1 multiplexer to

implement a Boolean function of n (input) variables.

• Example: The function F(A,B,C) = S m(0,1,3,6) can be implemented

using a 4-to-1 (22:1) multiplexer rather than an 8-to-1 (23:1)
multiplexer.

RVK-LDCO-2.5 83
 Implementation Using Smaller Multiplexer
(cont..)
• Design Procedure is as follows:
1. Express a Boolean function in sum-of-minterms form.

2. Reserve one variable for input lines of multiplexer and use the
rest (n-1) variables for selection lines.

3. Draw the truth table for function, by grouping inputs by

selection line values, then determine multiplexer inputs by
comparing input line and function for corresponding selection
line values.

RVK-LDCO-2.5 84
 Example1 : Implementation Using Smaller
Multiplexer
Ex1: F(A,B,C) = S m(0,1,3,6) = A'×B'×C' + A'×B'×C + A'×B×C + A×B×C’
Sol.
• Truth table and implementation using 8-to-1 (23:1)
multiplexer as the function has 3 variables:

1 0
1 1
0 2
1 3 mux F
0 4
0 5
1 6
0 7
A B C

• It can be implemented using a smaller i.e. 4-to-1 (22:1)

multiplexer. RVK-LDCO-2.5 85
 Example1 : Implementation Using Smaller
Multiplexer(cont..)
• Procedure:
1. Expression of a Boolean function in sum-of-minterms form:
F(A,B,C) = S m(0,1,3,6)
2. Reserve a variable C (in this case, we have taken the least significant one) for
input lines of multiplexer, and apply other two variables, A and B, as
selection lines of the multiplexer.
3. Draw the truth table for function, by grouping inputs by selection line
values, then determine multiplexer inputs by comparing input line (C) and
function (F) for corresponding selection line values.

? 0
? 1 F
mux
? 2
? 3

A B
RVK-LDCO-2.5 86
 Example1 : Implementation Using
Smaller Multiplexer (cont..)
MUX A B C F Mux
A B C F Input
input
0 0 0 1 1 0
0 0 0 1 1
0 0 1 1 C 1
0 0 1 1 F
0 1 0 0
C 2 mux
0 1 0 0 0 1 1 1 0
3
0 1 1 1
1 0 0 0
0 C'
1 0 1 0
1 0 0 0 1 1 0 1
C’
1 0 1 0 1 1 1 0 A B
1 1 0 1
1 1 1 0

• Note: Two of the variables, A and B, are applied as selection lines of

the multiplexer, while the inputs of the multiplexer contain 1, C, 0
and C'.
RVK-LDCO-2.5 87
 Hardware Reduction Table Method
• Implementation of a Boolean function using a smaller multiplexer
can be easily done by Hardware Reduction Table Method.
• We can reserve any variable for input data lines and the rest are
used as selection lines.
• Procedure:
– Reserve any variable and considering its LOW and HIGH value mark minterms
in the hardware reduction table.(In the hardware reduction table, #columns =
# inputs of a MUX to be used.)
– Identify/Highlight the minterms of the given function for both the logical
values of the reserved variable.
– If in each column of a hardware reduction table,
• None of the highlighted minterm is present then, MUX i/p will be 0.
• Both the highlighted minterms are present then, MUX i/p will be 1.
• If the highlighted minterm is present for only Logic 0, MUX i/p will be a complemented
value of that variable.
• If the highlighted minterm is present for only Logic 1, MUX i/p will be the same variable.
RVK-LDCO-2.5 88
 Example1 : Implementation Using
Smaller Multiplexer (cont..)
Ex.1 F(A,B,C) = S m(0,1,3,6)
Alternative Sol.: By Hardware Reduction Table Method:
• Reserve variable C for input data lines and the rest are used as
selection lines. D0 D1 D2 D3
C’ 0 2 4 6
C 1 3 5 7
i/p to MUX 1 C 0 C’

• OR Reserve variable A for input data lines and the rest are used as
selection lines. D D D D
0 1 2 3

A’ 0 1 2 3
A 4 5 6 7
i/p to MUX A’ A’ A A’
RVK-LDCO-2.5 89
 Example 2: Implementation Using Smaller
Multiplexer
Ex.2 F(A,B,C,D) = S m(0,2,3,6,8,9,12,14)
Sol.
• Since there are 4 variables, a
multiplexer with 4 select lines is
needed.
• Hence 24-to-1 (16:1) multiplexer is
used.
• Thus only one IC package for 16:1
multiplexer is required to implement a
given Boolean function.
• Note: Here, a multiplexer output is active-high.
In case of active-low, the logic ‘0’ and logic ‘1’
on this figure are to be interchanged.

RVK-LDCO-2.5 90
 Example 2: Implementation Using Smaller
Multiplexer (cont..)
Alternative Sol. : Implementing a Boolean function of n variables with
a multiplexer that has n - 1 selection inputs.
• Truth Tables for F(A,B,C,D) = S m(0,2,3,6,8,9,12,14)
With 4 variables
With 3 variables

RVK-LDCO-2.5 91
 Example 2: Implementation Using Smaller
Multiplexer (cont..)
Alternative Sol. : (with n-1 select lines)
• Thus realization with 3 variables require 3 select lines and thus 23-
to-1 (8:1) multiplexer is used.

RVK-LDCO-2.5 92
 Example2 : Implementation Using
Smaller Multiplexer (cont..)
Ex.2 F(A,B,C,D) = S m(0,2,3,6,8,9,12,14)
Alternative Sol. : (with n-1 select lines)
By Hardware Reduction Table Method:
• Reserve variable D for input data lines and the rest are used as
selection lines.

D0 D1 D2 D3 D4 D5 D6 D7

D’ 0 2 4 6 8 10 12 14
D 1 3 5 7 9 11 13 15
i/p to MUX D’ 1 0 D’ 1 0 D’ D’

RVK-LDCO-2.5 93
 Example 3: Implementation Using Smaller
Multiplexer (cont..)
Ex.3: Implement the function below with 74151A:
f(x1,x2,x3,x4) = S m(0,1,2,3,4,9,13,14,15)
Sol. 74151A is 8:1 Mux.

RVK-LDCO-2.5 94
 Example4 : Implementation Using
Smaller Multiplexer (cont..)
Ex.4 Implement the function below with 74153 using variable A at
data input lines of a MUX: F(A,B,C) = S m(1,2,4,7)
Sol. 74153 is 4:1 MUX.
• We will use Hardware Reduction Table Method.

• Reserve variable A for input data lines and the rest are used as
selection lines.

D0 D1 D2 D3
A’ 0 1 2 3
A 4 5 6 7
i/p to MUX A A’ A’ A

RVK-LDCO-2.5 95
 Example5 : Implementation Using
Smaller Multiplexer (cont..)
Ex.5 Implement the function below with 74151A using variable B at
data input lines of a MUX: f(A,B,C,D) = S m(0,1,2,3,4,9,13,14,15)
Sol. 74151A is 8:1 MUX.
• We will use Hardware Reduction Table Method.

• Reserve variable B for input data lines and the rest are used as
selection lines.

D0 D1 D2 D3 D4 D5 D6 D7

B’ 0 1 2 3 8 9 10 11
B 4 5 6 7 12 13 14 15
i/p to MUX B B’ B’ 0 0 1 B B

RVK-LDCO-2.5 96
Implementing Full Adder
Using Multiplexer
 Full Adder
• Adding two single-bit binary
values, X, Y with a carry input bit
C-in produces a sum bit S and a
carry out C-out bit.

The S function is the three-bit XOR function

(Odd Function): S = X Å Y Å (C-in)

C-out = XC-in + YC-in+ XY

RVK-LDCO-2.5 98
 Full Adder Using 4:1 Multiplexer(IC74153)
• S(X,Y,C-in) = ∑(1,2,4,7)
• Instead of 3 select lines for 3 variables we can use 2 select lines.
• Reserve a variable C-in (we take the least significant one) for input
lines of multiplexer, and apply other two variables, X and Y, as
selection lines of the multiplexer.

Truth Table Logic

RVK-LDCO-2.5 Diagram for Sum S using 4:1 Mux99
 Full Adder Using 4:1 Multiplexer(cont..)
• C-out(X,Y,C-in) = ∑(3,5,6,7)
• Instead of 3 select lines for 3 variables we can use 2 select lines.
• Reserve a variable C-in (we take the least significant one) for input
lines of multiplexer, and apply other two variables, X and Y, as
selection lines of the multiplexer.

Truth Table Logic

RVK-LDCO-2.5 Diagram for Carry C-out using 4:1 Mux
100
Demultiplexers
 Demultiplexers
• Given an input line and a set of selection lines, a demultiplexer
directs data from the input to one selected output line.
• Example: 1-to-4 demultiplexer.
Outputs

Y0 = D∙S1'∙S0'
Y1 = D∙S1'∙S0
Data D demux
Y2 = D∙S1∙S0'
Y3 = D∙S1∙S0

S1 S0
select

S1 So Y0 Y1 Y2 Y3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D RVK-LDCO-2.5 102
 Demultiplexers (cont..)
• It turns out that the demultiplexer circuit is actually identical to a
decoder with enable.

• Note: Decoder is a combinational circuit that converts binary

information from n coded inputs to a maximum 2n coded outputs
→ n to 2n decoder

Y0 = E∙A’∙B'
Y1 = E∙A’∙B
Y2 = E∙A∙B'
Y3 = E∙A∙B

RVK-LDCO-2.5 103
Cascading of Demultiplexers
 Larger Demultiplexers
• Implementation of 1:8 demultiplexer using 1:4 demultiplexers and
1:2 demultiplexer:

RVK-LDCO-2.5 105
 Larger Demultiplexers
• Implementation of
1:16 demultiplexer
using 1:8
demultiplexers and 1:2
demultiplexer:

RVK-LDCO-2.5 106
 2.6 Combinational Circuits-
Decoders & Encoders

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second Edition.
Decoders
 Decoders
• A combinational circuit that converts binary information from n
coded inputs to a maximum 2n coded outputs → n to 2n decoder.

• n-to-m decoder, m £ 2n
– Examples: BCD-to-7-segment decoder,
where n = 4 and m = 10

• Enable input: it must be ON (active) for the decoder to function,

otherwise its outputs assume a single "disabled" output code word.

Only one output is HIGH for

each input code

RVK-LDCO-2.6 109
 2-to-4 Decoder
• This is what a 2-to-4 decoder looks like on the inside.

RVK-LDCO-2.6 110
3-line-to 8-line (3-to-8) or (1-of-8) Decoder
• Three inputs A, B, C, are decoded
into eight outputs, O0 through O7.

• Each output Oi represents one of

the minterms of the 3 input
variables.

• Oi = mi . E.g. Oi = 1 when the

binary number CBA = 001.

• The output variables are mutually

exclusive; exactly one output has
the value 1 at any time, and the
other seven are 0.

RVK-LDCO-2.6 111
 74138 Decoder with Enable
• 3-to-8 decoder constructed with NAND gates.
• As NAND gate produces AND operation with an inverted output, it
economically produces minterms in their complemented form.
• Logic diagram for the 74LS138 decoder:

RVK-LDCO-2.6 112
 Enable Inputs
• The 74138 features 3 ENABLE inputs, two active LOW (E1 and E2)
and one active HIGH (E3) to control the operation of the decoder.

• The decoder is enabled only if corresponding ENABLE is active.

• When ENABLE signal line E1 and E2 held LOW and E3 held HIGH, the
decoder will function normally and the A0, A1, A2 input code will
determine which output is LOW.

• When ENABLE signals

are in its inactive states,
all of the outputs will be
forced to the HIGH state
regardless of the levels
Truth table of the 74138 decoder of A,B,C inputs.
RVK-LDCO-2.6 113
 Example1: 74LS138 Decoder
Ex1. Indicate the states of the 74LS138 outputs for the following
inputs:
(a) E3=E2=1, E1=0, A2=A1=1, A0=0
(b) E3=1, E2=E1=0, A2=0, A1=A0=1
Sol.:
(a) The decoder is disabled and all the outputs are in their inactive
High states.

(b) The decoder is enabled, decoding input 0112=310. Thus O3 will

be LOW and all other outputs will be HIGH.

RVK-LDCO-2.6 114
Cascading of Decoders
 Larger Decoders
• Implementation of 4:16 decoder using 3:8 decoders:

• When w=0, the top decoder is enabled and the other is disabled.
– The bottom decoder outputs are all 0’s, and the top eight outputs generate
minterms 0000 to 0111.
• When w=1, the bottom decoder is enabled and the other is
disabled.
– The bottom decoder outputs generate minterms 1000 to 1111, while the
outputs of the top decoder are all 0’s.
• It demonstrates the usefulness of enable inputs.
RVK-LDCO-2.6 116
 Standard MSI Decoder
• 74138 : 3 lines-to-8 lines Decoder

(a) Package configuration

(b) Function table.
RVK-LDCO-2.6 117
 Implementing Boolean
Functions Using Decoder
Implementing Boolean Functions with Decoders
• A decoder can be conveniently used to implement a given Boolean
function.

• The decoder generates the required minterms and an external OR

gate is used to produce the sum of minterms.

• In general, an n-to-2n decoder and an external m inputs OR gate

can be used to implement any combinational circuit with n inputs
and m outputs.

RVK-LDCO-2.6 119
 Example 1: Implementing Functions Using
Decoder
Ex.1 Implement a given Boolean function using a decoder.
Y = A• B •C + A• B •C + A• B •C + A• B •C
Sol.
• A given function Y is written as Y(A,B,C)=∑(0,2,4,7).
• Since there are 3 variables and , a decoder 3-lines to 8-lines is
used.

RVK-LDCO-2.6 120
 Example 2: Implementing Functions Using
Decoder
Ex.2 Implement Full adder using a decoder.
Sol.
• In Full Adder, a function for Sum is written as S(X,Y,C-in) =∑(1,2,4,7)
and a function for C-out is written as C-out(X,Y,C-in) = ∑(3,5,6,7).
• Since there are 3 variables and , a decoder 3-lines to 8-lines is used.

RVK-LDCO-2.6 121
 Implementation of Full
Subtractor Using Decoder
 Full Subtractor
• Subtracting two single-bit
binary values, Y, B-in from a
single-bit value X produces a
difference bit D and a borrow
out B-out bit.
• This is called full subtraction. D = X Å Y Å (B-in)

B-out = X'Y + X'(B-in) + Y(B-in)

= X'Y + B-in(X Å Y)'
Note: D= X – Y – B-in
(In the same way as we did with the full adder)
D(X,Y, B-in) = S (1,2,4,7)
B-out(X, Y, B-in) = S (1,2,3,7)RVK-LDCOL-Week10-11 123
 Full Subtractor Using 3x8 Decoder
• D(X,Y,C-in) = ∑(1,2,4,7) and B-out(X, Y, B-in) = S (1,2,3,7)
• Since there are 3 variables and , a decoder 3-lines to 8-lines is
used.

Logic Diagram for Full Subtractor Using

3x8 Decoder
RVK-LDCO-2.6 124
 Full Subtractor Using 3x8 Decoder(IC74138)
• D(X,Y,C-in) = ∑(1,2,4,7) and B-out(X, Y, B-in) = S (1,2,3,7)
• Since there are 3 variables and , a decoder 3-lines to 8-lines is
used. As IC 74138 has active low output, NOR gates are used in the
second level to get D and B-out.

Logic Diagram for Full Subtractor Using

3x8 Decoder IC 74138
RVK-LDCO-2.6 125
Encoders
 Encoders
• Performs the inverse operation of a decoder.
• Has m input lines and n output lines of which only one input line
is usually active at a time. m £ 2n.
• The output generates an n-bit output code dependent upon
which input is activated.

RVK-LDCO-2.6 127
 Encoders
• Example: Octal-to-Binary encoder
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

– Output Functions:
x= D4 + D5 + D6 + D7
y= D2 + D3 + D6 + D7
z= D1 + D3 + D5 + D7
– At any one time, only one input line has a value of 1.
– Otherwise, we need priority encoder.
RVK-LDCO-2.6 128
 Encoders
• Example: Octal-to-Binary encoder

D0
D1 x = D 4 + D5 + D6 + D7
D2
D3
y = D 2 + D3 + D6 + D7
D4
D5
D6
D7 z = D 1 + D3 + D5 + D7

An 8-to-3 encoder

• Exercise: Can you design a 2n-to-n encoder without using K-

map?
RVK-LDCO-2.6 129
 Limitations of Encoders
• Example: Octal-to-Binary encoder:
• Only one input can be active at any given time.
– Output functions of octal-to binary encoder are:
x= D4 + D5 + D6 + D7
y= D2 + D3 + D6 + D7
z= D1 + D3 + D5 + D7
– If both D3 and D6 are 1 simultaneously then output (xyz)=111. It does not
represent either binary 3 or binary 6.
– To resolve this ambiguity, encoder circuits must establish an input priority to
ensure that only one input is encoded.

• An output with all 0’s is generated when all the inputs are 0; but this
output is the same as when D0 is equal to 1.
– The discrepancy can be resolved by providing one more output to indicate
whether at least one input is equal to 1.

RVK-LDCO-2.6 130
Priority Encoders
 Priority Encoders
• A priority encoder is one that includes the priority function.
– If two or more inputs are simultaneously equal to 1, the input with the highest
priority takes precedence.
– If all inputs are 0, this input combination is considered invalid.

• Example : 4-to-2 priority encoder: Inputs Outputs

– In addition to the 2 outputs x and y, the circuit D0 D1 D2 D3 x y V
has a 3rd output V as a valid bit indicator that 0 0 0 0 X X 0
is set to 1 when one or more inputs are 1.
1 0 0 0 0 0 1
– If all inputs are 0, there is no valid input. So, V
is equal to 0 and other 2 outputs x and y are X 1 0 0 0 1 1
not inspected and are specified as don’t-care X X 1 0 1 0 1
conditions (marked with X). X X X 1 1 1 1
– Note: Instead of listing all 16 minterms of 4
variables, the inputs are marked as X to
represent either 1 or 0. e.g. X100 represents
the 2 minterms 0100 and 1100. RVK-LDCO-2.6 132
 Priority Encoders (cont..)
• Example : 4-to-2 priority encoder: Inputs Outputs
– The higher the subscript number, the higher D0 D1 D2 D3 x y V
the priority of the input.
0 0 0 0 X X 0
– Input D3 has the highest priority, so,
regardless of the values of the other inputs, 1 0 0 0 0 0 1
when D3 = 1, the output for xy is 11 (binary 3). X 1 0 0 0 1 1
– D2 has the next priority level. The output is 10 X X 1 0 1 0 1
if D2 = 1, provided that D3 = 0, regardless of X X X 1 1 1 1
the values of the other two lower priority
inputs.
– The output for D1 is generated only if higher
priority inputs are 0, and so on down the
priority levels.

RVK-LDCO-2.6 133
 74HC147 Decimal to BCD Priority Encoder
• The 74HC147 is an example of an encoder IC.
• It has ten active-LOW inputs and converts the active input to an
active-LOW BCD output.
• This device offers additional
flexibility with a priority
encoder.
– An encoder in which multiple
asserted inputs are allowed but
only the highest value input digit
is encoded and any other active
input is ignored.
– Thus resolve the ambiguity
mentioned above.

RVK-LDCO-2.6 134
 2.7 Code Conversion

-Mrs. Radhika V. Kulkarni

Assistant Professor, Dept. of Information Technology,
Pune Institute of Computer Technology, Pune.

Sources:
1. “Modern Digital Electronics”, R.P. Jain, Tata McGraw-Hill , Third Edition.
2. “Digital Design”, M Morris Mano, Prentice Hall, Third Edition.
3. “Fundamentals of Digital Circuits”, A. Anand Kumar, PHI, Second Edition.
 Code Conversion
• Different digital systems use different codes .
• It is sometimes necessary to use the output of one system as the
input to another.
– A conversion circuit must be inserted between the two systems if each uses
different codes for the same information.

• A code converter is a circuit that makes the two systems compatible

even though each uses a different binary code.
– To convert from binary code A to binary code B, the input lines must supply
the bit combination of elements as specified by code A and the output lines
must generate the corresponding bit combination of code B.

• A combinational circuit performs this transformation by means of

logic gates.
– E.g. Binary Coded Decimal (BCD) to the Excess-3 code for the decimal digits.
RVK-LDCO-2.7 136
 BCD & Excess-3 Codes
• The BCD code is obtained by representing each decimal digit in a
given decimal number by its natural 4-bit binary equivalent..
– E.g. BCD Representation of (6349)10 is obtained as: 6 3 4 9
BCD= 0110 0011 0100 1001

– It represents the decimal numbers 0 to 9. So, some codes are unused, like
1010BCD, 1011BCD, … 1111BCD. These codes are considered as errors.

• The excess-3 code is obtained

by adding 3 (0011) to the
corresponding BCD equivalent
binary number.
– E.g. (4)10 = (0100)BCD = 0100+
0011 =(0111)XS-3

RVK-LDCO-2.7 137
BCD To Excess-3 Conversion
 Truth Table for Code Conversion
• 4 binary i/p variables may have 16
bit combinations, but BCD
represents decimal numbers 0 to 9
only (the first 10 i/p combinations),
so the last 6 i/p combinations have
no meaning in BCD. Hence those
are don’t-care combinations.

• To obtain simplified Boolean

functions for the outputs we need
to construct 4 K-Maps separately to
represent 4 outputs (W,X,Y,Z) of the
circuit as a function of the 4 i/p
variables.

RVK-LDCO-2.7 139
 K-Maps for
BCD to
Excess-3
Code
Conversion

RVK-LDCO-2.7 140
Logic Diagram for BCD to Excess-3
Code Conversion

RVK-LDCO-2.7 141
Alternative Logic Diagram for
BCD To Excess-3 Conversion
 Alternative Logic Diagram for BCD to
Excess-3 Code Conversion
• For a 4-bit BCD number, the inputs A,B,C,D can be expressed as
variables B3,B2,B1,B0 respectively.
• Similarly, the equivalent outputs W,X,Y,Z for an Excess-3 number
can be expressed as variables E3,E2,E1,E0 respectively.
E3 = B3+B2(B0+ B1)
E2 = B2’ B1 + B2’B0 + B2 B1’ B0’
= B2’(B1 + B0) + B2 (B1+ B0)’
= B2Å (B1 + B0)
E1= B1 B0 + B1’ B0’
= B 1ꙩ B 0

E0=B0’ RVK-LDCO-2.7 143

Alternative Logic Diagram for BCD to
Excess-3 Code Conversion (cont..)

RVK-LDCO-2.7 144
Thank You!

RVK-LDCO-2.7 145