M95640, M95320

M95160, M95080
64/32/16/8 Kbit Serial SPI Bus EEPROM
With High Speed Clock
PRELIMINARY DATA

■ SPI Bus Compatible Serial Interface

■ Supports Positive Clock SPI Modes
■ 5 MHz Clock Rate (maximum)
■ Single Supply Voltage:
– 4.5V to 5.5V for M95xxx 8 14
– 2.7V to 5.5V for M95xxx-V
– 2.5V to 5.5V for M95xxx-W 1 1
– 1.8V to 3.6V for M95xxx-R
PSDIP8 (BN) TSSOP14 (DL)
■ Status Register 0.25 mm frame 169 mil width
■ Hardware and Software Protection of the Status
Register
■ BYTE and PAGE WRITE (up to 32 Bytes)
8
■ Self-Timed Programming Cycle
■ Adjustable Size Read-Only EEPROM Area 1
■ Enhanced ESD Protection SO8 (MN)
150 mil width
■ 100,000 Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum)

DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are fabricated with STMi-
croelectronics’ High Endurance, Double
Polysilicon, CMOS technology. This guarantees Figure 1. Logic Diagram
an endurance typically well above one hundred
VCC

Table 1. Signal Names

C Serial Clock D Q

D Serial Data Input C

Q Serial Data Output S M95xxx

S Chip Select W

W Write Protect HOLD

HOLD Hold

VCC Supply Voltage

VSS
VSS Ground AI01789C

June 1999 1/19

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M95640, M95320, M95160, M95080

Figure 2A. DIP Connections Figure 2C. TSSOP Connections

M95128

M95xxx S 1 14 VCC
Q 2 13 HOLD
S 1 8 VCC
NC 3 12 NC
Q 2 7 HOLD
NC 4 11 NC
W 3 6 C
NC 5 10 NC
VSS 4 5 D
W 6 9 C
AI01790C
VSS 7 8 D
AI02346

Note: 1. NC = Not Connected

Figure 2B. SO Connections thousand Erase/Write cycles, with a data retention

of 40 years. The memories are organised as 8K x
8 bits and 4K x 8 bits (M95640, M95320) and 2K x
8 bits and 1K x 8 bits (M95160, M95080), and op-
erate down to 2.5 V (for the -W version of each de-
M95xxx vice), and down to 1.8 V (for the -R version of each
device).
S 1 8 VCC The M95640, M95320 and M95160, M95080 are
Q 2 7 HOLD available in Plastic Dual-in-Line, Plastic Small Out-
W 3 6 C line and Thin Shrink Small Outline packages.
VSS 4 5 D Each memory device is accessed by a simple se-
AI01791C rial interface that is SPI bus compatible. The bus
signals are C, D and Q, as shown in Table 1 and
Figure 3.
The device is selected when the chip select input
(S) is held low. Communications with the chip can
be interrupted using the hold input (HOLD).

Table 2. Absolute Maximum Ratings 1

Symbol Parameter Value Unit
TA Ambient Operating Temperature -40 to 125 °C
TSTG Storage Temperature -65 to 150 °C
PSDIP8: 10 sec 260
TLEAD Lead Temperature during Soldering SO8: 40 sec 215 °C
TSSOP14: t.b.c. t.b.c.
VO Output Voltage Range -0.3 to VCC+0.6 V
VI Input Voltage Range -0.3 to 6.5 V
VCC Supply Voltage Range -0.3 to 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 2 4000 V

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

2/19
 M95640, M95320, M95160, M95080

Figure 3. Microcontroller and Memory Devices on the SPI Bus

SPI Interface with D

(CPOL, CPHA) = Q
('0', '0') or ('1', '1')
C

Master
(ST6, ST7, ST9, C Q D C Q D C Q D
ST10, Others)
M95xxx M95xxx M95xxx

CS3 CS2 CS1 S S S

AI01958B

SIGNAL DESCRIPTION (though not to the WIP and WEL bits, which are
Serial Output (Q) set or reset by the device internal logic).
The output pin is used to transfer data serially out Bit 7 of the status register (as shown in Table 5) is
of the Memory. Data is shifted out on the falling the Status Register Write Disable bit (SRWD).
edge of the serial clock. When this is set to 0 (its initial delivery state) it is
possible to write to the status register if the WEL
Serial Input (D) bit (Write Enable Latch) has been set by the
The input pin is used to transfer data serially into WREN instruction (irrespective of the level being
the device. Instructions, addresses, and the data applied to the W input).
to be written, are each received this way. Input is
When bit 7 (SRWD) of the status register is set to
latched on the rising edge of the serial clock. 1, the ability to write to the status register depends
Serial Clock (C) on the logic level being presented at pin W:
The serial clock provides the timing for the serial – If W pin is high, it is possible to write to the sta-
interface (as shown in Figure 4). Instructions, ad- tus register, after having set the WEL bit using
dresses, or data are latched, from the input pin, on the WREN instruction (Write Enable Latch).
the rising edge of the clock input. The output data – If W pin is low, any attempt to modify the status
on the Q pin changes state after the falling edge of
register is ignored by the device, even if the
the clock input.
WEL bit has been set. As a consequence, all the
Chip Select (S) data bytes in the EEPROM area, protected by
When S is high, the memory device is deselected, the BPn bits of the status register, are also hard-
and the Q output pin is held in its high impedance ware protected against data corruption, and ap-
state. Unless an internal write operation is under- pear as a Read Only EEPROM area for the
way, the memory device is placed in its stand-by microcontroller. This mode is called the Hard-
power mode. ware Protected Mode (HPM).
After power-on, a high-to-low transition on S is re- It is possible to enter the Hardware Protected
quired prior to the start of any operation. Mode (HPM) either by setting the SRWD bit after
Write Protect (W) pulling low the W pin, or by pulling low the W pin
after setting the SRWD bit.
The protection features of the memory device are
summarized in Table 3. The only way to abort the Hardware Protected
Mode, once entered, is to pull high the W pin.
The hardware write protection, controlled by the W
pin, restricts write access to the Status Register If W pin is permanently tied to the high level, the
Hardware Protected Mode is never activated, and
the memory device only allows the user to protect

3/19
M95640, M95320, M95160, M95080

Figure 4. Data and Clock Timing

CPOL CPHA

0 0 C

1 1 C

D or Q MSB LSB

AI01438

a part of the memory, using the BPn bits of the sta- OPERATIONS
tus register, in the Software Protected Mode All instructions, addresses and data are shifted se-
(SPM). rially in and out of the chip. The most significant bit
Hold (HOLD) is presented first, with the data input (D) sampled
The HOLD pin is used to pause the serial commu- on the first rising edge of the clock (C) after the
nications between the SPI memory and controller, chip select (S) goes low.
without losing bits that have already been decoded Every instruction starts with a single-byte code, as
in the serial sequence. For a hold condition to oc- summarised in Table 4. This code is entered via
cur, the memory device must already have been the data input (D), and latched on the rising edge
selected (S = 0). The hold condition starts when of the clock input (C). To enter an instruction code,
the HOLD pin is held low while the clock pin (C) is the product must have been previously selected (S
also low (as shown in Figure 14). held low). If an invalid instruction is sent (one not
During the hold condition, the Q output pin is held contained in Table 4), the chip automatically dese-
in its high impedance state, and the levels on the lects itself.
input pins (D and C) are ignored by the memory Write Enable (WREN) and Write Disable (WRDI)
device. The write enable latch, inside the memory device,
It is possible to deselect the device when it is still must be set prior to each WRITE and WRSR oper-
in the hold state, thereby resetting whatever trans- ation. The WREN instruction (write enable) sets
fer had been in progress. The memory remains in this latch, and the WRDI instruction (write disable)
the hold state as long as the HOLD pin is low. To resets it.
restart communication with the device, it is neces- The latch becomes reset by any of the following
sary both to remove the hold condition (by taking events:
HOLD high) and to select the memory (by taking S
– Power on
low).
– WRDI instruction completion
– WRSR instruction completion
– WRITE instruction completion.

Table 3. Write Protection Control on the M95640, M95320, M95160, M95080

SRWD Data Bytes
W Mode Status Register
Bit
Protected Area Unprotected Area

0 or 1 0 Software Writeable (if the WREN Software write protected Writeable (if the WREN
Protected instruction has set the by the BPn of the status instruction has set the
1 1 (SPM) WEL bit) register WEL bit)

Hardware Hardware write protected Writeable (if the WREN

0 1 Protected Hardware write protected by the BPn bits of the instruction has set the
(HPM) status register WEL bit)

4/19
 M95640, M95320, M95160, M95080

Figure 5. Block Diagram

HOLD
High Voltage
W Control Logic Generator
S

D
I/O Shift Register
Q

Address Register Data

and Counter Register

Status
Register

An - 31 An Size of the
Read only
EEPROM
area
Y Decoder

32 Bytes

0000h 001Fh

X Decoder

AI01792C

Note: 1. The cell An represents the byte at the highest address in the memory

As soon as the WREN or WRDI instruction is re- ■ Repeated RDSR instructions (each one
ceived, the memory device first executes the in- consisting of S being taken low, C being clocked
struction, then enters a wait mode until the device 8 times for the instruction and 8 times for the
is deselected.
read operation, and S being taken high)
Read Status Register (RDSR)
■ A single, prolonged RDSR instruction
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during (consisting of S being taken low, C being
a Write operation. Indeed, when a Write is in clocked 8 times for the instruction and kept
progress, it is recommended that the value of the running for repeated read operations), as
Write-In-Progress (WIP) bit be checked. The value shown in Figure 6.
in the WIP bit (whose position in the status register
is shown in Table 5) can be continuously polled, The Write-In-Process (WIP) bit is read-only, and
before sending a new WRITE instruction. This can indicates whether the memory is busy with a Write
be performed in one of two ways:

5/19
M95640, M95320, M95160, M95080

Table 4. Instruction Set using the RDSR instruction. However, during a

Instruc Instruction
Write operation, the values of the non-volatile bits
tion
Description
Format
(SRWD, BP0, BP1) become frozen at a constant
value. The updated value of these bits becomes
WREN Set Write Enable Latch 0000 0110 available when a new RDSR instruction is execut-
ed, after completion of the write cycle. On the oth-
WRDI Reset Write Enable Latch 0000 0100
er hand, the two read-only bits (WEL, WIP) are
RDSR Read Status Register 0000 0101 dynamically updated during internal write cycles.
Using this facility, it is possible to poll the WIP bit
WRSR Write Status Register 0000 0001 to detect the end of the internal write cycle.
READ Read Data from Memory Array 0000 0011 Write Status Register (WRSR)
WRITE Write Data to Memory Array 0000 0010
The format of the WRSR instruction is shown in
Figure 7. After the instruction and the eight bits of
the status register have been latched-in, the inter-
Table 5. Status Register Format nal Write cycle is triggered by the rising edge of
the S line. This must occur after the falling edge of
b7 b0
the 16th clock pulse, and before the rising edge of
SRWD X X X BP1 BP0 WEL WIP the 17th clock (as indicated in Figure 7), otherwise
Note: 1. SRWD, BP0 and BP1 are Read and write bits.
the internal write sequence is not performed.
2. WEL and WIP are Read only bits. The WRSR instruction is used for the following:
■ to select the size of memory area that is to be

operation. A ’1’ indicates that a write is in progress, write-protected

and a ’0’ that no write is in progress. ■ to select between SPM (Software Protected
The Write Enable Latch (WEL) bit indicates the Mode) and HPM (Hardware Protected Mode).
status of the write enable latch. It, too, is read-only. The size of the write-protection area applies equal-
Its value can only be changed by one of the events ly in SPM and HPM. The BP1 and BP0 bits of the
listed in the previous paragraph, or as a result of status register have the appropriate value (see Ta-
executing WREN or WRDI instruction. It cannot be ble 6) written into them after the contents of the
changed using a WRSR instruction. A ’1’ indicates protected area of the EEPROM have been written.
that the latch is set (the forthcoming Write instruc-
tion will be executed), and a ’0’ that it is reset (and The initial delivery state of the BP1 and BP0 bits is
any forthcoming Write instructions will be ignored). 00, indicating a write-protection size of 0.
The Block Protect (BP0 and BP1) bits indicate the Software Protected Mode (SPM)
amount of the memory that is to be write-protect- The act of writing a non-zero value to the BP1 and
ed. These two bits are non-volatile. They are set BP0 bits causes the Software Protected Mode
using a WRSR instruction. (SPM) to be started. All attempts to write a byte or
During a Write operation (whether it be to the page in the protected area are ignored, even if the
memory area or to the status register), all bits of Write Enable Latch is set. However, writing is still
the status register remain valid, and can be read allowed in the unprotected area of the memory ar-

Figure 6. RDSR: Read Status Register Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

INSTRUCTION

STATUS REG. OUT STATUS REG. OUT

HIGH IMPEDANCE
Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

AI02031

6/19
 M95640, M95320, M95160, M95080

Table 6. Write Protected Block Size

Status Register Bits Array Addresses Protected
Protected Block
BP1 BP0 M95640 M95320 M95160 M95080
0 0 none none none none none
0 1 Upper quarter 1800h - 1FFFh 0C00h - 0FFFh 0600h - 07FFh 0300h - 03FFh
1 0 Upper half 1000h - 1FFFh 0800h - 0FFFh 0400h - 07FFh 0200h - 03FFh
1 1 Whole memory 0000h - 1FFFh 0000h - 0FFFh 0000h - 07FFh 0000h - 03FFh

ray and to the SRWD, BP1 and BP0 bits of the sta- Typical Use of HPM and SPM
tus register, provided that the WEL bit is first set. The W pin can be dynamically driven by an output
Hardware Protected Mode (HPM) port of a microcontroller. It is also possible,
The Hardware Protected Mode (HPM) offers a though, to connect it permanently to V SS (by a sol-
higher level of protection, and can be selected by der connection, or through a pull-down resistor).
setting the SRWD bit after pulling down the W pin The manufacturer of such a printed circuit board
or by pulling down the W pin after setting the can take the memory device, still in its initial deliv-
SRWD bit. The SRWD is set by the WSR instruc- ery state, and can solder it directly on to the board.
tion, provided that the WEL bit is first set. The set- After power on, the microcontroller can be instruct-
ting of the SRWD bit can be made independently ed to write the protected data into the appropriate
of, or at the same time as, writing a new value to area of the memory. When it has finished, the ap-
the BP1 and BP0 bits. propriate values are written to the BP1, BP0 and
SRWD bits, thereby putting the device in the hard-
Once the device is in the Hardware Protected
ware protected mode.
Mode, the data bytes in the protected area of the
memory array, and the content of the status regis- An alternative method is to write the protected da-
ter, are write-protected. The only way to re-enable ta, and to set the BP1, BP0 and SRWD bits, before
writing new values to the status register is to pull soldering the memory device to the board. Again,
the W pin high. This cause the device to leave the this results in the memory device being placed in
Hardware Protected Mode, and to revert to being its hardware protected mode.
in the Software Protected Mode. (The value in the If the W pin has been connected to V SS by a pull-
BP1 and BP0 bits will not have been changed). down resistor, the memory device can be taken
Further details of the operation of the Write Protect out of the hardware protected mode by driving the
pin (W) are given earlier, on page 3. W pin high, to override the pull-down resistor.
If the W pin has been directly soldered to V SS,
there is only one way of taking the memory device
out of the hardware protected mode: the memory

Figure 7. WRSR: Write Status Register Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

INSTRUCTION STATUS REG.

D 7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
Q
AI02282

7/19
M95640, M95320, M95160, M95080

Figure 8. Read EEPROM Array Operation Sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30

INSTRUCTION 16 BIT ADDRESS

D 15 14 13 3 2 1 0

DATA OUT
HIGH IMPEDANCE
Q 7 6 5 4 3 2 1 0
MSB

AI01793

Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

Table 7. Address Range Bits counter is automatically incremented to the next

Device M95640 M95320 M95160 M95080
higher address after each byte of data has been
shifted out. The data stored in the memory, at the
Address Bits A12-A0 A11-A0 A10-A0 A9-A0 next address, can be read by successive clock
Note: 1. Address bits up to b15 are treated as Don’t Care.
pulses. When the highest address is reached, the
address counter rolls over to “0000h”, allowing the
read cycle to be continued indefinitely. The read
device must be de-soldered from the board, and operation is terminated by deselecting the chip.
connected to external equipment in which the W The chip can be deselected at any time during
pin is allowed to be taken high. data output. If a read instruction is received during
a write cycle, it is rejected, and the memory device
Read Operation deselects itself.
The chip is first selected by holding S low. The se- Byte Write Operation
rial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in Before any write can take place, the WEL bit must
during the rising edge of the clock (C). be set, using the WREN instruction. The write
state is entered by selecting the chip, issuing three
The data stored in the memory, at the selected ad- bytes of instruction and address, and one byte of
dress, is shifted out on the Q output pin. Each bit data. Chip Select (S) must remain low throughout
is shifted out during the falling edge of the clock the operation, as shown in Figure 10. The product
(C) as shown in Figure 8. The internal address must be deselected just after the eighth bit of the

Figure 9. Write Enable Latch Sequence

0 1 2 3 4 5 6 7

HIGH IMPEDANCE
Q
AI02281

8/19
 M95640, M95320, M95160, M95080

Figure 10. Byte Write Operation Sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

INSTRUCTION 16 BIT ADDRESS DATA BYTE

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

HIGH IMPEDANCE
Q

AI01795

Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

data byte has been latched in, as shown in Figure during the self-timed write cycle, and a ‘0’ when
10, otherwise the write process is cancelled. As the cycle is complete, (at which point the write en-
soon as the memory device is deselected, the self- able latch is also reset).
timed internal write cycle is initiated. While the Page Write Operation
write is in progress, the status register may be
A maximum of 32 bytes of data can be written dur-
read to check the status of the SRWD, BP1, BP0,
WEL and WIP bits. In particular, WIP contains a ‘1’ ing one Write time, tW, provided that they are all to

Figure 11. Page Write Operation Sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

INSTRUCTION 16 BIT ADDRESS DATA BYTE 1

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

DATA BYTE 2 DATA BYTE 3 DATA BYTE N

D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0

AI01796

Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

9/19
M95640, M95320, M95160, M95080

the same page (see Figure 5). The Page Write op- POWER ON STATE
eration is the same as the Byte Write operation, After power-on, the memory device is in the follow-
except that instead of deselecting the device after ing state:
the first byte of data, up to 31 additional bytes can
– low power stand-by state
be shifted in (and then the device is deselected af-
ter the last byte). – deselected (after power-on, a high-to-low transi-
Any address of the memory can be chosen as the tion is required on the S input before any opera-
first address to be written. If the address counter tions can be started).
reaches the end of the page (an address of the – not in the hold condition
form xxxx xxxx xxx1 1111) and the clock contin- – the WEL bit is reset
ues, the counter rolls over to the first address of – the SRWD, BP1 and BP0 bits of the status reg-
the same page (xxxx xxxx xxx0 0000) and over- ister are unchanged from the previous power-
writes any previously written data. down (they are non-volatile bits).
As before, the Write cycle only starts if the S tran-
sition occurs just after the eighth bit of the last data INITIAL DELIVERY STATE
byte has been received, as shown in Figure 11. The device is delivered with the memory array in a
fully erased state (all data set at all “1’s” or FFh).
DATA PROTECTION AND PROTOCOL SAFETY The status register bits are initialized to 00h, as
To protect the data in the memory from inadvertent shown in Table 8.
corruption, the memory device only responds to
correctly formulated commands. The main securi-
ty measures can be summarised as follows: Table 8. Initial Status Register Format
– The WEL bit is reset at power-up. b7 b0
– S must rise after the eighth clock count (or mul- 0 0 0 0 0 0 0 0
tiple thereof) in order to start a non-volatile write
cycle (in the memory array or in the status reg-
ister).
– Accesses to the memory array are ignored dur-
ing the non-volatile programming cycle, and the
programming cycle continues unaffected.
– After execution of a WREN, WRDI, or RDSR in-
struction, the chip enters a wait state, and waits
to be deselected.
– Invalid S and HOLD transitions are ignored.

Table 9. Input Parameters1 (TA = 25 °C, f = 5 MHz)

Symbol Parameter Test Condition Min. Max. Unit
COUT Output Capacitance (Q) 8 pF
CIN Input Capacitance (other pins) 6 pF
Note: 1. Sampled only, not 100% tested.

10/19
 M95640, M95320, M95160, M95080

Table 10. DC Characteristics

(TA = 0 to 70 °C, -40 to 85 °C or -40 to 125 °C; VCC = 4.5 to 5.5 V)
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 5.5 V)
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.5 to 5.5 V)
(TA = 0 to 70 °C or -20 to 85 °C; VCC = 1.8 to 3.6 V)
Voltage Temp.
Symbol Parameter Test Condition Min. Max. Unit
Range Range
Input Leakage
ILI all all ±2 µA
Current
Output Leakage
ILO all all ±2 µA
Current
C = 0.1 VCC/0.9. VCC at 5 MHz,
4.5-5.5 6 4 mA
VCC = 5 V, Q = open
C = 0.1 VCC/0.9. VCC at 2 MHz,
4.5-5.5 3 4 mA
VCC = 5 V, Q = open
ICC Supply Current
C = 0.1 VCC/0.9. VCC at 5 MHz,
2.7-5.5 6 3 mA
VCC = 2.7 V, Q = open
C = 0.1 V CC/0.9. VCC at 2 MHz,
2.5-5.5 6 2 mA
VCC = 2.5 V, Q = open
C = 0.1 V CC/0.9. VCC at 1 MHz,
1.8-3.6 5 2 mA
VCC = 1.8 V, Q = open

4.5-5.5 6 S = VCC, VIN = VSS or VCC , VCC = 5 V 10 µA

Supply Current 4.5-5.5 3 S = VCC, VIN = VSS or VCC , VCC = 5 V 10 µA

ICC1
(Stand-by)
2.7-5.5 6 S = VCC, VIN = VSS or VCC , VCC = 2.7 V 2 µA
2.5-5.5 6 S = VCC, VIN = VSS or VCC , VCC = 2.5 V 2 µA
1.8-3.6 5 S = VCC, VIN = VSS or VCC , VCC = 1.8 V 1 µA
Input Low
VIL all all – 0.3 0.3 VCC V
Voltage
Input High
VIH all all 0.7 VCC VCC+1 V
Voltage
4.5-5.5 6 IOL = 2 mA, VCC = 5 V 0.4 V

4.5-5.5 3 IOL = 2 mA, VCC = 5 V 0.4 V

Output Low
VOL1 Voltage 2.7-5.5 6 IOL = 1.5 mA, VCC = 2.7 V 0.4 V

2.5-5.5 6 IOL = 1.5 mA, VCC = 2.5 V 0.4 V

1.8-3.6 5 IOL = 0.15 mA, VCC = 1.8 V 0.3 V

4.5-5.5 6 IOH = –2 mA, VCC = 5 V 0.8 VCC V

Output High 4.5-5.5 3 IOH = –2 mA, VCC = 5 V 0.8 VCC V

VOH1 Voltage
2.7-5.5 6 IOH = –0.4 mA, VCC = 2.7 V 0.8 VCC V
2.5-5.5 6 IOH = –0.4 mA, VCC = 2.5 V 0.8 VCC V
1.8-3.6 5 IOH = –0.1 mA, VCC = 1.8 V 0.8 VCC V
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

11/19
M95640, M95320, M95160, M95080

Table 11A. AC Characteristics

M95640, M95320, M95160, M95080
VCC=4.5 to 5.5 V
VCC=4.5 to 5.5 V
Symbol Alt. Parameter TA=0 to 70°C or Unit
TA=-40 to 125°C
-40 to 85°C
Min Max Min Max
fC fSCK Clock Frequency D.C. 5 D.C. 2 MHz

tSLCH tCSS1 S Active Setup Time 90 200 ns

tSHCH tCSS2 S Not Active Setup Time 90 200 ns

tSHSL tCS S Deselect Time 100 200 ns

tCHSH tCSH S Active Hold Time 90 200 ns

tCHSL S Not Active Hold Time 90 200 ns

tCH 1 tCLH Clock High Time 90 200 ns

tCL 1 tCLL Clock Low Time 90 200 ns

tCLCH 2 tRC Clock Rise Time 1 1 µs

tCHCL 2 tFC Clock Fall Time 1 1 µs

tDVCH tDSU Data In Setup Time 20 40 ns

tCHDX tDH Data In Hold Time 30 50 ns

tDLDH 2 tRI Data In Rise Time 1 1 µs

tDHDL 2 tFI Data In Fall Time 1 1 µs

tHHCH tCD Clock Low Hold Time after HOLD not Active 70 140 ns

tHLCH Clock Low Hold Time after HOLD Active 40 90 ns

tCLHL Clock Low Set-up Time before HOLD Active 0 0 ns

tCLHH Clock Low Set-up Time before HOLD not Active 0 0 ns

tSHQZ 2 tDIS Output Disable Time 100 250 ns

tCLQV tV Clock Low to Output Valid 60 150 ns

tCLQX tHO Output Hold Time 0 0 ns

tQLQH 2 tRO Output Rise Time 50 100 ns

tQHQL 2 tFO Output Fall Time 50 100 ns

tHHQX 2 tLZ HOLD High to Output Low-Z 50 100 ns

tHLQZ 2 tHZ HOLD Low to Output High-Z 100 250 ns

tW tWC Write Time 10 10 ms

Note: 1. tCH + tCL ≥ 1 / fC.
2. Value guaranteed by characterization, not 100% tested in production.

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 M95640, M95320, M95160, M95080

Table 11B. AC Characteristics

M95xxx-V M95xxx-W M95xxx-R
VCC=2.7 to 5.5 V VCC=2.5 to 5.5 V VCC=1.8 to 3.6 V
Symbol Alt. Parameter TA=0 to 70°C or TA=0 to 70°C or TA=0 to 70°C or Unit
-40 to 85°C -40 to 85°C -20 to 85°C
Min Max Min Max Min Max
fC fSCK Clock Frequency D.C. 5 D.C. 2 D.C. 1 MHz

tSLCH tCSS1 S Active Setup Time 90 200 400 ns

tSHCH tCSS2 S Not Active Setup Time 90 200 400 ns

tSHSL tCS S Deselect Time 100 200 300 ns

tCHSH tCSH S Active Hold Time 90 200 400 ns

tCHSL S Not Active Hold Time 90 200 400 ns

tCH 1 tCLH Clock High Time 90 200 400 ns

tCL 1 tCLL Clock Low Time 90 200 400 ns

tCLCH 2 tRC Clock Rise Time 1 1 1 µs

tCHCL 2 tFC Clock Fall Time 1 1 1 µs

tDVCH tDSU Data In Setup Time 20 40 60 ns

tCHDX tDH Data In Hold Time 30 50 100 ns

tDLDH 2 tRI Data In Rise Time 1 1 1 µs

tDHDL 2 tFI Data In Fall Time 1 1 1 µs

Clock Low Hold Time after HOLD

tHHCH tCD 70 140 350 ns
not Active
Clock Low Hold Time after HOLD
tHLCH 40 90 200 ns
Active
Clock Low Set-up Time before
tCLHL 0 0 0 ns
HOLD Active
Clock Low Set-up Time before
tCLHH 0 0 0 ns
HOLD not Active

tSHQZ 2 tDIS Output Disable Time 100 250 500 ns

tCLQV tV Clock Low to Output Valid 60 150 380 ns

tCLQX tHO Output Hold Time 0 0 0 ns

tQLQH 2 tRO Output Rise Time 50 100 200 ns

tQHQL 2 tFO Output Fall Time 50 100 200 ns

tHHQX 2 tLZ HOLD High to Output Low-Z 50 100 250 ns

tHLQZ 2 tHZ HOLD Low to Output High-Z 100 250 500 ns

tW tWC Write Time 10 10 10 ms

Note: 1. tCH + tCL ≥ 1 / fC.
2. Value guaranteed by characterization, not 100% tested in production.

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M95640, M95320, M95160, M95080

Table 12. AC Measurement Conditions Figure 12. AC Testing Input Output Waveforms
Input Rise and Fall Times ≤ 50 ns
0.8VCC
Input Pulse Voltages 0.2VCC to 0.8VCC 0.7VCC

Input and Output Timing 0.3VCC

0.3VCC to 0.7VCC 0.2VCC
Reference Voltages
AI00825
Output Load CL = 100 pF
Note: 1. Output Hi-Z is defined as the point where data is no long-
er driven.

Figure 13. Serial Input Timing

tSHSL

tCHSL tSLCH tCHSH tSHCH

tDVCH tCHCL

tCHDX tCLCH

D MSB IN LSB IN

tDLDH
tDHDL
HIGH IMPEDANCE
Q

AI01447

Figure 14. Hold Timing

tHLCH

tCLHL tHHCH

tCLHH

tHLQZ tHHQX

HOLD

AI01448

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 M95640, M95320, M95160, M95080

Figure 15. Output Timing

tCH

tCLQV tCL tSHQZ

tCLQX

Q LSB OUT

tQLQH
tQHQL

D ADDR.LSB IN

AI01449B

ORDERING INFORMATION
The notation used for the device number is as shown in Table 13. For a list of available options (speed,
package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office
nearest to you.

Table 13. Ordering Information Scheme

Example: M95640 – W MN 6 T

Memory Capacity4 Option

640 64 Kbit (8K x 8) with positive clock strobe T Tape and Reel Packing
320 32 Kbit (4K x 8) with positive clock strobe
160 16 Kbit (2K x 8) with positive clock strobe Temperature Range
080 8 Kbit (1K x 8) with positive clock strobe 1 0 °C to 70 °C
1
5 –20 °C to 85 °C
6 –40 °C to 85 °C
Operating Voltage 32 –40 °C to 125 °C
blank 4.5 V to 5.5 V
V 2.7 V to 5.5 V Package
W 2.5 V to 5.5 V BN PSDIP8 (0.25 mm frame)

R3 1.8 V to 3.6 V MN SO8 (150 mil width)

DL5 TSSOP14 (169 mil width)

Note: 1. Temperature range available only on request.
2. Produced with High Reliability Certified Flow (HRCF), in VCC range 4.5 V to 5.5 V only.
3. The -R version (VCC range 1.8 V to 3.6 V) only available in temperature ranges 5 or 1.
4. All devices use a positive clock strobe: Data In is strobed on the rising edge of the clock (C) and Data Out is synchronised from the
falling edge of the clock.
5. TSSOP14, 169 mil width, package is available for the M95640 series only.

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M95640, M95320, M95160, M95080

Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394
L 3.00 3.80 0.118 0.150
N 8 8

Figure 16. PSDIP8 (BN)

A2 A

A1 L
B e1 C
B1 eA
D eB

E1 E

1
PSDIP-a

Note: 1. Drawing is not to scale.

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 M95640, M95320, M95160, M95080

Table 15. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N 8 8
CP 0.10 0.004

Figure 17. SO8 narrow (MN)

h x 45˚

A
C
B
e CP

E H
1

A1 α L

SO-a

Note: 1. Drawing is not to scale.

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M95640, M95320, M95160, M95080

Table 16. TSSOP14 - 14 lead Thin Shrink Small Outline

mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.10 0.043
A1 0.05 0.15 0.002 0.006
A2 0.85 0.95 0.033 0.037
B 0.19 0.30 0.007 0.012
C 0.09 0.20 0.004 0.008
D 4.90 5.10 0.193 0.197
E 6.25 6.50 0.246 0.256
E1 4.30 4.50 0.169 0.177
e 0.65 – – 0.026 – –
L 0.50 0.70 0.020 0.028
α 0° 8° 0° 8°
N 14 14
CP 0.08 0.003

Figure 18. TSSOP14 (DL)

DIE
N
C

E1 E

1 N/2

A1
A A2 L

CP B e
TSSOP

Note: 1. Drawing is not to scale.

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 M95640, M95320, M95160, M95080

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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19/19
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