Scribd
Upload
50 views13 pages

Lab 6

Uploaded by

Saim Ashraf
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
50 views13 pages

Lab 6

Uploaded by

Saim Ashraf
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 13

Digital Logic Design

Lab report 6

Submitted by
M SAIM ASHRAF
Registration No:
FA21-BEE-128
Submitted to
DR ADNAN QURESHI
Lab# 06 Xilinx ISE Design Flow with FPGA

Pre lab:
Task 1(a):
K-map:
For variable W=A
For Variable X= A xor B:

For Variable Y= C xor B:


For Variable Z= C xor D:

Task 1(b):
Gate level Circuit Diagram of a simplified Function:
In Lab Task:
Gate level Code for binary to Gray Converter:

Verilog Code:
Test Bench:
Behavior Test:

Time graph of Gate Level code


Behavioral Model for binary to gray converter:
Verilog Code:
Behavioral code for Binary to Gray code converter
Test Bench:
Behavior Test:

Time graph for binary to gray code converter |


behavioral code

Post Lab:
Resource utilization and Critical path delay of In lab 1 and 2:

Resource utilization of Gatelevel BINARY to GRAY converter


Time Delay summary of Gate level BINARY to GRAY converter

Resource utilization summary of behavioral code of BINARY to GRAY converter

Time delay summary of behavioral code of BINARY to GRAY converter


Critical Analysis:
In this lab 6 we learned how to convert Binary codes into the gray codes, for this
we first derived the equations for it using the automated tool known as K-Map
Minimizer and then we simply implemented the simplified circuit diagram on
proteus and at the last we did the same conversion of binary codes to gray codes
using the XILINX ISE and synthesized it in the HDL and wrote the Gate level and
Behavioral Model codes for both the tasks and we also learned the time delay
summary and the resource utilization of the lab project as well.

You might also like