CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS

Chapter Outline
8.1 The CMOS Differential Pair
8.2 Small-Signal Operations of the MOS Differential Pair
8.3 The BJT Differential Pair
8.4 Other Non-ideal Characteristics of the Differential Amplifier
8.5 The Differential Amplifier with Active Load

NTUEE Electronics – L.H. Lu 8-1

 8.1 The MOS Differential Pair

The differential pair (differential amplifier) configuration

Widely used building block in analog integrated circuit design
 Performance depends critically on the matching of the devices
 Utilizes more components than single-ended circuits
 Well suited for IC fabrication
Advantages of using differential pair
 Less sensitive to noise and interference than single-ended circuits
 Bias is provided without the need for bypass and coupling capacitors
The CMOS differential pair
The design philosophy for ICs is different from that of discrete-component circuits
 Two matched transistors are used
 Identical device parameters for Q1 and Q2
(kn, Vt, and even layout)
 The source terminals are connected together
 Biased by a constant-current source
 Resistive loads are used for illustration
 Differential input at the gate terminals
 Differential output at the drain terminals

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Operation with a common-mode input voltage
Circuit analysis
 Both inputs are connected to a common-mode voltage VCM
 The differential pair Q1 and Q2 are in saturation
 The current divides equally due to device matching
𝐼 1 𝑊
= 𝑘 (𝑉 −𝑉)
2 2 𝐿
𝐼
𝑉 =𝑉 −𝑉 =𝑉 − −𝑉
𝑘 (𝑊/𝐿)

𝐼
𝑉 =
𝑘 (𝑊/𝐿)
𝐼
𝑉 =𝑉 =𝑉 − 𝑅
2
 Output does not respond to VCM
 VOV is defined at ID1 = ID2 = I/2
Input common-mode range (ICMR):
 The range of VCM for proper operation
 Both Q1 and Q2 should be in saturation
VCM,max = VDD–RDI/2+Vt
VCM,min = -VSS+VCS(headroom for current source)+VGS

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Operation with a differential input voltage
A difference voltage vid exists between the input terminals
The current of Q1 is different from that of Q2 as vGS1  vGS2
The overall current I remains unchanged
The value of vid at which the entire bias current I is steered into Q1 is
2𝐼
𝑣 =𝑉 + = 𝑉 + 2𝑉
𝑘 (𝑊/𝐿)
𝑣 =𝑉

𝑣 , = 2𝑉

The current I can be steered from one transistor to the other

by varying vid in the range − 2𝑉 < 𝑣 < 2𝑉
Differential pair as a linear amplifier
 Keep the differential input voltage vid small
 The currents of the transistor pair become I/2  I
 I is linearly proportional to vid for small-signal operation
 A differential output voltage is taken between the two drains as 2IRD

NTUEE Electronics – L.H. Lu 8-4

Large-signal operation
2𝑖 2𝑖
𝑣 =𝑣 −𝑣 = −
𝑘 (𝑊/𝐿) 𝑘 (𝑊/𝐿)
𝐼=𝑖 +𝑖
Drain currents of the differential pair

𝐼 𝐼 𝑣 𝑣
𝑖 = + 1−
2 𝑉 2 2𝑉

𝐼 𝐼 𝑣 𝑣
𝑖 = − 1−
2 𝑉 2 2𝑉

Normalized transfer characteristics

 Nonlinear transfer characteristics
 The overdrive voltage VOV is calculated as
iD1 = iD2 = I /2
Small-signal approximation
 Linear I-V characteristics for small vid
𝐼 𝐼 𝑣
𝑖 ≈ +
2 𝑉 2
𝐼 𝐼 𝑣
𝑖 ≈ −
2 𝑉 2
 Transconductance: Gm  iD/vid = I/VOV

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Linearity of the differential pair
The linearity of the differential pair can be increased by increasing the overdrive voltage VOV
Linearity-transconductance trade-off:
 Smaller aspect ratio (W/L) of Q1 and Q2 at fixed bias current I
 Resulting in smaller transconductance and smaller gain

Linearity-power trand-off:
 Larger bias current I with fixed aspect ratio
 Resulting in larger transconductance and gain at the cost of higher power dissipation

NTUEE Electronics – L.H. Lu 8-6

 8.2 Small-Signal Operation of the MOS Differential Pair

Small-signal analysis technique for differential amplifiers

The ac inputs are defined as vg1 and vg2 at the differential pair based on the small-signal model
It can also be treated as superposition of differential (vid) and common-mode (vicm) voltages
The circuit analysis can be divided into differential and common-mode operations

ac equivalent circuit

VD + vo1 VD + vo1 vo1 vo1

VCM + vg1 VCM + vg1 vg1 vg2

𝑣 =𝑣 −𝑣
𝑣 +𝑣
𝑣 =
2
Differential gain
The differential input signal (vid) is applied in a complementary (or balanced) manner
Single-ended outputs (vo1 and vo2): output taken between one of the drains and ground
Differential output (vod): output taken between the two drains
Differential gain is defined as the ratio of vod to vid:
𝑣 𝑣 −𝑣
𝐴 ≡ =
𝑣 𝑣 −𝑣

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Small-signal circuit analysis (simplified model):
𝑣 𝑔 𝑣
𝑖= =
1/𝑔 + 1/𝑔 2
→𝑣 =0
 Differential gain:
𝑖 𝑖
𝑔 𝑅 𝑣
𝑣 = −𝑖𝑅 = −
2
𝑔 𝑅 𝑣
𝑣 = 𝑖𝑅 =
2 𝑣 = 0V
𝑣 𝑣 −𝑣
𝐴 ≡ = =𝑔 𝑅 𝑣
𝑣 𝑣 𝑖=
1 1
Small-signal circuit analysis (with ro and RSS): 𝑔
+
𝑔
𝑣 𝑣 −𝑣 𝑣 𝑣 −𝑣
𝑔 −𝑣 + +𝑔 − −𝑣 + =0
2 𝑟 2 𝑟
𝑣 𝑣 −𝑣 𝑣
𝑔 −𝑣 + + =0
2 𝑟 𝑅
𝑣 𝑣 −𝑣 𝑣
𝑔 − −𝑣 + + =0
2 𝑟 𝑅
𝑟 𝑟
→𝑣 =0
 Differential gain:
𝑣
𝑔 /2
𝑣 = −𝑣 = 𝑣
1/𝑟 + 1/𝑅 𝑅
𝑣 𝑣 −𝑣
𝐴 ≡ = = 𝑔 𝑅 ||𝑟
𝑣 𝑣
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The differential half-circuit
Virtual ground:
 Differential operation for a symmetrical circuit
 The voltage at the nodes on the symmetrical axis (the joint source connection) must be zero
 A signal ground is established at the source terminals without a large bypass capacitor
The differential half-circuit analysis:
 A technique useful to simplify the ac analysis of fully differential circuits
 All the nodes on symmetric line are considered ac ground
 The complete circuit can typically be separated into two half-circuits
 Performance of a symmetrical differential circuit can be evaluated by half-circuit analysis

𝑣
𝐴 ≡ = 𝑔 (𝑅 ||𝑟 ) ≈ 𝑔 𝑟
𝑣

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The differential amplifier with current-source load

𝑣
𝐴 ≡ =𝑔 (𝑟 ||𝑟 )
𝑣 𝑣
𝐴 ≡ =𝑔 (𝑅 | 𝑅 ≈𝑔 (𝑔 𝑟 𝑟 ||𝑔 𝑟 𝑟 )
𝑣

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Example for differential half-circuit analysis

𝑣 𝑔 𝑅
𝐴 ≡ = 𝑅 ||
𝑣 1+𝑔 𝑅 2

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Common-mode gain of a differential pair
A differential pair with ideal current source
 The output resistance (RSS) is infinite
 Drain currents of Q1 and Q2 do not change with the input
common-mode voltage VCM
 The single-ended outputs remain unchanged
 The differential output voltage and common-mode gain are zero
A differential pair with a practical current source
 The output resistance (RSS) is finite
 Drain currents of Q1 and Q2 change simultaneously with VCM
 The singled-ended outputs vary with VCM
 The differential output voltage and common-mode gain are zero
The differential pair rejects common-mode signals regardless the
value of RSS, resulting in zero differential output voltage
1 𝑣
𝑣 =𝑖 + 2𝑖𝑅 →𝑖=
𝑔 1
+ 2𝑅
𝑔
𝑅 𝑅
𝑣 =𝑣 =− 𝑣 ≈− 𝑣
1 2𝑅
𝑔 + 2𝑅
𝑣 =𝑣 −𝑣 =0

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Common-mode half-circuit
The common-mode half-circuit analysis:
 Circuit analysis technique for symmetrical circuit with common-mode operation
 The symmetrical points are equal potential
 No current flowing across the symmetrical line and can be treated as open
 The complete circuit can be typically divided into two half-circuits
 The performance can be evaluated by common-mode half-circuit to simplify the analysis

𝑔 𝑅 𝑅
𝑣 =𝑣 =− 𝑣 ≈− 𝑣
1 + 2𝑔 𝑅 2𝑅

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Complete small-signal analysis:
AC equivalent circuit: Differential operation: Common-mode operation:

vg1 vg2 𝑣 𝑣 𝑣 𝑣
−
2 2

RSS RSS RSS

𝑔 𝑅 𝑣 𝑅
𝑣 =𝑣 −𝑣 𝑣 =− 𝑣 ≈− 𝑣
2 2𝑅
𝑣 +𝑣 𝑔 𝑅 𝑣 𝑅
𝑣 = 𝑣 = 𝑣 ≈− 𝑣
2 2 2𝑅
𝑣 −𝑣 𝑣 −𝑣
𝐴 = =𝑔 𝑅 𝐴 = =0
𝑣
Overall response: 𝑣
𝑔 𝑅 𝑅
𝑣 =𝑉 _ − 𝑣 − 𝑣
2 2𝑅
𝑔 𝑅 𝑅
𝑣 =𝑉 _ + 𝑣 − 𝑣
2 2𝑅

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Device mismatch in the differential pair RD+RD RD
Mismatch between Q1 and Q2 or RD1 and RD2 leads to non-ideal effects
Assume RD1 = RD+RD and RD2 = RD for resistance mismatch
Operation with a differential input voltage vid:
Q1 Q2
𝑣 1
= 𝑖 + 𝑅 (𝑖 + 𝑖 ) i1 i2
2 𝑔
vid/2 -vid/2
𝑣 1
− = 𝑖 + 𝑅 (𝑖 + 𝑖 )
2 𝑔
𝑣 i1+i2
→ 𝑖 = −𝑖 = 𝑔
2
∆𝑅
→𝑣 =𝑣 −𝑣 =𝑔 𝑅 1+ 𝑣
2𝑅
∆𝑅
→𝐴 =𝑔 𝑅 1+ ≈𝑔 𝑅
2𝑅

 The mismatch ∆𝑅 /𝑅 is generally small in modern integrated circuit technology

 The differential gain Ad does not change significantly due to mismatch
 Analysis of device mismatch is typically focused on non-ideal effects in common-mode operation

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Effect of resistance mismatch RD+RD RD
Common-mode gain:
1 1
𝑣 = 𝑖 + 𝑅 (𝑖 + 𝑖 ) = 𝑖 + 𝑅 (𝑖 + 𝑖 )
𝑔 𝑔
𝑣
→𝑖 =𝑖 = Q1 Q2
1
+ 2𝑅 i1 i2
𝑔
vicm vicm
𝑅 ∆𝑅
→𝑣 =𝑣 −𝑣 = 𝑣
1 𝑅
𝑔 + 2𝑅
i1+i2
𝑣 𝑅 ∆𝑅
→𝐴 ≡ ≈
𝑣 2𝑅 𝑅

 For a current source with finite RSS, mismatch in RD causes a finite common-mode gain Acm
Common-mode rejection ratio (CMRR):
 CMRR is defined as the ratio of differential-mode gain and the common-mode gain
 A measure of the effectiveness of the differential pair in rejecting common-mode interference
 Is given by CMRR = |Ad/Acm| and usually expressed in decibels CMRR (dB) = 20log|Ad/Acm|
CMRR of the differential amplifier with respect to the resistance mismatch
𝐴 2𝑔 𝑅
C𝑀𝑅𝑅 = =
𝐴 ∆𝑅 /𝑅
 Utilizes a bias current source with a high output resistance
 High degree of matching between the drain resistance

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Effect of transconductance mismatch RD RD
Mismatch exists between Q1 and Q2
∆𝑔
𝑔 =𝑔 +
2
∆𝑔
𝑔 =𝑔 − Q1 Q2
2
i1 i2
Common-mode gain: vicm vicm
1 1
𝑣 = 𝑖 +𝑅 𝑖 +𝑖 = 𝑖 +𝑅 𝑖 +𝑖
𝑔 𝑔
𝑔 𝑅 i1+i2
𝑣 = −𝑖 𝑅 =− 𝑣
1+ 𝑔 +𝑔 𝑅
𝑔 𝑅
𝑣 = −𝑖 𝑅 =− 𝑣
1+ 𝑔 +𝑔 𝑅
∆𝑔 𝑅
→𝑣 =𝑣 −𝑣 = 𝑣
1 + 2𝑔 𝑅
𝑣 𝑅 ∆𝑔
→𝐴 ≡ ≈
𝑣 2𝑅 𝑔
Common-mode rejection ratio:
𝐴 2𝑔 𝑅
𝐶𝑀𝑅𝑅 ≡ ≈
𝐴 ∆𝑔 /𝑔

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 8.3 The BJT Differential Pair

Circuit configuration
Two identical BJT transistors Q1 and Q2 with emitters jointed together
Biased with a current source
Input common-mode range
Allowable range of VCM for Q1 and Q2 in active mode
𝐼
𝑉 ≈ 𝑉 + 0.5V = 𝑉 − 𝛼𝑅 + 0.5V
2
𝑉 = −𝑉 +𝑉 +𝑉

Common-mode operation
Common-mode input voltage VCM for vB1 and vB2
Single-ended output voltage:
𝑣 =𝑉 − 𝛼𝑅 𝐼/2
𝑣 =𝑉 − 𝛼𝑅 𝐼/2
Differential output voltage:
𝑣 =𝑣 −𝑣 =0
Finite output resistance of the current source
 Single-ended output change with VCM
 Differential output is still zero

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Large-signal operation
Transfer characteristics
𝐼 ( )/ 𝐼
𝑖 𝑒
=𝛼 =𝑒 ( )/ 𝑖 =
1 + 𝑒𝑥𝑝(−𝑣 /𝑉 )
𝑖 𝐼 ( )/
𝑒
𝛼 𝐼
𝑖 =
𝑖 +𝑖 =𝐼 1 + 𝑒𝑥𝑝(𝑣 /𝑉 )
Normalized characteristics
 The bias current is divided equally for vid = 0
 Unequal current through Q1 and Q2 for vid  0
 A relatively small vid for complete current switching
 The linearity can be improved by emitter degeneration Re
 Transconductance and gain decrease due to emitter degeneration

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Small-signal operation

Small-signal current
 Differential pair: ic = gmvid/2
 Differential pair with emitter degeneration : ic = vid/(2re+2Re)  gmvid/2(1+gmRe)
Input differential resistance
 Differential pair: Rid  vid/ib = 2r
 Differential pair with emitter degeneration: Rid = ( +1)(2re+2Re)  2[Re+r(1+gmRe)]

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Differential gain

 Differential pair: Ad  vod/vid = gmRC

 Differential pair with emitter degeneration: Ad = RC/(re+Re)  gmRC/(1+gmRe)
 The differential amplifier can also be fed in a single-ended fashion
Equivalent circuit model

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Common-mode gain and CMRR
Differential pair with device matching:
𝛼𝑅
𝑣 =𝑣 =− 𝑣
𝑟 + 2𝑅
𝑣 =𝑣 −𝑣 =0

Differential pair with resistance mismatch:

𝑣 =𝑖 𝑟 + 𝑖 +𝑖 𝑅 = 𝑖 𝑟 + (𝑖 + 𝑖 )𝑅

𝑖 =𝑖 =𝑣 / 𝑟 + 2𝑅
𝛼𝑅
𝑣 =− 𝑣
𝑟 + 2𝑅
ie1 ie2
𝛼(𝑅 + ∆𝑅 )
𝑣 =− 𝑣 RD RD+RD
𝑟 + 2𝑅
𝛼∆𝑅
𝑣 =𝑣 −𝑣 =− 𝑣
𝑟 + 2𝑅
𝑣 𝛼∆𝑅 𝑅 ∆𝑅
𝐴 ≡ =− ≈− ie1 ie2
𝑣 𝑟 + 2𝑅 2𝑅 𝑅
2𝑔 𝑅
𝐶𝑀𝑅𝑅 =
∆𝑅 /𝑅 ie1+ie2

 High output resistance is desirable for current source

 Resistance mismatch for the load should be minimized

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 8.4 Other Non-ideal Characteristics of the Differential Amplifier

Input offset voltage of the MOS differential pair

Output dc offset voltage: the finite output voltage with both input grounded
Input offset voltage (VOS): the input referred offset voltage as the output offset divided by gain
 Output voltage becomes zero if VOS is applied between the inputs
 Its polarity can not be predetermined
Factors contribute to the dc offset voltage:
 Mismatch in load resistance RD
 Mismatch in aspect ratio (W/L)
 Mismatch in threshold voltage Vt

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Input offset voltage due to load resistance mismatch
𝑅 = 𝑅 + ∆𝑅 /2 𝑉 𝐼 ∆𝑅 𝑉 ∆𝑅
𝑉 = = =
𝑅 = 𝑅 − ∆𝑅 /2 𝑔 𝑅 2𝑔 𝑅 2 𝑅
Input offset voltage due to aspect ratio mismatch
𝑊 𝑊 1 𝑊 𝐼 ∆(𝑊/𝐿)
= + ∆ 𝐼 = 1+
𝐿 𝐿 2 𝐿 2 2(𝑊/𝐿) 𝑅 (𝐼 − 𝐼 ) 𝑉 ∆(𝑊/𝐿)
𝑉 = =
𝑊 𝑊 1 𝑊 𝑔 𝑅 2 (𝑊/𝐿)
𝐼 ∆(𝑊/𝐿)
= − ∆ 𝐼 = 1−
𝐿 𝐿 2 𝐿 2 2(𝑊/𝐿)
Input offset voltage due to threshold voltage mismatch
∆𝑉 𝑘 ∆𝑉 𝐼 ∆𝑉
𝑉 =𝑉 + 𝐼 = 𝑉 −𝑉 1− ≈ 1− 𝑅 (𝐼 − 𝐼 )
2 2 2(𝑉 − 𝑉 ) 2 𝑉 −𝑉 𝑉 = = ∆𝑉
∆𝑉 𝑔 𝑅
𝑉 =𝑉 − 𝑘 ∆𝑉 𝐼 ∆𝑉
2 𝐼 = 𝑉 −𝑉 1+ ≈ 1+
2 2(𝑉 − 𝑉 ) 2 𝑉 −𝑉

Input offset voltage:

 The three mismatch factors are uncorrelated

𝑉 ∆𝑅 𝑉 ∆(𝑊/𝐿)
𝑉 = + + ∆𝑉
2 𝑅 2 (𝑊/𝐿)
 To minimize the input offset voltage
Decrease overdrive voltage VOV
Minimize the device mismatch ratio

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Input offset voltage of the bipolar differential pair
Factors contribute to offset voltage
 Mismatch in load resistance RC
 Mismatch in junction area AE
 Mismatch in 
Input offset voltage due to load resistance mismatch
𝑅 = 𝑅 + ∆𝑅 /2 𝛼(𝐼/2)∆𝑅 ∆𝑅
𝑉 = =𝑉
𝑅 = 𝑅 − ∆𝑅 /2 𝑔 𝑅 𝑅
Input offset voltage due to emitter area mismatch
∆𝐼 𝐼 ∆𝐼
𝐼 =𝐼 + 𝐼 = 1+ 𝐼 ∆𝐼 𝑅 ∆𝐼
2 2 2𝐼
𝑉 =𝛼 =𝑉
∆𝐼 𝐼 ∆𝐼 2 𝐼 𝑔 𝑅 𝐼
𝐼 =𝐼 − 𝐼 = 1−
2 2 2𝐼
Input offset voltage:
 The factors are uncorrelated
∆𝑅 ∆𝐼
𝑉 =𝑉 +
𝑅 𝐼
 The offset voltage can be minimized by reducing the device mismatch ratios
 The input offset voltage for BJT (proportional to VT) is typically smaller than its MOS
counterpart (proportional to VOV)

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Input bias current and offset currents of the bipolar differential pair
Input bias current:
 Finite bias currents are required at the input terminals of BJT differential pair
 The input bias currents are simply the base current of the BJT transistors
𝐼
𝐼 =𝐼 =
2(𝛽 + 1)
Input offset current:
 Offset in the input bias currents due to device mismatch
 Mostly from the mismatch in 
∆𝛽 𝐼 1 𝐼 1 ∆𝛽
𝛽 =𝛽+ 𝐼 = ≈ 1−
2 2 𝛽 + 1 + ∆𝛽/2 2 𝛽 + 1 2𝛽 𝐼 ∆𝛽 ∆𝛽
∆𝛽 𝐼 1 𝐼 1 ∆𝛽 𝐼 = =𝐼
𝐼 = ≈ 1+ 2(𝛽 + 1) 𝛽 𝛽
𝛽 =𝛽−
2 2 𝛽 + 1 − ∆𝛽/2 2 𝛽 + 1 2𝛽

Comparison for MOS and bipolar differential pair

Bipolar differential pair typically has smaller input offset voltage
Bipolar differential pair suffers from input offset current

NTUEE Electronics – L.H. Lu 8-26

 8.5 The Differential Amplifier with Active Load

Differential to single-ended conversion

Differential pair with differential output
 Improved CMRR: suppress the influence of the common-mode interference
 Higher voltage gain: gain is increased by a factor or 2
Differential pair with single-ended output
 Certain applications require single-ended output
 A resistive load differential pair can simply provide the differential to single-ended conversion
The active-loaded MOS differential pair
 Utilizes a current mirror (Q3 and Q4) as the active load
 Provides single-ended output for the differential pair

NTUEE Electronics – L.H. Lu 8-27

Basic circuit operation
Quiescent point:
 Perfect matching case:
Bias current is equally divided for Q1 and Q2
The current of Q1 also flows through Q3
Current of Q3 is mirrored to Q4
All currents are identical (ID1 = ID2 = ID3 = ID4 = I/2)
The currents of Q2 and Q4 balance out
Zero output current to the following stage
Quiescent output voltage = VDD  VSG3
 Input common-mode range (ICMR):
ICMRmax = VDD – VSG3 + Vtn
ICMRmin = –VSS + VCS + VGS1
 Mismatch in the devices:
Nonzero net current at the output node
The current flows into the output resistances of Q2 and Q4
The output voltage deviates from VDDVSG3
Applying differential input voltage:
 A difference current between Q1 and Q2
 The net difference current exists at the output

NTUEE Electronics – L.H. Lu 8-28

Voltage gain of the active-loaded MOS differential pair
Transconductance: Gm = gm1
 The transconductance is evaluated by output current with v0 = 0 V
 The drain of Q3 is considered a low-impedance node and the voltage is relatively low vg3  0 V
 With vg3  v0 = 0 V, differential half circuit applies for Q1 and Q2 and source voltage is 0 V

𝑣 1 𝑔 𝑣
𝑣 = −𝑔 𝑟 𝑟 ≈−
2 𝑔 𝑔 2
𝑣 𝑔 𝑣 𝑣
𝑖 = −𝑔 𝑣 +𝑔 =𝑔 +𝑔 ≈𝑔 𝑣
2 𝑔 2 2
→𝐺 ≈𝑔 =𝑔

NTUEE Electronics – L.H. Lu 8-29

Output resistance: Ro  ro2||ro4

𝑟 +𝑅 1 1/𝑔 1
𝑅 = = + ≈
𝑔 𝑟 𝑔 𝑔 𝑟 𝑔
1 2𝑟
𝑅 =𝑅 +𝑟 +𝑔 𝑟 𝑅 == +𝑟 + ≈ 2𝑟
𝑔 𝑔
𝑣
𝑖=
𝑅
𝑣 2𝑣 𝑣
𝑖 =𝑖+𝑖+ = +
𝑟 𝑅 𝑟
𝑅 = 𝑟 ||𝑟

Differential gain: Ad = GmRo = gm1(ro2||ro4)  gmro/2

Circuit model for MOS differential amplifier with a current-mirror load

NTUEE Electronics – L.H. Lu 8-30

Common-mode gain and CMRR
The active-loaded CMOS differential pair has a high CMRR even with a single-ended output
Common-mode half-circuit is not applicable as the circuit is not symmetrical
Q1 and Q2 can be treated as two separated CS transistors with source degeneration

NTUEE Electronics – L.H. Lu 8-31

Common-mode gain: Acm  –1/(2gm3RSS)
2𝑅 ||𝑟
𝑣 = 𝑣 ≈𝑣
2𝑅 ||𝑟 + 1/𝑔
𝑣
𝑖 =
2𝑅
𝑖 1
𝐺 ≡ =
𝑣 2𝑅
𝑅 = 2𝑅 +𝑟 +𝑔 𝑟 (2𝑅 )

𝑅 = 2𝑅 +𝑟 +𝑔 𝑟 (2𝑅 )
1
𝑣 = −𝐺 𝑣 𝑅 ||𝑟 ||
𝑔
1
𝑖 =𝑔 𝑣 =𝑔 𝑣 = −𝑔 𝐺 𝑣 𝑅 |𝑟 |
𝑔
𝑖 =𝐺 𝑣
𝑅 ||𝑟 1
𝑣 = 𝑖 +𝑖 𝑅 ||𝑟 = −𝑣 1−𝑔 𝑅 ||𝑟 ||
2𝑅 𝑔
𝑣 𝑟 1 1
𝐴 ≡ ≈− ≈−
𝑣 2𝑅 1 + 𝑔 𝑟 2𝑔 𝑅

Common-mode rejection ratio: CMRR = gm1(ro2||ro4)(2gm3RSS)

NTUEE Electronics – L.H. Lu 8-32

The bipolar differential pair with active load
Circuit schematic:
 Bipolar differential pair Q1 and Q2
 Bipolar current mirror Q3 and Q4 as active load
 Constant current source for dc bias
 The bias current is equally divided for Q1 and Q2
Input resistance: Rid = 2r1
Transconductance: Gm  gm1
 Transconductance is evaluated by output current with vo = 0V
 Collector of Q3 is low-impedance node with vb3  oV
 Differential half circuit applies for Q1 and Q2 with emitter voltage = 0V

𝑣 𝑣
𝑣 = −𝑔 (𝑟 | 𝑟 |𝑟 ||𝑟 ) ≈ −𝑔 𝑟
2 2
𝑣
𝑔 𝑣 = −𝑔 𝑔 𝑟
2
𝑣 𝑣
𝑖 =𝑔 −𝑔 𝑣 = 𝑔 +𝑔 𝑔 𝑟
2 2
𝑖 1
𝐺 ≡ = 𝑔 +𝑔 𝑔 𝑟 ≈𝑔
𝑣 2

NTUEE Electronics – L.H. Lu 8-33

Output resistance (Ro):
𝑅 ≈𝑟 1+𝑔 𝑟 ||𝑟 ≈𝑟 1+𝑔 𝑟 ≈ 2𝑟
𝑣 𝑣
𝑖= =
𝑅 2𝑟
𝑣 𝑣 𝑣
𝑖 = 2𝑖 + = +
𝑟 𝑟 𝑟

𝑅 ≡ = 𝑟 ||𝑟

Differential gain:
𝑣 1
𝐴 ≡ = 𝐺 𝑅 = 𝑔 (𝑟 ||𝑟 ) ≈ 𝑔 𝑟
𝑣 2
Common-mode gain:
𝑣
𝑖 ≈𝑖 ≈
2𝑅
1
𝑣 = −𝑖 ||𝑟 ||𝑟 |𝑟
𝑔
𝑣 = −𝑟 𝑔 𝑣 +𝑖
𝑣 𝑟 1
𝐴 ≡ = 𝑔 ||𝑟 ||𝑟 |𝑟 −1
𝑣 2𝑅 𝑔
𝑟 2/𝑟 𝑟
≈− ≈−
2𝑅 𝑔 + 2/𝑟 𝛽 𝑅

CMRR:
𝐴 𝛽 𝑅 1
𝐶𝑀𝑅𝑅 ≡ =𝑔 (𝑟 ||𝑟 ) ≈ 𝛽𝑔 𝑅
𝐴 𝑟 2

NTUEE Electronics – L.H. Lu 8-34

Systematic input offset voltage
 Difference current between Q3 and Q4 due to finite 
 Net current at output for both input terminals grounded
 Input offset voltage to eliminate the output current
 This offset has nothing to do with device mismatch
𝐼 1
=
𝐼 1 + 2/𝛽
𝐼/2
𝐼 =𝛼
1 + 2/𝛽
𝐼 1 𝐼 2/𝛽 𝐼
∆𝑖 = 𝛼 1− =𝛼 ≈𝛼
2 1 + 2/𝛽 2 1 + 2/𝛽 𝛽
∆𝑖 2𝑉
𝑉 =− =−
𝐺 𝛽

 Improved current mirror can be used to reduce the systematic input offset

NTUEE Electronics – L.H. Lu 8-35