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EE203 Notes-Slides Liang-Hung-Lu Ch5

Electronics (King Fahd University of Petroleum and Minerals)

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CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS (MOSFETs)

Chapter Outline
5.1 Device Structure and Physical Operation
5.2 Current-Voltage Characteristics
5.3 MOSFET Circuits at DC
5.4 Applying the MOSFET in Amplifier Design
5.5 Small-Signal Operation and Models
5.6 Basic MOSFET Amplifier Configurations
5.7 Biasing in MOS Amplifier Circuits
5 8 Discrete-Circuit
5.8 Discrete Circuit MOS Amplifiers
5.9 The Body Effect and Other Topics

NTUEE Electronics – L. H. Lu 5-1

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5.1 Device Structure and Physical Operation

Device structure of MOSFET

“MOS” ≡ metal-oxide-semiconductor structure.

MOSFET is a four-terminal device: gate (G), source (S), drain (D) and body (B).
The device size (channel region) is specified by channel width (W) and channel length (L).
Two kinds of MOSFETs: n-channel (NMOS) and p-channel (PMOS) devices
The device structure is basically symmetric in terms of drain and source.
Source and drain terminals are specified by the operation voltage.

NTUEE Electronics – L. H. Lu 5-2

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Operation with zero gate voltage

The MOS structure form a parallel-plate plate capacitor with gate oxide layer in the middle.
Two pn junctions (S-B and D-B) are connected as back to back diodes.
The source and drain terminals are isolated by two depletion regions without conducting current.
The operating principles will be introduced by using the n-channel MOSFET as an example.
Creating a channel for current flow
Positive charges accumulate in gate as a positive voltage applies to gate electrode.
The electric field forms a depletion region by pushing holes in p-type substrate away from the surface.
Electrons start to accumulate on the substrate surface as gate voltage exceeds a threshold voltage Vt .
The induced n region thus forms a channel for current flow from drain to source.
source
The channel is created by inverting the substrate surface from p-type to n-type  inversion layer.
The field controls the amount of charge in the channel and determines the channel conductivity.

NTUEE Electronics – L. H. Lu 5-3

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Applying a small drain voltage

A positive vGS > Vt is used to induce the channel and it is called n-channel enhancement-type MOSFET.
Free electrons travel from source to drain through the induced n-channel due to a small vDS.
The resulting current iD flows from drain to source (opposite to the direction of the flow of negative charge).
The current is proportional to the number of carriers in the induced channel.
The channel is controlled by the effective voltage or overdrive voltage: vOV  vGS  Vt
The electron charge in the channel due to the overdrive voltage: |Q| = CoxWLvOV
Gate oxide capacitance Cox is defined as capacitance per unit area.
MOSFET can be approximated as a linear resistor in this region with a resistance value inversely
pproportional
p to the excess ggate voltage.
g

iD (mA)

vGS = Vt +4V
0.4

vGS = Vt +3V
0.3
vGS = Vt +2V
0.2

vGS = Vt +1V
0.1
vGS  Vt
vDS (mV)
100 200

NTUEE Electronics – L. H. Lu 5-4

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Operation as increasing drain voltage

As vDS increases, the voltage along the channel increases from 0 to vDS , and the voltage between the gate
and the points along the channel decreases from vGS at the source end to (vGS  vDS) at the drain end.
Since the inversion layer depends on the voltage difference across the MOS structure, increasing vDS will
result in a tapered channel.
The resistance increases due to tapered channel and the iD-vDS curve does not continue as a straight line.
At the point vDSsat = vGS  Vt , the channel is pinched off at the drain side.
Increasing vDS beyond this value has little effect on the channel shape and iD saturates at this value.
Triode region: vDS < vDSsat
Saturation region: vDS  vDSsat

Gate

vGS vGS  Vt
0 vDS

Channel
Source Drain

vDS
vDS = 0
vDS = vGS  Vt

NTUEE Electronics – L. H. Lu 5-5

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Derivation of the I-V relationship

Induced charge in the channel due to MOS capacitor:
QI ( x)  Cox [vGS  Vt  v( x)]
Equivalent resistance dR along the channel:
dx dx
dR  
qn( x)  n h( x)W  nWQI ( x)
I-V derivations:
iD dx iD dx
dv  iD dR  
 nWQI ( x)  nCoxW [vGS  Vt  v( x)]
v DS L


0
 nCoxW [vGS  Vt  v( x)]dv   iD dx
0

W 1 2
iD   nCox [(vGS  Vt )vDS  vDS ]
L 2
 Process transconductance parameter (A/V2): k’n= nCox
 Aspect ratio: W/L
 Transconductance parameter (A/V2): kn= nCox(W/L)
Drain current of MOSFETs:
 Triode region: iD  kn [(vGS  Vt )vDS  1 vDS
2
]
2
 Saturation region: iDsat 1
 k n (vGS  Vt ) 2
2
On-resistance (channel resistance for small vDS): rDS  1 / kn (vGS  Vt )

NTUEE Electronics – L. H. Lu 5-6

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The p-channel enhancement-type MOSFET

p-channel enhanced-type MOSFETs are fabricated on n-type substrate with p+ source and p+ drain.
Normally, source is connected to high voltage and drain is connected to low voltage.
As a negative voltage applies to gate electrode, negative charges accumulate in gate and the resulting field
pushes electrons in n-type substrate away from the surface, leaving behind a carrier-depletion region.
As gate voltage exceeds a negative threshold voltage Vt , holes start to accumulate on the substrate surface.
The induced p region (inversion layer) thus forms a p-type channel for current flow from source to drain.
Negative gate voltage is required to induce the channel  enhancement-type MOSFET.

Complementary MOS (CMOS)

CMOS technology employs both PMOS and NMOS devices.
If substrate is p-type, PMOS transistors are formed in n well (n-type body needed).
If substrate is n-type, NMOS transistors are formed in p well (p-type body needed).
The substrate and the well are connected to voltages which reverse bias the junctions for device isolation.

NTUEE Electronics – L. H. Lu 5-7

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5.2 Current-Voltage Characteristics

Circuit symbol
n-channel enhancement-mode MOSFET

The current-voltage characteristics

Cut-off region: (vGS  Vt)
 iD  0
T i d region:
Triode i ( GS > Vt andd vDS < vGS V
(v Vt)
W 1 2
 iD   nCox [(vGS  Vt )vDS  vDS ]
L 2
Saturation: (vGS > Vt and vDS  vGS Vt)
1 W
 iD   nCox (vGS  Vt ) 2
2 L
large-signal model (saturation)

NTUEE Electronics – L. H. Lu 5-8

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Channel length modulation

Channel length modulation: the channel pinch-off point moves slightly away from drain as vDS > vDSsat.
The effective channel length (Leff) reduces with vDS.
Electrons travel to pinch-off point will be swept to drain by electric field.
The length accounted for conductance in the channel is replaced by Leff :
vGS Vt Leff

 k W [vGS  Vt  v( x)]dv  i
'
n D dx
0 0

1 ' W 1 W 1 W L
iD  kn (vGS  Vt ) 2  k n' (vGS  Vt ) 2  k n' (vGS  Vt ) 2 (1  )
2 Leff 2 L  L 2 L L
ΔL 1 W
assuming that  vDS  iD  k n' (vGS  Vt ) 2 (1  vDS )
L 2 L
Finite output resistance
iD 1 k' W 1 V
ro  [ ]vGS constant  [ n (vGS  Vt ) 2 ]1   A
vDS 2 L I D I D

VA (Early voltage) = 1/ is proportional to channel length: VA = V’AL

V’A is process-technology dependent with a typical value from 5 ~ 50 V/m.
Due to the dependence of iD on vDS, MOSFET shows finite output resistance in saturation region.

NTUEE Electronics – L. H. Lu 5-9

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The body effect

The BS and BD junction should be reverse biased for the device to function properly.
Normally, the body of a n-channel MOSFET is connected to the most negative voltage.
The depletion region widens in BS and BD junctions and under the channel as VSB increases.
Body effect: Vt increases due to the excess charge in the depletion region under the channel.
The body effect can cause considerable degradation in circuit performance.
Threshold voltage:
Vt  Vt 0   [ 2 f  VSB  2 f ]
2qN A Si kT N
where   and  f  ln( A )
Cox q ni

Current equations:
W 1 2
iD   nCox [(vGS  Vt )vDS  vDS ]
L 2
1 W
iDsat   n Cox (vGS  Vt ) 2
2 L
Temperature effect
Vt decreases by ~2mV for every 1C rise → iD increases with temperature.
k’n decreases with temperature → iD decreases with increasing temperature.
For a given bias voltage, the overall observed effect of a temperature increase is a decrease in iD .

NTUEE Electronics – L. H. Lu 5-10

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Breakdown and input protection

Weak avalanche
 pn junction between the drain and substrate suffers avalanche breakdown as VDS increases
 Large drain current is observed
 Typical breakdown voltage 20 ~ 150 V
Punch-through
 Occurs at lower voltage (~20 V) for short channel devices
 Drain current increases rapidly as the drain depletion region extends through the channel
 Does not result in permanent damage to the device
Gate-oxide
Gate oxide breakdown
 Gate-oxide breakdown occurs when gate-to-source voltage exceeds 30 V
 Permanent damage to the device
Input Protection
 Protection circuit is needed for the input terminals of MOS integrated circuits
 Using clamping diode for the input protection

NTUEE Electronics – L. H. Lu 5-11

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The p-channel enhancement-type MOSFET

For a p-channel MOSFET, the source is connected to high voltage and the drain is connected to low voltage.
To induce the p-channel for the MOSFET, a negative vGS is required  Vt (threshold voltage) < 0V.
The body is normally connected to the most positive voltage.
The current-voltage
current voltage characteristics
Cut-off region: (vGS  Vtp)
 iD  0
Triode region: (vGS < Vtp and vDS > vGS Vtp)
W 1
 iD   pCox L [(vGS  Vtp )vDS  2 vDS ]
2

Saturation: (vGS < Vtp and vDS  vGS Vtp)

1 W
 iD  2  pCox L (vGS  Vtp )
2

Transconductance parameter k’p = pCox ≈ 0.4 k’n

The values of vGS , vDS , Vt and  for p-channel MOSFET operation are all negative
Drain current iD is still defined as a positive current.

NTUEE Electronics – L. H. Lu 5-12

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5.3 MOSFET Circuits at DC

DC analysis for MOSFET circuits

Assume the operation mode and solve the dc bias utilizing the corresponding current equation.
Verify the assumption with terminal voltages (cutoff, triode and saturation).
If the solution is invalid, change the assumption of operation mode and analyze again.
DC analysis example

Assuming MOSFET in saturation Assuming MOSFET in saturation Assuming MOSFET in triode

1 W W 1 2
VSS  VGS  I D RS  VGS  k n' (VGS  Vt ) 2 RS  VGS  3V and VDS  1.696V I D  k n' [(VGS  Vt )VDS  VDS ]
2 L L 2
 VGS  3V or 1V (not a valid solution) VDS < VGS  Vt  not in saturation! VGS  I D RS  VSS
(VDS = 4V)  (VGS  Vt = 1V)  saturation VDS  I D ( RD  RS )  VDD  VSS
 VGS  3.35V , VDS  0.35V and I D  0.33mA
VDS < VGS  Vt  in triode

NTUEE Electronics – L. H. Lu 5-13

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5.4 Applying the MOSFET in Amplifier Design

MOSFET voltage amplifier

MOSFET with a resistive load RD can be used as a voltage amplifier
The voltage transfer characteristic (VTC)
 The plot of vI (vGS) versus vO (vDS)
 DC analysis as vGS increases from 0 to VDD
 Cutoff mode: (0 V  vGS < Vt)
 iD  0
 vO  vDS  VDD
 Saturation mode: (vGS > Vt)
1
 iD  2 kn (vGS  Vt )
2

1
 vO  vDS  VDD  2 kn (vGS  Vt ) RD
2

 Triode mode: (vGS further increases)

1 2
 iD  kn [(vGS  Vt )vDS  vDS ]
2
1
 vO  vDS  VDD  kn [(vGS  Vt )vDS  vDS
2
]RD
2

NTUEE Electronics – L. H. Lu 5-14

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Biasing the MOSFET to obtain linear amplification

The slope in the VTC indicates voltage gain
MOSFET in saturation can be used as voltage amplification
Point Q is known as bias point or dc operating point
1
 VDS  VDD  kn (VGS  Vt ) 2 RD
2
The signal to be amplified is superimposed on VBE
vGS(t) = VGS + vgs(t)
The time-varying part in vGS(t) is the amplified signal
The circuit can be used as a linear amplifier if:
 A proper bias point is chosen for gain
 The input signal is small in amplitude
The small-signal voltage gain
The amplifier gain is the slope at Q:
dvDS
Av  vGS VGS   k n (VGS  Vt ) RD   k nVOV RD
dvGS
Maximum voltage gain of the amplifier
I D RD V
Av    DD | Av max |
VOV / 2 VOV / 2

NTUEE Electronics – L. H. Lu 5-15

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Determining the VTC by graphical analysis

Provides more insight into the circuit operation
Load line: the straight line represents in effect the load
iD = (VDDvDS)/RD
The operating point is the intersection point
Locating the bias point Q
The bias point (intersection) is determined by properly choosing the load line
The output voltage is bounded by VDD (upper bound) and VOV (lower bound)
The load line determines the voltage gain
The bias point determines the maximum upper/lower voltage swing of the amplifier

NTUEE Electronics – L. H. Lu 5-16

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5.5 Small-Signal Operation and Models

The DC bias point

MOSFET in saturation
1 1
 Drain current: I D  kn (VGS  Vt ) 2  knVOV2
2 2
 Drain voltage: VDS  VDD  I D RD  VOV
The small-signal circuit parameters are determined by the bias point.
The signal-signal operation
The small-signal drain current:
vGS  VGS  v gs
1 'W 1 W W 1 W 2
iD  k n (VGS  vgs  Vt ) 2  k n' (VGS  Vt ) 2  k n' (VGS  Vt )v gs  k n' v gs
2 L 2 L L 2 L
1 W W
 k n' (VGS  Vt ) 2  k n' (VGS  Vt )vgs  I D  id
2 L L
W
 id  k n' (VGS  Vt )v gs
L
The small-signal voltage gain:
vD  VDD  iD RD  VDD  ( I D  id ) RD  VD  id Rd  VD  vd
W
 vd  id RD  k n VOV RD v gs
L
vd W
 Av   k n VOV RD
vgs L

NTUEE Electronics – L. H. Lu 5-17

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The small-signal parameters

Transconductance (gm): describes how id change with vgs
id i W W
gm   D vGS VGS  k n' (VGS  Vt )  2k n' ID
v gs vGS L L
Output resistance (ro): describes how id change with vds
iD 1 1 V
ro  [ ]vGS constant   A
vDS I D I D
 Drain current varies with vDS due to channel length modulation
 Finite ro to model the linear dependence of iD on vDS
 The effect can be neglected
g if ro is sufficientlyy large
g
Body transconductance (gmb): describes how id changes with vbs
1 'W
iD  k n (vGS  Vt ) 2 G D
2 L +
B
i i Vt W V Vt +
 g mb  D vGS constant  D  k n' (vGS  Vt ) t  g m vgs ro vbs
vBS vDS constant Vt vBS L vBS vSB
gmvgs gmbvbs
 
Vt  Vt 0   [ 2 F  vSB  2F ] where   2qN A Si / Cox
Vt 
  S
vSB 2 2F  VSB
g mb  g m 

 The body effect of the MOSFET is modeled by gmb

 Can be neglected if body and source are connected together

NTUEE Electronics – L. H. Lu 5-18

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The small-signal equivalent circuit models

Hybrid- model

Neglect ro

T-model

Neglect ro

NTUEE Electronics – L. H. Lu 5-19

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5.6 Basic MOSFET Amplifier Configuration

Three basic configurations

Common-Source (CS) Common-Gete (CG) Common-Drain (CD)

Characterizing amplifiers
The MOSFET circuits can be characterized by a voltage amplifier model (unilateral model)
The electrical properties of the amplifier is represented by Rin, Ro and Avo
The analysis is based on the small-signal or linear equivalent circuit where dc components are not included
vo RL
Voltage gain: Av   Avo
vi RL  Ro
Overall voltage gain: Gv  vo  Rin Av  Rin RL
Avo
vsig Rin  Rsig Rin  Rsig RL  Rso

NTUEE Electronics – L. H. Lu 5-20

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The common-source (CS) amplifier

Characteristic parameters of the CS amplifier
 Input resistance: Rin  
 Output resistance: Ro  RD || ro  RD
 Open-circuit voltage gain: Avo   g m ( RD || ro )   g m RD
 Voltage gain: Av   g m ( RD || RL || ro )   g m ( RD || RL )
r r
 Overall voltage gain: Gv   g m ( RD || RL || ro )   g m ( RD || RL )
r  Rsig r  Rsig
CS amplifier can provide high voltage gain.
Input
p and output
p are out of phase
p due to negative
g gain.
g
Output resistance is moderate to high.
Small RD reduces Ro at the cost of voltage gain.

NTUEE Electronics – L. H. Lu 5-21

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The common-source (CS) with a source resistance

Characteristic parameters (by neglecting ro)
 Input resistance:
Rin  
 Output resistance:
Ro  RD
 Open-circuit voltage gain:
g m RD
Avo  
1  g m Rs
 Voltage gain:
g m ( RD || RL )
Av  
1  g m Rs
 Overall voltage gain:
g m ( RD || RL )
Gv  
1  g m Rs

Source degeneration resistance Rs is adopted.

Gain is reduced by the factor (1+gmRs).
It is considered a negative feedback of the amplifier.

NTUEE Electronics – L. H. Lu 5-22

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The common-gate (CG) amplifier

Characteristic parameters of the CG amplifier (by neglecting ro)
 Input resistance: Rin  1 / g m
 Output resistance: Ro  RD
 Open-circuit voltage gain: Avo  g m RD
 Voltage gain: Av  g m ( RD || RL )
1
 Overall voltage gain: Gv  g m ( RD || RL )
1  g m Rsig
CG amplifier can provide high voltage gain.
Input
p and outputp are in-phase
p due to ppositive ggain.
Input resistance is very low.
A single CG stage is not suitable for voltage amplification.
Output resistance is moderate to high.
Small RD reduces Ro at the cost of voltage gain.
The amplifier is no longer unilateral if ro is included.

NTUEE Electronics – L. H. Lu 5-23

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The common-collector (CD) amplifier

Characteristic parameters of the CD amplifier (by neglecting ro)
 Input resistance: Rin  
 Output resistance: Ro  1 / g m
 Voltage gain: Av  RL /( RL  1 / g m )  g m RL /( g m RL  1)  1
 Overall voltage gain: Gv  ( RL ) /( RL  1 / g m )  g m RL /( g m RL  1)  1
CD amplifier is also called source follower.
Input resistance is very high.
Output resistance is very low.
The voltage gain is less than but can be close to 1. 1
CD amplifier can be used as voltage buffer.
It is noted that, in the analysis, the amplifier is not unilateral.

NTUEE Electronics – L. H. Lu 5-24

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5.7 Biasing in MOS Amplifier Circuits

DC bias for MOSFET amplifier

The amplifiers are operating at a proper dc bias point.
Linear signal amplification is provided based on small-signal circuit operation.
The DC bias circuit is to ensure the MOSFET in saturation with a proper collector current ID.
Biasing by fixing gate-to-source voltage
1 1
Fix the dc voltage VGS to specify the saturation current of the MOSFET: I D  kn (VGS  Vt ) 2  kn (VG  Vt ) 2
2 2
The bias current deviates from the desirable value due to variations in the device parameters Vt and n
Biasing by fixing gate voltage and connecting a source resistance
1 1
The bias condition is specified by: VG  VGS  kn (VGS  Vt ) 2 RS and I D  kn (VGS  Vt ) 2
2 2
Drain current has better tolerance to variations in the device parameters

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Biasing using a drain-to-gate feedback resistor

A single power supply is needed.
RG ensures the MOSFET in saturation (VGS = VDS)
MOSFET operating point: VDD  VGS  1 k n (VGS  Vt ) 2
RD 2
The value of the feedback resistor RG affects the small-signal gain.
Biasing using a constant-current source
The MOSFET can be biased with a constant current source I.
The resistor RD is chosen to operate the MOSFET in active mode.
The current source is typically a current mirror.
mirror
Current mirror circuit:
 MOSFETs Q1 and Q2 are in saturation.
 The reference current IREF = I = ID
VDD  VGS 1
 k n (VGS  Vt ) 2
R 2
1
I REF  k n (VGS  Vt ) 2
2
 When applying to the amplifier circuit, the voltage
VD2 has to be high enough to ensure Q2 in saturation.

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5.8 Discrete-Circuit MOS Amplifiers

Circuit analysis:
DC analysis:
 Remove all ac sources (short for voltage source and open for current source)
 All capacitors are considered open-circuit
 DC analysis of MOSFET circuits for all nodal voltages and branch currents
 Find the dc current ID and make sure the MOSFET is in saturation
AC analysis:
 Remove all dc sources (short for voltage source and open for current source)
 All large capacitors are considered short-circuit
 Replace the MOSFET with its small
small-signal
signal model for ac analysis
 The circuit parameters in the small-signal model are obtained based on the value of ID
Complete amplifier circuit DC equivalent circuit AC equivalent circuit

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The common-source (CS) amplifier

The common-source amplifier with a source resistance

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The common-gate (CG) amplifier

The common-drain (CD) amplifier

NTUEE Electronics – L. H. Lu 5-29

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The amplifier frequency response

The gain falls off at low frequency band due to the effects of the coupling and by-pass capacitors
The gain falls off at high frequency band due to the internal capacitive effects in the MOSFETs
Midband:
 All coupling and by-pass capacitors (large capacitance) are considered short-circuit
 All internal capacitive effects (small capacitance) are considered open-circuit
 Midband gain is nearly constant and is evaluated by small-signal analysis
 The bandwidth is defined as BW = fH – fL
 A figure-of-merit for the amplifier is its gain-bandwidth product defined as GB = |AM|BW

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