Tps 62088

TPS62088, TPS62088A, TPS62089A
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
TPS62088 and TPS6208xA, 2.4-V to 5.5-V Input, Tiny 6-Pin 2-A/3-A Step-Down
Converter in 1.2-mm × 0.8-mm Wafer Chip Scale Package and Suitable for Embedding
1 Features 3 Description
• DCS-Control topology The TPS6208xx device family is a high-frequency
• Up to 95% efficiency synchronous step-down converters optimized for
• 26-mΩ and 26-mΩ internal power MOSFETs small solution size and high efficiency. With an
• 2.4-V to 5.5-V input voltage range input voltage range of 2.4 V to 5.5 V, common
• 4-μA operating quiescent current battery technologies are supported. At medium
• 1% output voltage accuracy to heavy loads, the converter operates in PWM
• 4-MHz switching frequency mode and automatically enters power save mode
• Power save mode for light-load efficiency operation at light load to maintain high efficiency
• A forced-PWM version for CCM operation over the entire load current range. The forced PWM
• 100% duty cycle for lowest dropout version of the device maintains a CCM operation
• Active output discharge across any load. The 4-MHz switching frequency
• Power good output allows the device to use small external components.
• Thermal shutdown protection Together with its DCS-control architecture, excellent
• Hiccup short-circuit protection load transient performance, and output voltage
• Available in 6-pin WCSP and PowerWCSP with regulation accuracy are achieved. Other features like
0.4-mm pitch overcurrent protection, thermal shutdown protection,
• 0.3-mm tall YWC package supports embedded active output discharge, and power good are built in.
systems The device is available in a 6-pin WCSP package.
• Supports 12 mm2 solution size
Device Information
• Supports < 0.6 mm height solution
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Create a custom design using the TPS62088 with
the WEBENCH® Power Designer TPS62088
YFP (6) 0.8 mm × 1.2 mm × 0.5 mm
TPS62089A
2 Applications TPS62088A YWC (6) 0.8 mm × 1.2 mm × 0.3 mm
• Solid-state drives
(1) For all available packages, see the orderable addendum at
• Wearable products
the end of the data sheet.
• Smartphones
• Camera modules
• Optical modules
VIN TPS6208818 L1 VOUT 100
2.4 V to 5.5 V 0.24 µH 1.8 V
95
VIN SW
90
C1 C2 C3
R3 4.7 µF 10 µF 10 µF 85
EN FB
100 k 80
Efficiency (%)
VPG 75
PG GND 70
65
60
Copyright Ú 2017, Texas Instruments Incorporated VOUT = 0.6V
55 VOUT = 0.9V
Typical Application Schematic 50 VOUT = 1.2V
VOUT = 1.8V
45 VOUT = 2.5V
40
100P 1m 10m 100m 1 3
Load (A) D007
3.3-V Input Voltage Efficiency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62088, TPS62088A, TPS62089A
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021 www.ti.com
Table of Contents
1 Features............................................................................1 9 Application and Implementation.................................. 10
2 Applications..................................................................... 1 9.1 Application Information............................................. 10
3 Description.......................................................................1 9.2 Typical Application.................................................... 10
4 Revision History.............................................................. 2 10 Power Supply Recommendations..............................19
5 Device Options................................................................ 3 11 Layout........................................................................... 20
6 Pin Configuration and Functions...................................3 11.1 Layout Guidelines................................................... 20
7 Specifications.................................................................. 4 11.2 Layout Example...................................................... 20
7.1 Absolute Maximum Ratings ...................................... 4 12 Device and Documentation Support..........................21
7.2 ESD Ratings .............................................................. 4 12.1 Device Support....................................................... 21
7.3 Recommended Operating Conditions ........................4 12.2 Documentation Support.......................................... 21
7.4 Thermal Information ..................................................4 12.3 Receiving Notification of Documentation Updates..21
7.5 Electrical Characteristics ............................................5 12.4 Support Resources................................................. 21
7.6 Typical Characteristics................................................ 6 12.5 Trademarks............................................................. 21
8 Detailed Description........................................................7 12.6 Electrostatic Discharge Caution..............................22
8.1 Overview..................................................................... 7 12.7 Glossary..................................................................22
8.2 Functional Block Diagram........................................... 7 13 Mechanical, Packaging, and Orderable
8.3 Feature Description.....................................................7 Information.................................................................... 22
8.4 Device Functional Modes............................................9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2019) to Revision E (November 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Added information for the FPWM devices.......................................................................................................... 3
• Added new curves for FPWM devices..............................................................................................................14
Changes from Revision C (May 2019) to Revision D (September 2019) Page

• Changed TPS62088YWC status to production.................................................................................................. 1
• Added TPS62088YWCEVM-084 to the Thermal information table.................................................................... 4
2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A

TPS62088, TPS62088A, TPS62089A
www.ti.com SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
5 Device Options
Device Options
PART NUMBER(1) OPERATION MODE OUTPUT VOLTAGE
TPS62088YFP PFM/PWM 3-A adjustable
TPS62088YWC PFM/PWM 3-A adjustable
TPS6208812YFP PFM/PWM 3 A with 1.2 V
TPS62088AYFP Forced-PWM 3-A adjustable
TPS62089AYFP Forced-PWM 2-A adjustable
(1) For detailed ordering information, please check the package option addendum section at the end of this data sheet.
6 Pin Configuration and Functions
1 2 1 2
A EN VIN A EN VIN
B PG SW B PG SW
C FB GND C FB GND
Figure 6-1. YFP Package Top View Figure 6-2. YWC Package Top View
Table 6-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low
EN A1 I
disables the device. Do not leave floating.
Power-good open-drain output pin. The pullup resistor can be connected to voltages up to
PG B1 O
5.5 V. If unused, leave it floating.
Feedback pin. For the fixed output voltage versions, this pin must be connected to the
FB C1 I
output.
GND C2 — Ground pin
SW B2 O Switch pin of the power stage
VIN A2 I Input voltage pin
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

TPS62088, TPS62088A, TPS62089A
7 Specifications
7.1 Absolute Maximum Ratings
MIN MAX UNIT
VIN, FB, EN, PG –0.3 6
SW (DC) –0.3 VIN + 0.3
Voltage at pins (2) V
SW (DC, in current limit) –1.0 VIN + 0.3
SW (AC, less than 10 ns) (3) –2.5 10
Operating junction temperature, TJ –40 150
Temperature °C
Storage temperature, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V
V(ESD) Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage range 2.4 5.5 V
VOUT Output voltage range 0.6 4.0 V
IOUT Output current range, TPS62089A 0 2 A
IOUT Output current range, TPS62088, TPS62088A (1) 0 3 A
ISINK_PG Sink current at the PG pin 1 mA
VPG Pullup resistor voltage 5.5 V
TJ Operating junction temperature -40 125 °C
(1) For YFP package versions, lifetime is reduced when operating continuously at 3-A output current with the junction temperature higher
than 85°C.
7.4 Thermal Information

TPS62088/TPS6208xA
THERMAL METRIC(1) 6 PINS UNIT
YFP (6 PINS) YWC (6 PINS) YFP EVM-814 YWC EVM-084
RθJA Junction-to-ambient thermal resistance 141.3 130.9 85.7 70.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1.7 1.1 n/a (2) n/a (2) °C/W
RθJB Junction-to-board thermal resistance 47.3 27.3 n/a (2) n/a (2) °C/W
ψJT Junction-to-top characterization parameter 0.5 0.7 1.9 0.5 °C/W
Junction-to-board characterization
ψJB 47.5 27.2 55.9 38.7 °C/W
parameter
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM.

TPS62088, TPS62088A, TPS62089A
7.5 Electrical Characteristics

TJ = –40°C to 125°C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V , unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = HIGH, no load, device not switching 4 10 µA
IQ Quiescent current EN = HIGH, no load, TPS62088A and TPS62089A 8 mA
ISD Shutdown current EN = LOW, TJ = –40℃ to 85℃ 0.05 0.5 µA
Undervoltage lockout threshold VIN falling 2.1 2.2 2.3 V
VUVLO
Undervoltage lockout hysteresis VIN rising 160 mV
Thermal shutdown threshold TJ rising 150 °C
TJSD
Thermal shutdown hysteresis TJ falling 20 °C
LOGIC INTERFACE EN
VIH High-level input threshold voltage 1.0 V
VIL Low-level input threshold voltage 0.4 V
IEN,LKG Input leakage current into EN pin 0.01 0.1 µA
SOFT START, POWER GOOD
tSS Soft-start time Time from EN high to 95% of VOUT nominal 1.25 ms
VPG rising, VFB referenced to VFB nominal 94% 96% 98%
Power-good lower threshold
VPG falling, VFB referenced to VFB nominal 90% 92% 94%
VPG
VPG rising, VFB referenced to VFB nominal 103% 105% 107%
Power-good upper threshold
VPG falling, VFB referenced to VFB nominal 108% 110% 112%
VPG,OL Low-level output voltage Isink = 1 mA 0.4 V
IPG,LKG Input leakage current into PG pin VPG = 5.0 V 0.01 0.1 µA
OUTPUT
TPS6208812, PWM mode 1.188 1.2 1.212
VOUT Output voltage accuracy TPS6208818, PWM mode 1.782 1.8 1.818 V
TPS6208833, PWM mode 3.267 3.3 3.333
VFB Feedback regulation voltage PWM mode 594 600 606 mV
IFB,LKG Feedback input leakage current TPS62088, VFB = 0.6 V 0.01 0.05 µA
Internal resistor divider connected to FB
RFB TPS6208812, TPS6208818, TPS6208833 7.5 MΩ
pin
IDIS Output discharge current VSW = 0.4V; EN = LOW 75 400 mA
POWER SWITCH
High-side FET on-resistance 26 mΩ
RDS(on)
Low-side FET on-resistance 26 mΩ
ILIM High-side FET switch current limit TPS62089A 2.7 3.3 3.9 A
ILIM High-side FET switch current limit TPS62088 and TPS62088A 3.6 4.3 5.0 A
ILIM Low-side FET switch negative current limit TPS62088A and TPS62089A -1.6 A
fSW PWM switching frequency IOUT = 1 A, VOUT = 1.8 V 4 MHz

TPS62088, TPS62088A, TPS62089A
7.6 Typical Characteristics
70.0 70.0
60.0 60.0
50.0 50.0
RDS(on) (mOhm)
RDS(on) (mOhm)
40.0 40.0
30.0 30.0
20.0 20.0
TJ = 0 °C TJ = 0 °C
TJ = 25 °C TJ = 25 °C
10.0 TJ = 85 °C 10.0 TJ = 85 °C
TJ = 125 °C TJ = 125 °C
0.0 0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V) D010 Input Voltage (V) D011
Figure 7-1. High-Side FET On-Resistance Figure 7-2. Low-Side FET On-Resistance
8.0 0.5
TJ = -40 °C
TJ = 25 °C
0.4 TJ = 85 °C
6.0 TJ = 125 °C
$
$
4XLHVFHQW &XUUHQW
6KXWGRZQ &XUUHQW
0.3
4.0
0.2
2.0 TJ = -40 °C
0.1
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
0.0 0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V) Input Voltage (V) D000
D001
Figure 7-3. Quiescent Current Figure 7-4. Shutdown Current

TPS62088, TPS62088A, TPS62089A
8 Detailed Description
8.1 Overview
The TPS62088xx family is synchronous step-down converter that adopts a new generation DCS-Control (Direct
Control with Seamless transition into power save mode) topology without the output voltage sense (VOS) pin.
This is an advanced regulation topology that combines the advantages of hysteretic, voltage, and current mode
control schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in power save mode at light load currents. In PWM mode, the converter operates with its nominal switching
frequency of 4 MHz, having a controlled frequency variation over the input voltage range. As the load current
decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC
current consumption to achieve high efficiency over the entire load current range. In forced PWM devices,
the converter maintains a continuous conduction mode operation and keeps the output voltage ripple very low
across the whole load range and at a nominal switching frequency of 4 MHz. Because DCS-Control supports
both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to power
save mode is seamless and without effects on the output voltage. The devices offer both excellent DC voltage
and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with
RF circuits.
8.2 Functional Block Diagram
PG VIN
VPG_H
+
VFB ±
Control Logic
VREF +
VPG_L GND
EN UVLO ±
Thermal Shutdown
Startup
Peak Current Detect
VSW
TON
VIN HICCUP
VSW Direct Control

&
Compensation
SW
Gate
VREF Modulator
Drive
+
_EA Comparator
Discharge
FB
Zero Current Detect
GND
Fixed VOUT
GND
8.3 Feature Description

8.3.1 Power Save Mode
As the load current decreases, the device enters power save mode operation. The power save mode occurs
when the inductor current becomes discontinuous. Power save mode is based on a fixed on-time architecture,
as related in Equation 1.

TPS62088, TPS62088A, TPS62089A
VOUT
tON 250ns u
VIN
(1)
In power save mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitor or inductor value.
When the device operates close to 100% duty cycle mode, the device cannot enter power save mode regardless
of the load current if the input voltage decreases to typically 10% above the output voltage. The device maintains
output regulation in PWM mode.
8.3.2 Pulse Width Modulation (PWM) Operation
At load currents larger than half the inductor ripple current, the device operates in pulse width modulation in
continuous conduction mode (CCM). The PWM operation is based on an adaptive constant on-time control with
stabilized switching frequency.
In forced-PWM devices, the device always operates in pulse width modulation in continuous conduction mode
(CCM).
8.3.3 100% Duty Cycle Low Dropout Operation
The devices offer low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly
useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current
and output voltage can be calculated as:
VIN,MIN = VOUT + IOUT,MAX ´ (RDS(on) + RL )

(2)
where
• VIN,MIN = Minimum input voltage to maintain an output voltage
• IOUT,MAX = Maximum output current
• RDS(on) = High-side FET ON-resistance
• RL = Inductor ohmic resistance (DCR)
8.3.4 Soft Start
After enabling the device, there is a 250-µs delay before switching starts. Then, an internal soft start-up circuitry
ramps up the output voltage which reaches nominal output voltage during the start-up time of 1 ms. This avoids
excessive inrush current and creates a smooth output voltage rise slope. It also prevents excessive voltage
drops of primary cells and rechargeable batteries with high internal impedance.
The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the
output voltage to its nominal value.
8.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET
is turned off and the low-side MOSFET remains off, while the inductor current flows through its body diode and
quickly ramps down.
When this switch current limits is triggered 32 times, the device stops switching. The device then automatically
starts a new start-up after a typical delay time of 128 µs has passed. This is named HICCUP short-circuit
protection. The device repeats this mode until the high load condition disappears.

TPS62088, TPS62088A, TPS62089A
In forced PWM devices, a negative current limit (ILIMN) is enabled to prevent excessive current flowing
backwards to the input. When the inductor current reaches ILIMN, the low-side MOSFET turns off and the
highside MOSFET turns on and kept on until TON time expires.
8.3.6 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, undervoltage lockout is implemented that shuts down
the device at voltages lower than VUVLO.
8.3.7 Thermal Shutdown
The device goes into thermal shutdown and stops the power stage switching when the junction temperature
exceeds TJSD. When the device temperature falls below the threshold by 20°C, the device returns to normal
operation automatically by switching the power stage again.
8.4 Device Functional Modes
8.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic HIGH. Accordingly, shutdown mode is forced if the EN pin
is pulled LOW with a shutdown current of typically 50 nA. In shutdown mode, the internal power switches as well
as the entire control circuitry are turned off. An internal switch smoothly discharges the output through the SW
pin in shutdown mode. Do not leave the EN pin floating.
The typical threshold value of the EN pin is 0.89 V for rising input signal, and 0.62 V for falling input signal.
8.4.2 Power Good
The device has a power-good output. The PG pin goes high impedance once the FB pin voltage is above 96%
and less than 105% of the nominal voltage, and is driven low once the voltage falls below typically 92% or higher
than 110% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The
power-good output requires a pullup resistor connecting to any voltage rail less than 5.5 V.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin unconnected when not used. The PG rising edge has a 100-µs blanking time and the PG
falling edge has a deglitch delay of 20 µs.
Table 8-1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH IMPEDANCE LOW
EN = HIGH, VFB ≥ 0.576 V √
EN = HIGH, VFB ≤ 0.552 V √
Enable
EN = HIGH, VFB ≤ 0.63 V √
EN = HIGH, VFB ≥ 0.66 V √
Shutdown EN = LOW √
Thermal shutdown TJ > TJSD √
UVLO 0.7 V < VIN < VUVLO √
Power supply removal VIN < 0.7 V undefined

TPS62088, TPS62088A, TPS62089A
9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information

The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application
VIN TPS62088 L1 VOUT
2.4 V to 5.5 V 0.24 µH 1.8 V
VIN SW
C1 C2 C3 C4
R3 4.7 µF 10 µF 10 µF R1 120 pF
EN
100 k 200 k
VPG
PG GND FB
R2
100 k
Copyright Ú 2017, Texas Instruments Incorporated
Figure 9-1. Typical Application of Adjustable Output

VIN TPS6208818 L1 VOUT
2.4 V to 5.5 V 0.24 µH 1.8 V
VIN SW
C1 C2 C3
R3 4.7 µF 10 µF 10 µF
EN FB
100 k
VPG
PG GND
Copyright Ú 2017, Texas Instruments Incorporated
Figure 9-2. Typical Application of Fixed Output
9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage 2.4 V to 5.5 V
Output voltage 1.8 V
Maximum peak output current 3A

TPS62088, TPS62088A, TPS62089A
Table 9-2 lists the components used for the example.

Table 9-2. List of Components of Figure 9-1
REFERENCE DESCRIPTION MANUFACTURER(1)
C1 4.7 µF, Ceramic capacitor, 6.3 V, X7R, size 0603, JMK107BB7475MA Taiyo Yuden
C2, C3 10 µF, Ceramic capacitor, 10 V, X7R, size 0603, GRM188Z71A106MA73D Murata
C4 120 pF, Ceramic capacitor, 50 V, size 0603, GRM1885C1H121JA01D Murata
L1 0.24 µH, Power Inductor, size 0603, DFE160810S-R24M (DFE18SANR24MG0) Murata
R1 Depending on the output voltage, 1%, size 0603 Std
R2 100 kΩ, Chip resistor, 1/16 W, 1%, size 0603 Std
R3 100 kΩ, Chip resistor, 1/16 W, 1%, size 0603 Std
(1) See Third-party Products disclaimer.
Table 9-3. List of Components of Figure 9-2, Smallest Solution

REFERENCE DESCRIPTION MANUFACTURER(1)
C1, C2, C3 10 µF, Ceramic capacitor, 6.3 V, X5R, size 0402, GRM155R60J106ME47 Murata
L1 0.24 µH, Power Inductor, size 0603, DFE160810S-R24M (DFE18SANR24MG0) Murata
R3 100 kΩ, Chip resistor, 1/16 W, size 0402 Std
9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62088 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Setting The Output Voltage
Choose resistors R1 and R2 to set the output voltage within a range of 0.6V to 4V, according to Equation 3. To
keep the feedback (FB) net robust from noise, set R2 equal to or lower than 100 kΩ to have at least 0.6 µA of
current in the voltage divider. Lower values of FB resistors achieve better noise immunity, and lower light load
efficiency, as explained in the Design Considerations For A Resistive Feedback Divider In A DC/DC Converter
Analog Design Journal.
§V · §V ·
R1 R2 u ¨ OUT 1¸ R2 u ¨ OUT 1¸
© VFB ¹ © 0.6V ¹
(3)
For devices with a fixed output voltage, the FB pin must be connected to VOUT. R1, R2, and C4 are not needed.
The fixed output voltage devices have an internal feedforward capacitor.

TPS62088, TPS62088A, TPS62089A
9.2.2.3 Feedforward Capacitor

A feedforward capacitor (C4) is required in parallel with R1. Equation 4 calculates the capacitor value. For
the recommended 100 k value for R2, a 120 pF feedforward capacitor is used. For forced PWM devices, a
feedforward capacitor is not needed.
12 Ps
C4
R2 (4)
9.2.2.4 Output Filter Design

The inductor and the output capacitor together provide a low-pass filter. To simplify this process, Table 9-4
outlines possible inductor and capacitor value combinations for most applications. Checked cells represent
combinations that are proven for stability by simulation and lab test. Further combinations should be checked for
each individual application.
Table 9-4. Matrix of Output Capacitor and Inductor Combinations
NOMINAL COUT [µF](3)
NOMINAL L [µH](2)
10 2 x 10 or 1 x 22 47 100
0.24 + +(1) +
0.33 + + +
0.47
(1) This LC combination is the standard value and recommended for most applications. Other '+' marks indicate recommended filter
combinations. Other values may be acceptable in some applications but should be fully tested by the user.
(2) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
(3) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
9.2.2.5 Inductor Selection

The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 5 is given.
DIL
IL,MAX = IOUT,MAX +
2
VOUT
1-
VIN
DIL = VOUT ´
L ´ fSW (5)
where
• IOUT,MAX = Maximum output current
• ΔIL = Inductor current ripple
• fSW = Switching frequency
• L = Inductor value
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate
inductor. Table 9-5 lists recommended inductors.
Table 9-5. List of Recommended Inductors(1)
INDUCTANCE CURRENT RATING DIMENSIONS DC RESISTANCE
PART NUMBER
[µH] [A] [L × W × H mm] [mΩ]
Murata, DFE160810S-R24M
0.24 4.9 1.6 × 0.8 × 1.0 30
(DFE18SANR24MG0)
0.24 6.5 2.0 × 1.2 × 1.0 25 Murata, DFE201210U-R24M

TPS62088, TPS62088A, TPS62089A
Table 9-5. List of Recommended Inductors(1) (continued)

INDUCTANCE CURRENT RATING DIMENSIONS DC RESISTANCE
PART NUMBER
[µH] [A] [L × W × H mm] [mΩ]
0.24 4.9 1.6 × 0.8 × 0.8 22 Cyntec, HTEH16080H-R24MSR
0.25 9.7 4.0 × 4.0 × 1.2 7.64 Coilcraft, XFL4012-251ME
0.24 3.5 2.0 × 1.6 × 0.6 35 Wurth Electronics, 74479977124
0.24 3.5 2.0 × 1.6 × 0.6 35 Sunlord, MPM201606SR24M
9.2.2.6 Capacitor Selection

The input capacitor is the low-impedance energy source for the converters which helps to provide stable
operation. A low-ESR multilayer ceramic capacitor is recommended for best filtering and must be placed
between VIN and GND as close as possible to those pins. For most applications, 4.7 μF is sufficient, though a
larger value reduces input current ripple.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended typical output capacitor value is 2 × 10 μF or 1 × 22 µF; this
capacitance can vary over a wide range as outline in the output filter selection table.
A feedforward capacitor is required for the adjustable version, as described in Section 9.2.2.2. This capacitor is
not required for the fixed output voltage versions.

TPS62088, TPS62088A, TPS62089A
9.2.3 Application Curves
VIN = 5.0 V, VOUT = 1.8 V, TA = 25°C, BOM = Table 9-2, unless otherwise noted.
90 0.612
85 0.609
80
0.606
75
0.603
Efficiency (%)
70
Vout (V)
65 0.6
60 0.597
55 0.594 VIN = 2.5 V

VIN = 2.5V
50 VIN = 3.3 V
VIN = 3.3V 0.591 VIN = 4.2 V
45 VIN = 4.2V VIN = 5.0 V
VIN = 5.0V 0.588
40 100P 1m 10m 100m 1 3
100P 1m 10m 100m 1 3 Load (A) D021
Load (A) D002
VOUT = 0.6 V
VOUT = 0.6 V
Figure 9-4. Load Regulation
Figure 9-3. Efficiency
100% 0.606
95%
90% 0.604
85%
80% 0.602
Efficiency (%)
75%
Vout (V)
70% 0.6
65%
60% 0.598
55% VIN=2.5V VIN=2.5V
50% VIN=3.3V 0.596 VIN=3.3V
VIN=4.2V VIN=4.2V
45% VIN=5.0V VIN=5.0V
40% 0.594
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Load (A) Load (A)
VOUT = 0.6 V FPWM devices VOUT = 0.6 V FPWM devices
Figure 9-5. Efficiency Figure 9-6. Load Regulation

90 0.909
85
0.906
80
75 0.903
Efficiency (%)
70
Vout (V)
65 0.9
60
0.897
55
VIN = 2.5 V
VIN = 2.5V
50 0.894 VIN = 3.3 V
VIN = 3.3V VIN = 4.2 V
45 VIN = 4.2V VIN = 5.0 V
VIN = 5.0V 0.891
40 100P 1m 10m 100m 1 3
100P 1m 10m 100m 1 3 Load (A) D031
Load (A) D003
VOUT = 0.9 V
VOUT = 0.9 V
Figure 9-8. Load Regulation
Figure 9-7. Efficiency

TPS62088, TPS62088A, TPS62089A
100% 0.909
95%
90% 0.906
85%
80% 0.903
Efficiency (%)
75%
Vout (V)
70% 0.9
65%
60% 0.897
55% VIN=2.5V VIN=2.5V
50% VIN=3.3V 0.894 VIN=3.3V
VIN=4.2V VIN=4.2V
45% VIN=5.0V VIN=5.0V
40% 0.891
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Load (A) Load (A)
VOUT = 0.9 V FPWM devices VOUT = 0.9 V

100 1.212
95 1.209
90
1.206
85
Efficiency (%)
1.203
80
Vout (V)
75 1.2
70 1.197
65
1.194 VIN = 2.5 V
VIN = 2.5V
60 VIN = 3.3V VIN = 3.3 V
1.191 VIN = 4.2 V
55 VIN = 4.2V
VIN = 5.0V VIN = 5.0 V
50 1.188
100P 1m 10m 100m 1 3
100P 1m 10m 100m 1 3
Load (A)
Load (A) D004
D041
VOUT = 1.2 V VOUT = 1.2 V

100% 1.212
95%
1.209
90%
85% 1.206
80%
Efficiency (%)
1.203
75%
Vout (V)
70% 1.2
65%
1.197
60%
55% VIN=2.5V 1.194 VIN=2.5V
50% VIN=3.3V VIN=3.3V
VIN=4.2V 1.191 VIN=4.2V
45% VIN=5.0V VIN=5.0V
40% 1.188
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Load (A) Load (A)

TPS62088, TPS62088A, TPS62089A
100 1.818
95
1.812
90
1.806
Efficiency (%)
85
Vout (V)
80 1.8
75 1.794
70 VIN = 2.5V VIN = 2.5 V
VIN = 3.3V 1.788 VIN = 3.3 V
65 VIN = 4.2V VIN = 4.2 V
VIN = 5.0V VIN = 5.0 V
1.782
60
100P 1m 10m 100m 1 3
100P 1m 10m 100m 1 3
Load (A)
Load (A) D005
D051

100% 1.818
95% 1.815
90% 1.812
85% 1.809
80% 1.806
Efficiency (%)
75% Vout (V) 1.803

70% 1.8
65% 1.797
60% 1.794
55% VIN=2.5V 1.791 VIN=2.5V
50% VIN=3.3V 1.788 VIN=3.3V
VIN=4.2V VIN=4.2V
45% VIN=5.0V 1.785 VIN=5.0V
40% 1.782
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Load (A) Load (A)

100 3.333
3.322
95
3.311
90 3.3
Efficiency (%)
Vout (V)
3.289
85
3.278
80 3.267
3.256
75
VIN = 4.2V 3.245 VIN = 4.2V
VIN = 5.0V VIN = 5.0V
3.234
70
100P 1m 10m 100m 1 3
100P 1m 10m 100m 1 3
Load (A)
Load (A) D006
D061

TPS62088, TPS62088A, TPS62089A
100% 3.356
95% 3.351
90% 3.346
3.341
85%
3.336
80% 3.331
Efficiency (%)
75%
Vout (V)
3.326
70% 3.321
65% 3.316
60% 3.311
3.306
55%
3.301
50% 3.296
VIN=4.2V VIN=4.2V
45% VIN=5.0V 3.291 VIN=5.0V
40% 3.286
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Load (A) Load (A)

5.0 5.0
4.0
Switching Frequency (MHz)
Switching Frequency (MHz)

4.0
3.0
3.0
2.0
VOUT = 0.6V
VOUT = 0.6V 2.0 VOUT = 0.9V
1.0 VOUT = 0.9V VOUT = 1.2V
VOUT = 1.2V VOUT = 1.8V
VOUT = 1.8V VOUT = 3.3V
0.0 1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Load (A) D008
Input Voltage (V) D009
VIN = 3.3 V IOUT = 1.0 A
Figure 9-23. Switching Frequency Figure 9-24. Switching Frequency

4.50x106 4.50x106
6
4.00x10 4.00x106
3.50x106 3.50x106
Switching Frequency (Hz)
Switching Frequency (Hz)
6
3.00x10 3.00x106
2.50x106 2.50x106
6
2.00x10 2.00x106
1.50x106 1.50x106
VOUT=0.6V
1.00x10 6 VOUT=0.6V 1.00x106 VOUT=0.9V
VOUT=0.9V VOUT=1.2V
500.00x103 VOUT=1.2V 500.00x103 VOUT=1.8V
VOUT=1.8V VOUT=3.3V
0
0.00x10 0.00x100
0 0.5 1 1.5 2 2.5 3 2.5 3 3.5 4 4.5 5 5.5
Load (A) Input Voltage (V)
VIN = 3.3 V FPWM devices IOUT = 1.0 A FPWM devices
Figure 9-25. Switching Frequency Figure 9-26. Switching Frequency

TPS62088, TPS62088A, TPS62089A
ICOIL ICOIL
1A/DIV 1A/DIV
VOUT VOUT
10mV/DIV 10mV/DIV
AC AC
VSW VSW
5V/DIV 5V/DIV
Time - 200ns/DIV 7LPH V ',9

D013 D014
IOUT = 3.0 A IOUT = 0.1 A
Figure 9-27. PWM Operation Figure 9-28. PSM Operation
VEN
5V/DIV
VPG
5V/DIV
VOUT
1V/DIV
ICOIL
0.5A/DIV
IOUT = 0.1 A FPWM devices 7LPH V ',9
Figure 9-29. FPWM Operation D015
No load
Figure 9-30. Start-Up with No-Load
VEN
5V/DIV
VPG
5V/DIV
VOUT
1V/DIV
ICOIL
2A/DIV
No load FPWM devices

7LPH V ',9
Figure 9-31. Start-Up with No-Load D016
IOUT = 3.0 A
Figure 9-32. Start-Up with Load

TPS62088, TPS62088A, TPS62089A
VPG
5V/DIV
VPG
5V/DIV
ILOAD ICOIL
2A/DIV 2A/DIV
VOUT
50mV/DIV
AC
VOUT
1V/DIV
7LPH V ',9
7LPH V ',9
D017
D018
IOUT = 0.1 A to 3 A
IOUT = 1 A
Figure 9-33. Load Transient
Figure 9-34. HICCUP Short Circuit Protection
VPG
5V/DIV
ICOIL
2A/DIV
VOUT
1V/DIV
7LPH V ',9
D019
IOUT = 1 A
Figure 9-35. HICCUP Short Circuit Protection (Zoom In)
10 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.

TPS62088, TPS62088A, TPS62089A
11 Layout
11.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the device. See
Figure 11-1 and Figure 11-2 for the recommended PCB layout.
• The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps
the power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
• The low side of the input and output capacitors must be connected properly to the power GND to avoid a
GND potential shift.
• The sense traces connected to FB is a signal trace. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes. The connection of the output voltage trace for the FB
resistors should be made at the output capacitor.
• Refer to Figure 11-1 and Figure 11-2 for an example of component placement, routing and thermal design.
11.2 Layout Example
Figure 11-2. PCB Layout of Fixed Output Voltage

Figure 11-1. PCB Layout of Adjustable Output Application
Voltage Application
11.2.1 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics Application Notes,
Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report and
Semiconductor and IC Package Thermal Metrics Application Report.

TPS62088, TPS62088A, TPS62089A
12 Device and Documentation Support

12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62088 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

TPS62088, TPS62088A, TPS62089A
12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

TPS62088, TPS62088A, TPS62089A
PACKAGE OUTLINE
YWC0006A SCALE 15.000
PowerWCSP - 0.3 mm max height
POWER CHIP SCALE PACKAGE
0.82 A
B
0.78
PIN A1 INDEX
AREA
1.22
1.18
0.20
0.16 C
0.3 MAX
SEATING PLANE
0.10
PKG
0.07
0.16 0.378
3X 3X
0.14 0.358
B SYMM
0.86
0.187
2X
0.43 0.167
0.015 C A B
1 2 0.247
4X
0.227
0.165 0.015 C A B
0.439
4223997/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com

TPS62088, TPS62088A, TPS62089A
EXAMPLE BOARD LAYOUT

YWC0006A PowerWCSP - 0.3 mm max height
PKG PKG
3X (0.15) 3X (0.368) 3X (0.2) 3X (0.368)

1 2 1 2
A A
4X (0.237) 4X (0.237)
(0.43) TYP 2X (0.177) (0.43) TYP 2X (0.2)

SYMM SYMM
B B
(R0.05) TYP SOLDER MASK (R0.05) TYP SOLDER MASK

OPENING OPENING
TYP TYP
C C
METAL UNDER
METAL EDGE
SOLDER MASK
TYP
TYP
0.0375 MAX 0.0375 MIN
ALL AROUND (0.165) ALL AROUND (0.165)
TYP TYP
(0.439) (0.464)
LAND PATTERN EXAMPLE LAND PATTERN EXAMPLE

NON SOLDER MASK DEFINED
SOLDER MASK DEFINED
SCALE: 40X
SCALE: 40X
4223997/B 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com

TPS62088, TPS62088A, TPS62089A
EXAMPLE STENCIL DESIGN

YWC0006A PowerWCSP - 0.3 mm max height
PKG
3X (0.2) 3X (0.348) 3X (0.2) 3X (0.368)

1 2
A
4X (0.237) 4X (0.237)
(0.43) TYP PKG (0.43) TYP
SYMM SYMM
2X (0.2) 2X (0.2)
B
(R0.05) TYP (R0.05) TYP
METAL UNDER
SOLDER MASK
TYP
C
SOLDER MASK
OPENING
TYP
EXPOSED (0.175) (0.165)
METAL TO PKG
3X (0.474) (0.464)
SOLDER PASTE EXAMPLE SOLDER PASTE EXAMPLE

NON SOLDER MASK DEFINED SOLDER MASK DEFINED
BASED ON 0.075 mm THICK STENCIL BASED ON 0.075 mm THICK STENCIL
SCALE: 40X SCALE: 40X
4223997/B 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com

TPS62088, TPS62088A, TPS62089A
PACKAGE OUTLINE
YFP0006-C01 SCALE 10.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
B E A
BALL A1
CORNER
0.30
0.25
C
0.5 MAX
SEATING PLANE
0.19
0.13 BALL TYP
0.05 C
0.4
TYP
SYMM
D: Max = 1.22 mm, Min = 1.18 mm

0.8
TYP B SYMM E: Max = 0.82 mm, Min = 0.78 mm
0.4 TYP
A
0.25
6X
0.21 1 2
0.015 C A B
4224455/B 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com

TPS62088, TPS62088A, TPS62089A
EXAMPLE BOARD LAYOUT

YFP0006-C01 DSBGA - 0.5 mm max height
(0.4) TYP
6X ( 0.23)
1 2
(0.4) TYP
B SYMM
SYMM
LAND PATTERN EXAMPLE

SCALE:50X
( 0.23) 0.05 MAX 0.05 MIN METAL UNDER

METAL SOLDER MASK
SOLDER MASK ( 0.23)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS

NOT TO SCALE
4224455/B 02/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com

TPS62088, TPS62088A, TPS62089A
EXAMPLE STENCIL DESIGN

YFP0006-C01 DSBGA - 0.5 mm max height
(0.4) TYP
6X ( 0.25) (R0.05) TYP
1 2
(0.4) TYP
B SYMM
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:50X
4224455/B 02/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com

PACKAGE OPTION ADDENDUM
www.ti.com 8-Sep-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS6208812YFPR ACTIVE DSBGA YFP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 1B5 Samples
TPS6208812YFPT ACTIVE DSBGA YFP 6 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 1B5 Samples
TPS62088AYFPJ ACTIVE DSBGA YFP 6 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 W Samples
TPS62088AYFPR ACTIVE DSBGA YFP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 W Samples
TPS62088YFPR ACTIVE DSBGA YFP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 15X Samples
TPS62088YFPT ACTIVE DSBGA YFP 6 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 15X Samples
TPS62088YWCR ACTIVE DSBGA YWC 6 3000 RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 1GB Samples
TPS62089AYFPR ACTIVE DSBGA YFP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 X Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS6208812YFPR DSBGA YFP 6 3000 180.0 8.4 0.9 1.3 0.62 4.0 8.0 Q1
TPS6208812YFPT DSBGA YFP 6 250 180.0 8.4 0.9 1.3 0.62 4.0 8.0 Q1
TPS62088AYFPJ DSBGA YFP 6 12000 180.0 8.4 0.89 1.31 0.57 2.0 8.0 Q1
TPS62088AYFPR DSBGA YFP 6 3000 180.0 8.4 0.89 1.31 0.57 2.0 8.0 Q1
TPS62088YWCR DSBGA YWC 6 3000 180.0 8.4 0.95 1.35 0.38 4.0 8.0 Q1
TPS62089AYFPR DSBGA YFP 6 3000 180.0 8.4 0.89 1.31 0.57 2.0 8.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS6208812YFPR DSBGA YFP 6 3000 182.0 182.0 20.0
TPS6208812YFPT DSBGA YFP 6 250 210.0 185.0 35.0
TPS62088AYFPJ DSBGA YFP 6 12000 182.0 182.0 20.0
TPS62088AYFPR DSBGA YFP 6 3000 182.0 182.0 20.0
TPS62088YWCR DSBGA YWC 6 3000 182.0 182.0 20.0
TPS62089AYFPR DSBGA YFP 6 3000 182.0 182.0 20.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated

Tps 62088

Uploaded by

Copyright:

Available Formats

Tps 62088

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Tps 62088

Uploaded by

Copyright:

Available Formats

TPS62088, TPS62088A, TPS62089A

SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021

3.3-V Input Voltage Efficiency

Changes from Revision C (May 2019) to Revision D (September 2019) Page

2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TPS62088 TPS62088A TPS62089A

6 Pin Configuration and Functions

Table 6-1. Pin Functions

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TPS62088 TPS62088A TPS62089A

7.5 Electrical Characteristics

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5

7.6 Typical Characteristics

Figure 7-3. Quiescent Current Figure 7-4. Shutdown Current

6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TPS62088 TPS62088A TPS62089A

Peak Current Detect

VSW Direct Control

Zero Current Detect

8.3 Feature Description

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7

VIN,MIN = VOUT + IOUT,MAX ´ (RDS(on) + RL )

8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TPS62088 TPS62088A TPS62089A

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9

9 Application and Implementation

9.1 Application Information

Copyright Ú 2017, Texas Instruments Incorporated

Figure 9-1. Typical Application of Adjustable Output

Copyright Ú 2017, Texas Instruments Incorporated

Figure 9-2. Typical Application of Fixed Output

9.2.1 Design Requirements

10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TPS62088 TPS62088A TPS62089A

Table 9-2 lists the components used for the example.

(1) See Third-party Products disclaimer.

Table 9-3. List of Components of Figure 9-2, Smallest Solution

(1) See Third-party Products disclaimer.

9.2.2 Detailed Design Procedure

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11

9.2.2.3 Feedforward Capacitor

9.2.2.4 Output Filter Design

9.2.2.5 Inductor Selection

12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TPS62088 TPS62088A TPS62089A

Table 9-5. List of Recommended Inductors(1) (continued)

(1) See Third-party Products disclaimer.

9.2.2.6 Capacitor Selection

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13

9.2.3 Application Curves

55 0.594 VIN = 2.5 V

Figure 9-5. Efficiency Figure 9-6. Load Regulation

14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TPS62088 TPS62088A TPS62089A

Figure 9-9. Efficiency Figure 9-10. Load Regulation

VOUT = 1.2 V VOUT = 1.2 V