UDIMM DDR2 SDRAM

DDR2 Unbuffered SDRAM MODULE

240pin Unbuffered Module based on 2Gb A-die

64/72-bit Non-ECC/ECC

68FBGA with Lead-Free and Halogen-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

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UDIMM DDR2 SDRAM
Table of Contents

1.0 DDR2 Unbuffered DIMM Ordering Information ..........................................................................4

2.0 Features .........................................................................................................................................4
3.0 Address Configuration .................................................................................................................4
4.0 x64 DIMM Pin Configurations (Front side/Back side) ................................................................5
5.0 x72 DIMM Pin Configurations (Front side/Back side) ................................................................6
6.0 Pin Description ..............................................................................................................................6
7.0 Input/Output Function Description .............................................................................................7
8.0 Functional Block Diagram : .........................................................................................................8
8.1 4GB, 512Mx64 Module - M378T5263AZ(H)3 ......................................................................................8
8.2 4GB, 512Mx72 ECC Module - M391T5263AZ(H)3 ...............................................................................9
9.0 Absolute Maximum DC Ratings .................................................................................................10
10.0 AC & DC Operating Conditions ...............................................................................................10
10.1 Recommended DC Operating Conditions (SSTL - 1.8) ...................................................................10
10.2 Operating Temperature Condition ...............................................................................................11
10.3 Input DC Logic Level .................................................................................................................11
10.4 Input AC Logic Level .................................................................................................................11
10.5 AC Input Test Conditions ...........................................................................................................11
11.0 IDD Specification Parameters Definition ................................................................................12
12.0 Operating Current Table : ........................................................................................................13
12.1 M378T5263AZ(H)3 : 4GB(256Mx8 *16) Module ..............................................................................13
12.2 M391T5263AZ(H)3 : 4GB(256Mx8 *18) ECC Module .......................................................................13
13.0 Input/Output Capacitance ........................................................................................................14
14.0 Electrical Characteristics & AC Timing for DDR2-800/667/533 .............................................14
14.1 Refresh Parameters by Device Density ........................................................................................14
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .............................................14
14.3 Timing parameters by speed grade (DDR2-800 and DDR2-667) ........................................................15
14.4 Timing parameters by speed grade (DDR2-533) ..............................................................................17
15.0 Physical Dimensions : ..............................................................................................................19

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UDIMM DDR2 SDRAM
Revision History
Revision Month Year History
1.0 December 2007 - Initial Release
1.1 July 2008 - Applied JEDEC update(JESD79-2E) on AC timing table
1.2 September 2008 - Erased the product of 800Mbps CL5 speed

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UDIMM DDR2 SDRAM
1.0 DDR2 Unbuffered DIMM Ordering Information
Part Number Density Organization Component Composition Number of Rank Height
x64 Non ECC
M378T5263AZ(H)3-CF7/E6/D5 4GB 512Mx64 256Mx8(K4T2G084QA)*16 2 30mm
x72 ECC
M391T5263AZ(H)3-CF7/E6/D5 4GB 512Mx72 256Mx8(K4T2G084QA)*18 2 30mm
Note :
1. “Z” of Part number(12th digit) stands for Lead-Free products.
2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
3. “3” of Part number(13th digit) stands for Dummy Pad PCB products.

2.0 Features
• Performance range
F7 (DDR2-800) E6 (DDR2-667) D5 (DDR2-533) Unit
Speed@CL3 - 400 400 Mbps
Speed@CL4 533 533 533 Mbps
Speed@CL5 667 667 533 Mbps
Speed@CL6 800 - - Mbps
CL-tRCD-tRP 6-6-6 5-5-5 4-4-4 CK
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
- Support High Temperature Self-Refresh rate enable feature
• Package: 68ball FBGA - 128Mx8
• All of base components are Lead-Free, Halogen-Free, and RoHS compliant

Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.

3.0 Address Configuration

Organization Row Address Column Address Bank Address Auto Precharge
256Mx8(2Gb) based Module A0-A14 A0-A9 BA0-BA2 A10

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UDIMM DDR2 SDRAM
4.0 x64 DIMM Pin Configurations (Front side/Back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1 VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5
2 VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 NC
3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS
4 DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46
5 VSS 125 DM0 35 VSS 155 DM3 KEY 95 DQ42 215 DQ47
6 DQS0 126 NC 36 DQS3 156 NC 65 VSS 185 CK0 96 DQ43 216 VSS
7 DQS0 127 VSS 37 DQS3 157 VSS 66 VSS 186 CK0 97 VSS 217 DQ52
8 VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53
9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC 188 A0 99 DQ49 219 VSS
10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 CK2
11 VSS 131 DQ12 41 VSS 161 NC 70 A10/AP 190 BA1 101 SA2 221 CK2
12 DQ8 132 DQ13 42 NC 162 NC 71 BA0 191 VDDQ 102 NC, TEST1 222 VSS
13 DQ9 133 VSS 43 NC 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6
14 VSS 134 DM1 44 VSS 164 NC 73 WE 193 S0 104 DQS6 224 NC
15 DQS1 135 NC 45 NC 165 NC 74 CAS 194 VDDQ 105 DQS6 225 VSS
16 DQS1 136 VSS 46 NC 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54
17 VSS 137 CK1 47 VSS 167 NC 76 S1 196 A13 107 DQ50 227 DQ55
18 NC 138 CK1 48 NC 168 NC 77 ODT1 197 VDD 108 DQ51 228 VSS
19 NC 139 VSS 49 NC 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60
20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 DQ61
21 DQ10 141 DQ15 51 VDDQ 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS
22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7
23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4 113 DQS7 233 NC
24 DQ16 144 DQ21 54 NC 174 A14 83 DQS4 203 NC 114 DQS7 234 VSS
25 DQ17 145 VSS 55 NC 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62
26 VSS 146 DM2 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63
27 DQS2 147 NC 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS
28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD
29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0
30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1
90 DQ41 210 VSS

NC = No Connect, RFU = Reserved for Future Use

1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)

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UDIMM DDR2 SDRAM
5.0 x72 DIMM Pin Configurations (Front side/Back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1 VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5
2 VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 NC
3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS
4 DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46
5 VSS 125 DM0 35 VSS 155 DM3 KEY 95 DQ42 215 DQ47
6 DQS0 126 NC 36 DQS3 156 NC 65 VSS 185 CK0 96 DQ43 216 VSS
7 DQS0 127 VSS 37 DQS3 157 VSS 66 VSS 186 CK0 97 VSS 217 DQ52
8 VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53
9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC 188 A0 99 DQ49 219 VSS
10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 CK2
11 VSS 131 DQ12 41 VSS 161 CB4 70 A10/AP 190 BA1 101 SA2 221 CK2
12 DQ8 132 DQ13 42 CB0 162 CB5 71 BA0 191 VDDQ 102 NC, TEST1 222 VSS
13 DQ9 133 VSS 43 CB1 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6
14 VSS 134 DM1 44 VSS 164 DM8 73 WE 193 S0 104 DQS6 224 NC
15 DQS1 135 NC 45 DQS8 165 NC 74 CAS 194 VDDQ 105 DQS6 225 VSS
16 DQS1 136 VSS 46 DQS8 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54
17 VSS 137 CK1 47 VSS 167 CB6 76 S1 196 A13 107 DQ50 227 DQ55
18 NC 138 CK1 48 CB2 168 CB7 77 ODT1 197 VDD 108 DQ51 228 VSS
19 NC 139 VSS 49 CB3 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60
20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 DQ61
21 DQ10 141 DQ15 51 VDDQ 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS
22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7
23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4 113 DQS7 233 NC
24 DQ16 144 DQ21 54 NC 174 A14 83 DQS4 203 NC 114 DQS7 234 VSS
25 DQ17 145 VSS 55 NC 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62
26 VSS 146 DM2 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63
27 DQS2 147 NC 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS
28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD
29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0
30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1
90 DQ41 210 VSS

NC = No Connect, RFU = Reserved for Future Use

1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)

6.0 Pin Description

Pin Name Description Pin Name Description
A0-A14 DDR2 SDRAM address bus CK0, CK1, CK2 DDR2 SDRAM clocks (positive line of differential pair)
BA0-BA2 DDR2 SDRAM bank select CK0, CK1, CK2 DDR2 SDRAM clocks (negative line of differential pair)
RAS DDR2 SDRAM row address strobe SCL I2C serial bus clock for EEPROM
CAS DDR2 SDRAM column address strobe SDA I2C serial bus data line for EEPROM
WE DDR2 SDRAM wirte enable SA0-SA2 I2C serial address select for EEPROM
S0, S1 DIMM Rank Select Lines VDD* DDR2 SDRAM core power supply
CKE0,CKE1 DDR2 SDRAM clock enable lines VDDQ* DDR2 SDRAM I/O Driver power supply
ODT0, ODT1 On-die termination control lines VREF DDR2 SDRAM I/O reference supply
DQ0 - DQ63 DIMM memory data bus VSS Power supply return (ground)
CB0 - CB7 DIMM ECC check bits VDDSPD Serial EEPROM positive power supply
DQS0 - DQS8 DDR2 SDRAM data strobes NC Spare Pins(no connect)
DM(0-8) DDR2 SDRAM data masks RESET Not used on UDIMM
Used by memory bus analysis tools
DQS0-DQS8 DDR2 SDRAM differential data strobes TEST
(unused on memory DIMMs)
*The VDD and VDDQ pins are tied to the single power-plane on PCB.

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UDIMM DDR2 SDRAM
7.0 Input/Output Function Description
Symbol Type Description

CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of
CK0-CK2 Input positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK
CK0-CK2
(Both directions of crossing)

Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the
CKE0-CKE1 Input
clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode

Enables the associated SDRAM command decoder when low and disables the command decoder when
S0-S1 Input high. When the command decoder is disbled, new command are ignored but previous operations continue.
This signal provides for external rank selection on systems with multiple ranks

RAS, CAS, WE Input RAS, CAS, and WE (ALONG WITH CS) define the command being entered.

When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled
ODT0-ODT1 Input
in the Extended Mode Register Set (EMRS).

VREF Supply Reference voltage for SSTL 18 inputs.

Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current
VDDQ Supply DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.

BA0-BA2 Input Selects which SDRAM BANK of four is activated.

During a Bank Activate command cycle, Address input defines the row address (RA0-RA14)
During a Read or Write command cycle, Address input defines the colum address, In addition to the column
A0-A14 Input address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is
high, autoprecharge is selected and BA0-BA2 defines the bank to be precharged. If AP is low, autopre-
charge is disbled. During a precharge command cycle, AP is used in conjunction with BA0-BA2 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BA2.
If AP is low, BA0, BA1, BA2 are used to define which bank to precharge.

DQ0-DQ63 In/Out Data and Check Bit Input/Output pins.

CB0-CB7

DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with
DM0-DM8 Input that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading.
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/
VDD,VSS Supply
VDDQ planes on these modules.

DQS0-DQS8 Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the
In/Out
DQS0-DQS8 LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM
These signals and tied at the system planar to either VSS or VDD to configure the serial SPD EERPOM
SA0-SA2 Input
address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected
SDA In/Out
from the SDA bus line to VDD to act as a pullup on the system board.

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UDIMM DDR2 SDRAM
8.0 Functional Block Diagram :

8.1 4GB, 512Mx64 Module - M378T5263AZ(H)3

(Populated as 2 rank of x8 DDR2 SDRAMs)
S1
S0
DQS0 DQS4
DQS0 DQS4
DM0 DM4

DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS

DQ0 I/O 0 I/O 0 DQ32 I/O 0 I/O 0

DQ1 I/O 1 D0 I/O 1 D8 DQ33 I/O 1 D4 I/O 1 D12
DQ2 I/O 2 I/O 2 DQ34 I/O 2 I/O 2
DQ3 I/O 3 I/O 3 DQ35 I/O 3 I/O 3
DQ4 I/O 4 I/O 4 DQ36 I/O 4 I/O 4
DQ5 I/O 5 I/O 5 DQ37 I/O 5 I/O 5
DQ6 I/O 6 I/O 6 DQ38 I/O 6 I/O 6
DQ7 I/O 7 I/O 7 DQ39 I/O 7 I/O 7

DQS1 DQS5
DQS1 DQS5
DM1 DM5

DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS

DQ8 I/O 0 I/O 0 DQ40 I/O 0 I/O 0

DQ9 I/O 1 D1 I/O 1 D9 DQ41 I/O 1 D5 I/O 1 D13
DQ10 I/O 2 I/O 2 DQ42 I/O 2 I/O 2
DQ11 I/O 3 I/O 3 DQ43 I/O 3 I/O 3
DQ12 I/O 4 I/O 4 DQ44 I/O 4 I/O 4
DQ13 I/O 5 I/O 5 DQ45 I/O 5 I/O 5
DQ14 I/O 6 I/O 6 DQ46 I/O 6 I/O 6
DQ15 I/O 7 I/O 7 DQ47 I/O 7 I/O 7

DQS2 DQS6
DQS2 DQS6
DM2 DM6

DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS

DQ16 I/O 0 I/O 0 DQ48 I/O 0 I/O 0

DQ17 I/O 1 D2 I/O 1 D10 DQ49 I/O 1 D6 I/O 1 D14
DQ18 I/O 2 I/O 2 DQ50 I/O 2 I/O 2
DQ19 I/O 3 I/O 3 DQ51 I/O 3 I/O 3
DQ20 I/O 4 I/O 4 DQ52 I/O 4 I/O 4
DQ21 I/O 5 I/O 5 DQ53 I/O 5 I/O 5
DQ22 I/O 6 I/O 6 DQ54 I/O 6 I/O 6
DQ23 I/O 7 I/O 7 DQ55 I/O 7 I/O 7

DQS3 DQS7
DQS3 DQS7
DM3 DM7

DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS

DQ24 I/O 0 I/O 0 DQ56 I/O 0 I/O 0

DQ25 I/O 1 D3 I/O 1 D11 DQ57 I/O 1 D7 I/O 1 D15
DQ26 I/O 2 I/O 2 DQ58 I/O 2 I/O 2
DQ27 I/O 3 I/O 3 DQ59 I/O 3 I/O 3
DQ28 I/O 4 I/O 4 DQ60 I/O 4 I/O 4
DQ29 I/O 5 I/O 5 DQ61 I/O 5 I/O 5
DQ30 I/O 6 I/O 6 DQ62 I/O 6 I/O 6
DQ31 I/O 7 I/O 7 DQ63 I/O 7 I/O 7

VDDSPD Serial PD

Serial PD
VDD/VDDQ D0 - D15
SCL
VREF D0 - D15 WP SDA
A0 A1 A2
VSS D0 - D15
* Clock Wiring
SA0 SA1 SA2
BA0 - BA2 BA0-BA2 : DDR2 SDRAMs D0 - D15
Clock Input DDR2 SDRAMs
A0 - A14 A0-A14 : DDR2 SDRAMs D0 - D15 *CK0/CK0 4 DDR2 SDRAMs
CKE0 CKE : DDR2 SDRAMs D0 - D7 *CK1/CK1 6 DDR2 SDRAMs
CKE1 CKE : DDR2 SDRAMs D8 - D15 *CK2/CK2 6 DDR2 SDRAMs
RAS RAS : DDR2 SDRAMs D0 - D15 *Wire per Clock Loading
CAS CAS : DDR2 SDRAMs D0 - D15 Table/Wiring Diagrams

WE WE : DDR2 SDRAMs D0 - D15

Note :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
ODT0 ODT : DDR2 SDRAMs D0 - D7
2. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms ± 5%.
ODT1 ODT : DDR2 SDRAMs D8 - D15

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UDIMM DDR2 SDRAM

8.2 4GB, 512Mx72 ECC Module - M391T5263AZ(H)3

(Populated as 2 rank of x8 DDR2 SDRAMs)

S1
S0
DQS0 DQS4
DQS0 DQS4
DM0 DM4

DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS

DQ0 I/O 0 I/O 0 DQ32 I/O 0 I/O 0

DQ1 I/O 1 D0 I/O 1 D9 DQ33 I/O 1 D4 I/O 1 D13
DQ2 I/O 2 I/O 2 DQ34 I/O 2 I/O 2
DQ3 I/O 3 I/O 3 DQ35 I/O 3 I/O 3
DQ4 I/O 4 I/O 4 DQ36 I/O 4 I/O 4
DQ5 I/O 5 I/O 5 DQ37 I/O 5 I/O 5
DQ6 I/O 6 I/O 6 DQ38 I/O 6 I/O 6
DQ7 I/O 7 I/O 7 DQ39 I/O 7 I/O 7

DQS1 DQS5
DQS1 DQS5
DM1 DM5

DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS

DQ8 I/O 0 I/O 0 DQ40 I/O 0 I/O 0

DQ9 I/O 1 D1 I/O 1 D10 DQ41 I/O 1 D5 I/O 1 D14
DQ10 I/O 2 I/O 2 DQ42 I/O 2 I/O 2
DQ11 I/O 3 I/O 3 DQ43 I/O 3 I/O 3
DQ12 I/O 4 I/O 4 DQ44 I/O 4 I/O 4
DQ13 I/O 5 I/O 5 DQ45 I/O 5 I/O 5
DQ14 I/O 6 I/O 6 DQ46 I/O 6 I/O 6
DQ15 I/O 7 I/O 7 DQ47 I/O 7 I/O 7

DQS2 DQS6
DQS2 DQS6
DM2 DM6

DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS

DQ16 I/O 0 I/O 0 DQ48 I/O 0 I/O 0

DQ17 I/O 1 D2 I/O 1 D11 DQ49 I/O 1 D6 I/O 1 D15
DQ18 I/O 2 I/O 2 DQ50 I/O 2 I/O 2
DQ19 I/O 3 I/O 3 DQ51 I/O 3 I/O 3
DQ20 I/O 4 I/O 4 DQ52 I/O 4 I/O 4
DQ21 I/O 5 I/O 5 DQ53 I/O 5 I/O 5
DQ22 I/O 6 I/O 6 DQ54 I/O 6 I/O 6
DQ23 I/O 7 I/O 7 DQ55 I/O 7 I/O 7

DQS3 DQS7
DQS3 DQS7
DM3 DM7

DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS

DQ24 I/O 0 I/O 0 DQ56 I/O 0 I/O 0

DQ25 I/O 1 D3 I/O 1 D12 DQ57 I/O 1 D7 I/O 1 D16
DQ26 I/O 2 I/O 2 DQ58 I/O 2 I/O 2
DQ27 I/O 3 I/O 3 DQ59 I/O 3 I/O 3
DQ28 I/O 4 I/O 4 DQ60 I/O 4 I/O 4
DQ29 I/O 5 I/O 5 DQ61 I/O 5 I/O 5
DQ30 I/O 6 I/O 6 DQ62 I/O 6 I/O 6
DQ31 I/O 7 I/O 7 DQ63 I/O 7 I/O 7

DQS8
DQS8
DM8 Serial PD
DM CS DQS DQS DM CS DQS DQS
SCL
WP SDA
CB0 I/O 0 I/O 0
CB1 I/O 1 D8 I/O 1 D17 A0 A1 A2
CB2 I/O 2 I/O 2
CB3 I/O 3 I/O 3 SA0 SA1 SA2
CB4 I/O 4 I/O 4
CB5 I/O 5 I/O 5 * Clock Wiring
CB6 I/O 6 I/O 6
CB7 I/O 7 I/O 7 Clock Input DDR2 SDRAMs

VDDSPD Serial PD *CK0/CK0 6 DDR2 SDRAMs

BA0 - BA2 BA0-BA2 : DDR2 SDRAMs D0 - D17
*CK1/CK1 6 DDR2 SDRAMs
A0 - A14 A0-A14 : DDR2 SDRAMs D0 - D17 VDD/VDDQ D0 - D17 *CK2/CK2 6 DDR2 SDRAMs
CKE0 CKE : DDR2 SDRAMs D0 - D8
VREF D0 - D17 *Wire per Clock Loading
CKE1 CKE : DDR2 SDRAMs D9 - D17 Table/Wiring Diagrams
RAS RAS : DDR2 SDRAMs D0 - D17
VSS D0 - D17
CAS CAS : DDR2 SDRAMs D0 - D17
Note :
WE WE : DDR2 SDRAMs D0 - D17
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
ODT0 ODT : DDR2 SDRAMs D0 - D8
2. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms ± 5%.
ODT1 ODT : DDR2 SDRAMs D9 - D17

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UDIMM DDR2 SDRAM
9.0 Absolute Maximum DC Ratings
Symbol Parameter Rating Units Notes
VDD Voltage on VDD pin relative to VSS - 1.0 V ~ 2.3 V V 1
VDDQ Voltage on VDDQ pin relative to VSS - 0.5 V ~ 2.3 V V 1
VDDL Voltage on VDDL pin relative to VSS - 0.5 V ~ 2.3 V V 1
VIN, VOUT Voltage on any pin relative to VSS - 0.5 V ~ 2.3 V V 1
TSTG Storage Temperature -55 to +100 °C 1, 2

Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.

10.0 AC & DC Operating Conditions

10.1 Recommended DC Operating Conditions (SSTL - 1.8)

Rating
Symbol Parameter Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.7 1.8 1.9 V
VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 4
VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 4
VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 1,2
VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 3
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal
to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.

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UDIMM DDR2 SDRAM
10.2 Operating Temperature Condition
Symbol Parameter Rating Units Notes
TOPER Operating Temperature 0 to 95 °C 1, 2

Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

10.3 Input DC Logic Level

Symbol Parameter Min. Max. Units Notes
VIH(DC) DC input logic high VREF + 0.125 VDDQ + 0.3 V
VIL(DC) DC input logic low - 0.3 VREF - 0.125 V

10.4 Input AC Logic Level

DDR2-533 DDR2-667, DDR2-800
Symbol Parameter Units Notes
Min. Max. Min. Max.
VIH(AC) AC input logic high VREF + 0.250 - VREF + 0.200 V
VIL(AC) AC input logic low - VREF - 0.250 VREF - 0.200 V

10.5 AC Input Test Conditions

Symbol Condition Value Units Notes
VREF Input reference voltage 0.5 * VDDQ V 1
VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1
SLEW Input signal minimum slew rate 1.0 V/ns 2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.

VDDQ
VIH(AC) min
VIH(DC) min
VSWING(MAX)
VREF
VIL(DC) max
VIL(AC) max
VSS
delta TF delta TR

VREF - VIL(AC) max VIH(AC) min - VREF

Falling Slew = Rising Slew =
delta TF delta TR

< AC Input Test Signal Waveform >

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UDIMM DDR2 SDRAM
11.0 IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol Proposed Conditions Units Note
Operating one bank active-precharge current;
IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands; mA
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
IDD1 mA
tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDD4W
Precharge power-down current;
IDD2P All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are mA
FLOATING
Precharge quiet standby current;
IDD2Q All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data mA
bus inputs are FLOATING
Precharge standby current;
IDD2N All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; mA
Data bus inputs are SWITCHING
Active power-down current; Fast PDN Exit MRS(12) = 0mA mA
IDD3P All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING Slow PDN Exit MRS(12) = 1mA mA

Active standby current;

IDD3N All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid mA
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
IDD4W mA
tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-
IDD4R mA
max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
IDD5B tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; mA
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; Normal mA
IDD6 CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING Low Power mA

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =
IDD7 tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid com- mA
mands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following
page for detailed timing conditions

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UDIMM DDR2 SDRAM
12.0 Operating Current Table :
12.1 M378T5263AZ(H)3 : 4GB(256Mx8 *16) Module (TA=0oC, VDD= 1.9V)
800@CL6 667@CL=5 533@CL=4
Symbol Units Notes
CF7 CE6 CD5
IDD0 1,240 1,160 1,080 mA
IDD1 1,440 1,320 1,240 mA
IDD2P 240 240 240 mA
IDD2Q 880 800 720 mA
IDD2N 960 880 800 mA
IDD3P-F 800 640 640 mA
IDD3P-S 288 288 288 mA
IDD3N 1,120 1,000 920 mA
IDD4W 1,840 1,640 1,440 mA
IDD4R 2,080 1,800 1,600 mA
IDD5 2,720 2,520 2,400 mA
IDD6 240 240 240 mA
IDD7 3,280 3,000 2,720 mA

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

12.2 M391T5263AZ(H)3 : 4GB(256Mx8 *18) ECC Module (TA=0oC, VDD= 1.9V)

800@CL=6 667@CL=5 533@CL=4
Symbol Units Notes
CF7 CE6 CD5
IDD0 1,395 1,305 1,215 mA
IDD1 1,620 1,485 1,395 mA
IDD2P 270 270 270 mA
IDD2Q 990 900 810 mA
IDD2N 1,080 990 900 mA
IDD3P-F 900 720 720 mA
IDD3P-S 324 324 324 mA
IDD3N 1,260 1,125 1,035 mA
IDD4W 2,070 1,845 1,620 mA
IDD4R 2,340 2,025 1,800 mA
IDD5 3,060 2,835 2,700 mA
IDD6 270 270 270 mA
IDD7 3,690 3,375 3,060 mA

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

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UDIMM DDR2 SDRAM
13.0 Input/Output Capacitance (VDD=1.8V, VDDQ=1.8V, TA=25oC)

Parameter Min Max

Symbol Units
Non-ECC M378T5263AZ(H)3
CCK0 - 26
Input capacitance, CK and CK CCK1 - 28
CCK2 - 28 pF
Input capacitance, CKE and CS CI1 - 42

Input capacitance, Addr, RAS, CAS, WE CI2 - 42

Input/output capacitance, DQ, DM, DQS, DQS CIO - 10
ECC M391T5263AZ(H)3 Units
CCK0 - 28
Input capacitance, CK and CK CCK1 - 28
CCK2 - 28 pF
Input capacitance, CKE and CS CI1 - 44

Input capacitance, Addr, RAS, CAS, WE CI2 - 44

Input/output capacitance, DQ, DM, DQS, DQS CIO - 10
Note : DM is internally loaded to match DQ and DQS identically.

14.0 Electrical Characteristics & AC Timing for DDR2-800/667/533

(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)

14.1 Refresh Parameters by Device Density

Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units
Refresh to active/Refresh command time tRFC 75 105 127.5 195 327.5 ns
0 °C ≤ TCASE ≤ 85°C 7.8 7.8 7.8 7.8 7.8 µs
Average periodic refresh interval tREFI
85 °C < TCASE ≤ 95°C 3.9 3.9 3.9 3.9 3.9 µs

14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed DDR2-800(F7) DDR2-667(E6) DDR2-533(D5)
Bin(CL - tRCD - tRP) 6 - 6- 6 5-5-5 4-4-4 Units
Parameter min max min max min max
tCK, CL=3 - - 5 8 5 8 ns
tCK, CL=4 3.75 8 3.75 8 3.75 8 ns
tCK, CL=5 3 8 3 8 3.75 8 ns
tCK, CL=6 2.5 8 - - - - ns
tRCD 15 - 15 - 15 - ns
tRP 15 - 15 - 15 - ns
tRC 60 - 60 - 60 - ns
tRAS 45 70000 45 70000 45 70000 ns

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UDIMM DDR2 SDRAM
14.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)
(Refer to notes for informations related to this table at the component datasheet)
DDR2-800 DDR2-667
Parameter Symbol Units Notes
min max min max
DQ output access time from CK/CK tAC -400 400 -450 450 ps 40
DQS output access time from CK/CK tDQSCK -350 350 -400 400 ps 40
Average clock HIGH pulse width tCH(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36
Average clock LOW pulse width tCL(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36
Min(tCL(abs), Min(tCL(abs),
CK half pulse period tHP x x ps 37
tCH(abs)) tCH(abs))
Average clock period tCK(avg) 2500 8000 3000 8000 ps 35,36
DQ and DM input hold time tDH(base) 125 x 175 x ps 6,7,8,21,28,31
DQ and DM input setup time tDS(base) 50 x 100 x ps 6,7,8,20,28,31
Control & Address input pulse width for each input tIPW 0.6 x 0.6 x tCK(avg)
DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x tCK(avg)
Data-out high-impedance time from CK/CK tHZ x tAC(max) x tAC(max) ps 18,40
DQS/DQS low-impedance time from CK/CK tLZ(DQS) tAC(min) tAC(max) tAC(min) tAC(max) ps 18,40
DQ low-impedance time from CK/CK tLZ(DQ) 2* tAC(min) tAC(max) 2* tAC(min) tAC(max) ps 18,40
DQS-DQ skew for DQS and associated DQ signals tDQSQ x 200 x 240 ps 13
DQ hold skew factor tQHS x 300 x 340 ps 38
DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x ps 39
DQS latching rising transitions to associated clock edges tDQSS - 0.25 0.25 -0.25 0.25 tCK(avg) 30
DQS input HIGH pulse width tDQSH 0.35 x 0.35 x tCK(avg)
DQS input LOW pulse width tDQSL 0.35 x 0.35 x tCK(avg)
DQS falling edge to CK setup time tDSS 0.2 x 0.2 x tCK(avg) 30
DQS falling edge hold time from CK tDSH 0.2 x 0.2 x tCK(avg) 30
Mode register set command cycle time tMRD 2 x 2 x nCK
MRS command to ODT update delay tMOD 0 12 0 12 ns 32
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK(avg) 10
Write preamble tWPRE 0.35 x 0.35 x tCK(avg)
Address and control input hold time tIH(base) 250 x 275 x ps 5,7,9,23,29
Address and control input setup time tIS(base) 175 x 200 x ps 5,7,9,22,29
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK(avg) 19,41
Read postamble tRPST 0.4 0.6 0.4 0.6 tCK(avg) 19,42
Activate to activate command period for 1KB page size products tRRD 7.5 x 7.5 x ns 4,32
Activate to activate command period for 2KB page size products tRRD 10 x 10 x ns 4,32

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UDIMM DDR2 SDRAM

DDR2-800 DDR2-667
Parameter Symbol Units Notes
min max min max
Four Activate Window for 1KB page size products tFAW 35 x 37.5 x ns 32
Four Activate Window for 2KB page size products tFAW 45 x 50 x ns 32
CAS to CAS command delay tCCD 2 x 2 x nCK
Write recovery time tWR 15 x 15 x ns 32
Auto precharge write recovery + precharge time tDAL WR + tnRP x WR + tnRP x nCK 33
Internal write to read command delay tWTR 7.5 x 7.5 x ns 24,32
Internal read to precharge command delay tRTP 7.5 x 7.5 x ns 3,32
Exit self refresh to a non-read command tXSNR tRFC + 10 x tRFC + 10 x ns 32
Exit self refresh to a read command tXSRD 200 x 200 x nCK
Exit precharge power down to any command tXP 2 x 2 x nCK
Exit active power down to read command tXARD 2 x 2 x nCK 1
Exit active power down to read command
tXARDS 8 - AL x 7 - AL x nCK 1,2
(slow exit, lower power)
CKE minimum pulse width (HIGH and LOW pulse width) tCKE 3 x 3 x nCK 27
ODT turn-on delay tAOND 2 2 2 2 nCK 16
ODT turn-on tAON tAC(min) tAC(max)+0.7 tAC(min) tAC(max)+0.7 ns 6,16,40
2*tCK(avg) 2*tCK(avg)
ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 tAC(min)+2 ns
+tAC(max)+1 +tAC(max)+1
ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 nCK 17,45
ODT turn-off tAOF tAC(min) tAC(max)+0.6 tAC(min) tAC(max)+0.6 ns 17,43,45
2.5*tCK(avg) 2.5*tCK(avg)
ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 tAC(min)+2 ns
+tAC(max)+1 +tAC(max)+1
ODT to power down entry latency tANPD 3 x 3 x nCK
ODT power down exit latency tAXPD 8 x 8 x nCK
OCD drive mode output delay tOIT 0 12 0 12 ns 32
Minimum time clocks remains ON after CKE asynchronously tIS+tCK(avg) tIS+tCK(avg)
tDelay x x ns 15
drops LOW +tIH +tIH

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UDIMM DDR2 SDRAM
14.4 Timing parameters by speed grade (DDR2-533)
(Refer to notes for informations related to this table at the component datasheet)
DDR2-533
Parameter Symbol Units Notes
min max
DQ output access time from CK/CK tAC -500 500 ps
DQS output access time from CK/CK tDQSCK -450 450 ps
CK HIGH pulse width tCH 0.45 0.55 tCK
CK LOW pulse width tCL 0.45 0.55 tCK
CK half pulse period tHP Min(tCL, tCH) x ps 11,12
Clock cycle time, CL=x tCK 3750 8000 ps 15
DQ and DM input hold time (differential strobe) tDH(base) 225 x ps 6,7,8,21,28
DQ and DM input setup time (differential strobe) tDS(base) 100 x ps 6,7,8,20,28
DQ and DM input hold time (single-ended strobe) tDH1(base) -25 x ps 6,7,8,26
DQ and DM input setup time (single-ended strobe) tDS1(base) -25 x ps 6,7,8,25
Control & Address input pulse width for each input tIPW 0.6 x tCK
DQ and DM input pulse width for each input tDIPW 0.35 x tCK
Data-out high-impedance time from CK/CK tHZ x tAC(max) ps 18
DQS(/DQS) low-impedance time from CK/CK tLZ(DQS) tAC(min) tAC(max) ps 18
DQ low-impedance time from CK/CK tLZ(DQ) 2* tAC(min) tAC(max) ps 18
DQS-DQ skew for DQS and associated DQ signals tDQSQ x 300 ps 13
DQ hold skew factor tQHS x 400 ps 12
DQ/DQS output hold time from DQS tQH tHP - tQHS x ps
DQS latching rising transitions to associated clock edges tDQSS -0.25 0.25 tCK
DQS input HIGH pulse width tDQSH 0.35 x tCK
DQS input LOW pulse width tDQSL 0.35 x tCK
DQS falling edge to CK setup time tDSS 0.2 x tCK
DQS falling edge hold time from CK tDSH 0.2 x tCK
Mode register set command cycle time tMRD 2 x tCK
MRS command to ODT update delay tMOD 0 12 ns
Write postamble tWPST 0.4 0.6 tCK 10
Write preamble tWPRE 0.35 x tCK
Address and control input hold time tIH(base) 375 x ps 5,7,9,23
Address and control input setup time tIS(base) 250 x ps 5,7,9,22
Read preamble tRPRE 0.9 1.1 tCK 19
Read postamble tRPST 0.4 0.6 tCK 19
Active to active command period for 1KB page size products tRRD 7.5 x ns 4
Active to active command period for 2KB page size products tRRD 10 x ns 4

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UDIMM DDR2 SDRAM

DDR2-533
Parameter Symbol Units Notes
min max
Four Activate Window for 1KB page size products tFAW 37.5 x ns
Four Activate Window for 2KB page size products tFAW 50 x ns
CAS to CAS command delay tCCD 2 x tCK
Write recovery time tWR 15 x ns
Auto precharge write recovery + precharge time tDAL WR+tRP x tCK 14
Internal write to read command delay tWTR 7.5 x ns 24
Internal read to precharge command delay tRTP 7.5 x ns 3
Exit self refresh to a non-read command tXSNR tRFC + 10 x ns
Exit self refresh to a read command tXSRD 200 x tCK
Exit precharge power down to any non-read command tXP 2 x tCK
Exit active power down to read command tXARD 2 x tCK 1
Exit active power down to read command
tXARDS 6 - AL x tCK 1,2
(slow exit, lower power)
CKE minimum pulse width (HIGH and LOW pulse width) tCKE 3 x tCK 27
ODT turn-on delay tAOND 2 2 tCK 16
ODT turn-on tAON tAC(min) tAC(max)+1 ns 16
2tCK+
ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 ns
tAC(max)+1
ODT turn-off delay tAOFD 2.5 2.5 tCK 17,44
tAC(max)
ODT turn-off tAOF tAC(min) ns 17,44
+ 0.6
2.5tCK+
ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 ns
tAC(max)+1
ODT to power down entry latency tANPD 3 x tCK
ODT power down exit latency tAXPD 8 x tCK
OCD drive mode output delay tOIT 0 12 ns 32
Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay tIS+tCK+tIH x ns 15

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UDIMM DDR2 SDRAM
15.0 Physical Dimensions :

256Mbx8 based 512Mx64(x72) Module(2 Rank)

- M378(91)T5263AZ(H)3 Units : Millimeters

133.35

131.35
4.0 mm

(2X)4.00
128.95

N/A
(for x64)
10.00

ECC SPD
(for x72)
30.00

2.30
1.0 max

17.80
(2)
2.50
1.27 ± 0.10

A B
63.00 55.00

N/A
(for x64)
ECC
(for x72)

3.00
2.50±0.20

5.00
4.00 0.80±0.05
4.00

3.80 0.20

2.50 4.00
1.50±0.10 1.00

Detail A Detail B

The used device is 256M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T2G084QA

19 of 19 Rev. 1.2 September 2008