Pipelining Basic Concepts and Approaches
Pipelining Basic Concepts and Approaches
ISSN 2229-5518
Abstract-This paper is concerned with the pipelining principles while designing a processor.The basics of instruction pipeline are
discussed and an approach to minimize a pipeline stall is explained with the help of example.The main idea is to understand the working of
a pipeline in a processor.Various hazards that cause pipeline degradation are explained and solutions to minimize them are discussed.
Index Terms— Data dependency, Hazards in pipeline, Instruction dependency, parallelism, Pipelining, Processor, Stall.
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1 INTRODUCTION does the paint. Still,2 rooms are idle. These rooms that I want
to paint constitute my hardware.The painter and his skills are
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pendent tasks,but what i am limiting is the resources.
semblies developed for developing its chasis,adding a part to
I hope having this comcept in mind,now the reader knows
its body,wheels alignment and painting the parts.All this to-
what he has to do with his computer to achieve a maximum
gether bring up your favourite car,every assembly line adding utilization.[2]
to the perfection and doing their best.Now,if these units wait
for resources or we can say that if the second stage is depend- 3 DIFFERENCE BETWEEN SEQUENTIAL PRO-
ent on the first one,then more time will be consumed in build- CESSING AND PIPELINING :
ing the car.So,we divide the tasks in such a way that their de-
pendency is relaxed.In pipelining a task on computer,we ei- Below is an illustration of the basic difference between execut-
ther divide it in such a way that one task is independent of the ing four subtasks of a given instruction (in this case fetching F,
other so that hardware units can switch the tasks between decoding D, execution E, and writing the results W) using
them using a clock or we add a hardware circuitry to speed up pipelining and sequential processing.[3]
the tasks. The second approach adds up the cost while the first
one results in the efficient utilization of available resources,to
what we call Pipelining.[1]
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the succession of the sub-tasks in the pipe with respect to
time.[4] SUB R4,R5,R1 IF ID SUB EX MEM WB
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ISSN 2229-5518
an instruction that started three cycles earlier. Forwarding can
1 2 3 4 5 6 7 be arranged from MEM/WB latch to ALU input also. Using
those forwarding paths the code sequence can be executed
ADD R1, R2, R3 IF ID EX add MEM add WB
without stalls:
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latch), then the need for a stall can be avoided. than one pipe stage or allow an instruction to proceed even
Using this observation , forwarding works as follows: when a previous instruction is stalled. The DLX integer pipe-
line writes a register only in WB and avoids this class of haz-
-The ALU result from the EX/MEM register is always fed ards.
back to the ALU input latches.
-If the forwarding hardware detects that the previous ALU WAW hazards would be possible if we made the following
operation has written the register corresponding to the source two changes to the DLX pipeline:
for the current ALU operation, control logic selects the for-
warded result as the ALU input rather than the value read ▪move write back for an ALU operation into the MEM stage,
from the register file. since the data value is available by then.
▪suppose that the data memory access took two pipe stages.
Forwarding of results to the ALU requires the additional of Here is a sequence of two instructions showing the execution
three extra inputs on each ALU multiplexer and the addtion in this revised pipeline, highlighting the pipe stage that writes
of three paths to the new inputs. the result:
This can not happen in our example pipeline because all reads OR instruction has no problem, since it receives the value
are early (in ID) and all writes are late (in WB). This hazard through the register file (ID). In clock cycle no. 5, the WB of
occurs when there are some instructions that write results ear- the LW instruction occurs "early" in first half of the cycle and
ly in the instruction pipeline, and other instructions that read a the register read of the OR instruction occurs "late" in the se-
source late in the pipeline. cond half of the cycle.
Because of the natural structure of a pipeline, which typically For SUB instruction, the forwarded result would arrive too
reads values before it writes results, such hazards are rare. late - at the end of a clock cycle, when needed at the begin-
Pipelines for complex instruction sets that support autoincre- ning.
ment addressing and require operands to be read late in the
pipeline could create a WAR hazards. The load instruction has a delay or latency that cannot be elim-
inated by forwarding alone. Instead, we need to add hard-
If we modified the DLX pipeline as in the above example and ware, called a pipeline interlock, to preserve the correct execu-
also read some operands late, such as the source value for a tion pattern. In general, a pipeline interlock detects a hazard
store instruction, a WAR hazard could occur. Here is the pipe- and stalls the pipeline until the hazard is cleared.
line timing for such a potential hazard, highlighting the stage
where the conflict occurs: The pipeline with a stall and the legal forwarding is:
1 2 3 4 5 6 7 8 9
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SW R1, 0(R2) IF ID EX MEM1 MEM2 WB
LW R1, 0(R1) IF ID EX MEM WB
Solution:
1.The DLX assembly code for the given sequence of statements
The LW instruction does not have the data until the end of is:
clock cycle 4 (MEM) , while the SUB instruction needs to have
the data by the beginning of that clock cycle (EX sub ).
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Rd read in
SW Rd, d IF ID EX M WB second half
of ID;
Rg read in
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Sub Re, second half
IF ID EX M WB
Rg, Rh of ID;
LW Rb, b IF ID EX M WB Rh forwarded
LW Rc, c IF ID EX M WB
Add Ra,Rb,
IF ID stall EX M WB
Rc
SW Ra, a IF stall ID EX M WB
SW Re, e IF ID EX M WB Re forwarded
LW Rf, f stall IF ID EX M WB
Running this code segment will need some forwarding. But Note: Notice that the use of different registers for the first, se-
instructions LW and ALU(Add or Sub), when put in sequence, cond and third statements was critical for this schedule to be
are generating hazards for the pipeline that can not be re- legal! In general, pipeline scheduling can increase the register
solved by forwarding. So the pipeline will stall. Observe that count required.
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in time steps 4, 5, and 6, there are two forwards from the Data
memory unit to the ALU in the EX stage of the Add instruc- 7 CONCLUSION :
tion. So also the case in time steps 13, 14, and 15. The hard-
ware to implement this forwarding will need two Load
In this paper, the basic principles involved in designing pipe-
Memory Data registers to store the output of data memory.
line architectures were considered.Our coverage started with a
Note that for the SW instructions, the register value is needed
discussion on a number of metrics that can be used to assess
at the input of Data memory. The better solution with compil-
the goodness of a pipeline.We then moved to present a general
er assist is given below.
discussion on the main problems that need to be considered in
designing a pipelined architecture.
Rather then just allow the pipeline to stall, the compiler could
try to schedule the pipeline to avoid these stalls by rearrang-
– In particular two main problems are considered :- Instruc-
ing the code sequence to eliminate the hazards.[7]
tion and data dependency.
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