Faculty of Engineering

DEPARTMENT of ELECTRICAL AND ELECTRONIC

ENGINEERING

EENG447
Digital IC Design

Gürtaç Yemişcioğlu

Physical Layout Lab Manual

Date
29.11.17

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EENG447 Digital IC Design – Layout Lab Manual 13-Dec-17

Create a Project Folder

Create a folder to locate physical layout project files.

1. Open your existing EENG447 Lab folder and create a New Folder called “Layout”. (Do not use any
space between the characters!)

Figure 1: Create a new folder in EENG447_LAB and named as Layout.

LAUNCH L-EDIT
1. Launch L-Edit Physical Layout Editor.
2. On your desktop find an icon shown in Figure 2. Double click and launch the S-Edit.

Figure 2: L-Edit Icon.

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3. The application window shown in Figure 3 will appear.

Figure 3: L-Edit Application Window.

Figure 4: L-Edit User Interface.

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Figure 5: Tool Bars.

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Figure 6: Toolbars.

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Figure 7: Layer Palette.

Design Setup
Every L-Edit file contains basic information such as a layer list, technology settings and module – specific
options for SPR, DRC, and Extract. Collectively, this information is known as the “setup.” File  Replace
Setup lets you import setup information from a source file to the current file.

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Create a New Design

1. To create a new design, from the menu bar go to File New

Figure 8: New Design Dialog Box.

2. Select File type: Layout

3. Copy TDB setup from file:
a. Click Browse
b. Navigate through the AMSC35_14.3  L-EDIT  LIBRARIES  AMSC35_techfile

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Figure 9: AMS Layout Tech File.

c. Click Open

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4. Click OK.

5. L-Edit is ready to do physical layout design.

6. On the left Process specific Layer Palette will appear.

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7. Extra Rules for DRC.

a. Click on Setup Interactive DRC icon and scroll down to the end of the rules.
b. Enter the following rules
Layer DRC Rule Layer Distance (microns)
CONT Spacing POLY1 0.300
NTUB Surrounding DIFF 1.200
NTUB Spacing DIFF 2.600
FIMP Surrounding DIFF 1.200
FIMP Spacing NPLUS 2.600
NLDD Extension out of DIFF 0.250
PPLUS Spacing NPLUS 0.250

8. From the Verification Toolbar select Enable Interactive DRC icon, this will guide you on if you
are fitting with the design rules or not.
a. If it shows red border lines around the geometry that means it is not allowed.
b. If it shows blue border lines around the geometry that means it is allowed.

Process Design Rules

1. Process design rules are specific to fabrication process technology. These are given in a document
to provide designer guidance on how to draw physical layout which can be fabricated errorless.
2. These design rules are provided on the module website.
http://opencourses.emu.edu.tr/pluginfile.php/31894/mod_resource/content/1/Process%20Desig
n%20Rules.pdf
3. Save this file to your computer, because you will need it when you do your physical layout.

Create a Transistor
1. The most efficient design approach is hierarchical design. This approach has been used in
Schematic design and the same approach will also be used in physical layout design.
2. The first things that need to be designed are the two types of CMOS transistors which their
widths and lengths are based on process technology that have been used in schematic design. In
our designs we will use minimum sized widths and lengths based on process design rules.
3. Two transistor schematic symbols are shown in Figure 10.

Figure 10: S-Edit Transistor Dimensions.

4. To draw the physical layout of these transistors we need to refer to Process Design Rules.
5. To open the design navigator go to View  Design Navigator.

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NMOS Transistor
1. From the layer palette select the diffusion layer (DIFF )
2. From the drawing toolbar select Box object.
3. Draw a W = 0.700, H = 0.300 rectangular DIFF Box as shown in
a. H = 0.300 is given in the design rules page 17, rule OD.W.2.

Figure 11: Diffusion (DIFF) Box.

4. From the layer palette select the polysilicon layer (POLY1 )

5. From the drawing toolbar select Box object.
6. Draw a W = 0.350 (minimum), H = 0.700 rectangular POLY1 Box as shown in
a. W = 0.350 is given in the design rules page 18, rule PO.W.1a.
7. Expand your DIFF and POLY1 Boxes from their borders to fit into design rule geometry (blue and
red borders).

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Figure 12: Poly Silicon (POLY1) on Diffusion (DIFF).

8. Two contacts are needed on both sides so that source and drain terminals can be connected to
other layers.
9. From the layer palette select the contact later (CONT ).
10. From the drawing tool bar select Box object.
11. Refer to the design rules page 21, rule CO.W.1 and draw minimum sized contact where W =
0.400, H = 0.400 as shown in Figure 13.

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Figure 13: Contacts for Drain and Source.

12. Refer to the design rules to place the contacts minimum distance away from the poly silicon and
it can be covered with diffusion as shown in
13. Expand DIFF and POLY layers to fit to design rules geometry.
14. Both NMOS and PMOS transistors have got same width and length of POLY1, DIFF and CONT. To
distinguish NMOS from PMOS, implant layers are needed to be placed on top of the transistor.
15. For NMOS transistor NPLUS layer, For PMOS transistor PPLUS layer is needed as shown in Figure
14.

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Figure 14: NMOS Transistors.

Figure 15: PMOS Transistors.

16. To finish the transistors we also need to add bulk terminals to the layout.
17. For NMOS transistor, PDIFF is needed. For PMOS transistor NDIFF is needed.
18. Select DIFF layer and create a box with dimensions W = 0.7μ and H = 0.7μ.
19. Select CONT layer and create a contact box on top of the DIFF layer with dimensions W = 0.4μ
and H = 0.4μ

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20. For NMOS transistor this should be placed to the bottom of the transistor where GND line will be
passed as shown in Figure 14 and it should be covered with PPLUS layer.
21. For PMOS transistor this should be place on the top of the transistor where VDD line will be passed
as shown in Figure 15 and it should be covered with NPLUS layer.
22. Then for PMOS transistor NTUB layer need to be added on top of the transistor covering both
transistor and the NDIFF box. This will form the bulk connection.

CMOS_INVERTER
1. To create a CMOS Inverter, right click on design navigator and select New.
2. Write the Cell Name as shown in Figure 16 and click OK.
3. New blank page will appear to draw CMOS inverter.

Figure 16: Create a New Cell (CMOS_INVERTER).

4. Drag and drop the PMOS and NMOS inverter which you have already created into the blank page
(CMOS_INVERTER) as shown in Figure 17.

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Figure 17: Drag and Drop NMOS and PMOS Transistors.

5. According to the design rules the space between the NTUB layer of PMOS transistor and NPLUS
layer of NMOS transistor need to be 2.6 μ. Place the transistors 2.6μ away from each other as
shown in Figure 18.

Figure 18: Spacing Between NMOS and PMOS Transistors.

6. We now need to connect both transistors to form an Inverter.

7. Then connect the gates of the transistors using POLY1 layer as shown in Figure 19.

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Figure 19: Connecting Gates.

8. Now, add MET1 layer boxes H = 1.0μ on top of the PMOS and bottom of the NMOS transistors to
create VDD and GND lines as shown in Figure 20. Make sure that the bulk connections contacts are
surrounded with MET1 layer.

Figure 20: Adding VDD and GND.

9. Now, connect one terminal of PMOS transistor to VDD and one terminal NMOS transistor to GND
by using MET1 layer as shown in Figure 21.

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Figure 21: Connecting Terminals to VDD and GND.

10. Connect other terminals of PMOS and NMOS transistors together using MET1 layer as shown in
Figure 22 to form the output connection.

Figure 22: Connecting Output Terminals.

11. Add POLY1CON as shown in to create an input port for the inverter.
a. To create a POLY1CON use POLY1 layer and draw a box with dimensions W = 0.8μ and H =
0.8μ

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b. Add a contact box on top of POLY1, use CONT layer and draw a box with dimension W =
0.4μ and H = 0.4μ.

Figure 23: Adding POLY1CON.

12. Now, we need to label input, output, VDD and GND ports.

a. To label input port select POLY1 layer and click on switch to drawing ports .
b. Place your port to edge of the POLY1 layer as shown in Figure 24.

Figure 24: Input Port.

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c. Dialog box will open

d. Change the Port Name: IN
e. Make the text alignment Middle Center as shown in Figure 25.

Figure 25: Port Alignment.

f. Repeat the steps from a - e, to place ports for output, VDD and GND using MET1 layer.

13. Once the above steps are completed your inverter will look similar to Figure 26.

Figure 26: Inverter with ports labeled.

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14. We are now ready to perform Design Rule Check (DRC).

a. To setup DRC click on the icon

b. This will open a dialog box shown in Figure 27.

Figure 27: DRC Setup.

c. From the “DRC rule sets to run” double click AMSC35_14.3\... line

Figure 28: DRC Rules.

d. Click on . . . button to browse through the verification file.

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e. Go to your AMSC35_14.3 library folder.

Figure 29: AMS Library Folder.

f. Open L-Edit folder  Open Hiper folder.

g. Select the Verification file HiPerVerify_c35b4rules.cal and click OK twice.

Figure 30: Verification File.

15. To run DRC check click on the button perform DRC on active cell.
16. Dialog box will appear which will show the “verification progress”.

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Figure 31: Verification Progress.

17. When it performs the check, Verification Error Navigator dialog box will appear to show the
design errors on your cell as shown in.

Figure 32: Verification Error Navigator.

18. We need to go through each of these errors to correct them.

a. First warning says “CONT without MET1”. If you extend the error down and click on the
error it will point out the place on your cell where you have got an error.

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i. To correct this error we have to add MET1 on top of POLY1CON which we have
created for the input port.
ii. Select MET1 layer and add box on top of POLY1CON.

Figure 33: Metal1 on POLY1CON

b. Once it is corrected re-run the DRC to see if your correction is fine and error will
disappear from the list.

Figure 34: DRC Error List Updated.

c. We have to go through the each errors or warnings.

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d. The warnings which are ticked on the list can be ignored.

e. There two important errors which are MISSING_FIMP and MISSING_NLDD layer.
f. To correct these errors:
i. FIMP layer needed to place on top of the NTUB with the same dimensions with
NTUB layer.
ii. NLDD layer needed to place on top of NMOS transistor with the same dimensions
with NPLUS layer. Make sure that NLDD will also be placed on PMOS transistor
BULK connection.

g. Once these modifications are done. Re-run the DRC to check if these errors are
disappeared as shown.

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h. Now our design is free of errors. There is couple of warning where these can be ignored.
19. Save your design.

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