Rework Challenges for FCBGA & PoP Packages

with Fine Pitches (.4 mm to .7 mm)

and Thin Substrates (≤400 um core)
James Wade, Raiyo Aspandiar, Srini Aravamudhan,
Dudi Amir, and Alan Donaldson
Intel Corporation, Hillsboro, OR
 Introduction
• Trends in mobile (Smart phones; Tablets; &
Ultrabooks) industry has been moving toward:
• Reduction in BGA Pitch
• Enabler: Densification
• Reduced Z-height (thin die, thin substrate)
• Enabler: Low Z-height product
• Reduced PCB Thickness
• Enabler: Low Z-height product
• Increased Package Size
• Enabler: More feature set
• Package Technology (FCBGA and PoP)
• Enabler: Industry demand

Above Industry Trends Increases the

Challenge to the Rework Process
2
Challenges for Achieving
High Rework Yield
• Higher Package Dynamic Warpage
• PCB Dynamic Warpage
• Choosing Flux vs. Solder Paste
• Establishing Optimum Thermal Reflow
Parameters

Challenges to Overcome FCBGA/PoP

Rework to Maintain High Rework Yield

3 3
 Dynamic Warpage Overview
Dynamic warpage of the PCB/FCBGA stack occurs during the reflow
process (as generalized in the images below).

At Room Temperature/Before When Heated To Reflow Temperature

Reflow Soldering
FCBGA Package FCBGA Package FCBGA Package
Positive (+) Warpage Negative (-) Warpage Negative (-) Warpage
CTE ~ 4
ppm/°C Convex Concave Concave

(OR)
CTE ~15
ppm/°C PCB
PCB PCB
PCB Positive (+) Warpage Negative (-) Warpage
Relatively Flat Convex Concave

Worst Case Best Case

Even Though the PCB and Package will Warp when Heated, this Effect
can be Mitigated by Optimizing the Rework Process & Materials

4
4
 Defects Caused by
Excessive Dynamic Warpage
Die

Mother Board

Head on
Non Wet Pillow (HoP)
Open (NWO) Open
Bridging
Head on
Pillow (HoP)
NWO and HoP solder joints defects for FCBGAs are typically seen in the package
corners, while solder bridging is typically seen in the package center.

Schematic depiction of possible solder joint defects that can occur as a result of
increased PCB and/or FCBGA stack warpage, under an un-optimized rework
process.

Various Solder Joint Defects can occur during Rework Reflow Soldering but
they can be Mitigated by Optimizing the Rework Process & Materials

5
5
 Non-wet Open Defect

Possible Causes:
 Interaction between FCBGA dynamic warpage and solder paste
formulation (most probable).
• Paste sticks to ball rather than PCB pad when ball rises up due to
warpage when package is heated.
 Clogged stencil aperture.
 PCB pad contamination (rare).

Potential Solutions:
1. Selection of right solder paste formulation to overcome defect.
2. Over-printing solder paste volume in risk area (FCBGA package
corners).
3. Minimizing board warpage (e.g. use of an reflow pallet).

Non-wets Open Defects are Becoming More Prevalent

but there are Solutions for their Mitigation 6
6
 Head-on-Pillow Defect

Possible Causes:
 Interaction between FCBGA and PCB dynamic warpage (most probable).
• Convex of package substrate and PCB solder ball when molten due to warpage
induced gap.
 Incorrect reflow profile.
 Solder paste formulation.

Potential Solutions:
1. Over-print solder paste volume in risk area (FCBGA package corners).
2. Selection of right solder paste formulation to overcome defect.
3. Minimize Delta Temp within component, and increase Peak Temperature
and Time Above ≥220°C [SAC305 (LF) Type 4] in reflow.
4. Minimizing board warpage (e.g. use of an reflow pallet).

Head-on-Pillow Defects are Also Getting More Prevalent

but there are Materials and Process Solutions to Mitigate these Defects
7
7
 Bridging Defect

Possible Causes:
 Interaction between FCBGA and PCB dynamic warpage (most probable).
• Convex of package substrate and PCB due to warpage reduced gap.
 Incorrect reflow profile.
 Solder paste volume.

Potential Solutions:
1. Under-print solder paste volume in risk area (FCBGA package center).
2. Minimize Delta Temp within component.
3. Minimizing board warpage (e.g. use of an reflow pallet).

Bridging Defects are Getting More Prevalent too

but there are Materials and Process Solutions to Mitigate these Defects

8
8
 Board Dynamic Warpage
• Board warpage can be mitigated during rework unlike
package warpage.
To mitigate PCB warpage:
• Uniform board pre-heating is critical.
– Pre-heat the under side of board between 125 to 150 ⁰C prior to the top heater
applying heat to the package.
– Approximately 10⁰ C or below the Tg (glass transition temperature) of the PCB
material.
– Preheating reduces thermal stress to the PCB.
– Localized heating a the component site can induce board warpage.
• Use a rework pallet with top bracket.
– Holds the PCB flat especially at the component site being reworked.
– Prevents board warpage.
– Minimizing board warpage to be <50 µm (<2 mils) in the FCBGA land area during
reflow is strongly recommended. The use of a pallet is one minimizing approach.

Board Dynamic Warpage Mitigation Solutions

Exist during Rework
9
 Board Dynamic Warpage Results

• Board thickness will effect warpage/sag in an unsupported condition.

• Board without pallet, warpage increases with decreasing board thickness, 32 mil>40 mil>62 mil as
boards sag in an unsupported condition.
• Good pallet support will significant reduce warpage due to sag.
• Pallet supporting the board will reduce warpage even for 32 mil boards. Warpage change of 139% (-87
to +34) at 260C, with tighter distribution.

Use of Pallet Reduces Board Warpage

10 10
 Example of Rework Pallet
Design
Cut outs allow optimum heating the under Top bracket with thumb screws to hold PCB
side of the PCB. component site flat.

Support across center and around edge of Top bracket with thumb screws to hold PCB
pallet to hold PCB flat. component site flat.

Rework Pallet Design can Mitigate Board

Dynamic Warpage during Rework
11 11
Choosing Flux/Tacky Flux vs Solder
Paste for FCBGA Rework
• Flux or Solder paste is applied to the board during rework.
• Which to choose is a critical decision for high yields with
FCBGAs.
• Use Flux/Tacky Flux when
– Stencil printing of solder paste is difficult at very fine pitch lands and/or
lack of real estate around the land pattern.

• Use Solder Paste when

– Flux will NOT fill the gap between package solder sphere and PCB pads.

Solder Paste can be Used to Compensate

for Package & Board Warpage

12 12
Component Replacement: Flux-Only
Application Process on PCB Pads
• Flux should be applied in 2 directions (X and Y), as shown below, sufficient to
cover entire component PCB pad array. Apply flux fully in one direction first
(i.e. X), followed by the other direction (i.e. Y). Either direction can be applied
first.
• Visually inspect to ensure even flux coverage across the entire PCB pad array.
The flux should be clearly visible under the normal lighting conditions.

X Direction

Y Direction

Flux Application Technique to Prevent Opens

13 13
*Other names and brands may be claimed as the property of others.
Component Replacement: Flux-Only Application
Process on Package Solder Spheres

Memory Component

50% ± 10%
of the solder
ball size
Tacky flux (applied from a dip well reservoir)

Tacky Flux
50% ± 10% of
the solder ball
Memory Component size

Dip Well Fixture

Dip Well Flux Application Technique for PoP Memory Component

14
Rework Component Replacement: Solder
Paste Application on PCB Pads
Mini-Stencil Design Considerations:
• Appling solder paste onto the PCB pads will require a solder paste mini-stencil.
• Ensure adequate spacing between mini-stencil and adjacent components. Try to maintain a
3.2 mm (0.125 in) keep out zone, from the edge of mini-stencil to any adjacent
component. If not possible, cut out stencil openings for all adjacent components.
• Always apply high temp tape (i.e. Kapton*), ~ 12.7mm (~ 0.5 inch) wide, on all 4 sides of
the mini-stencil, prior to rework, to prevent movement of the stencil during paste printing.

Stencil design very important.

• When printing solder paste onto the PCB TAPE
pads oblong and square, or even rectangular
stencil apertures may be desirable rather
than circular, to maximize the solder paste

TAPE

TAPE
volume to the PCB pads.
• A minimum of 203.2 µm (8 mils) air gap is
needed between stencil apertures to prevent
solder joint bridging.
• Rotate square apertures by 45 degrees to TAPE
increase stencil air gap.

Apply Tape on Mini-Stencil to Prevent Wet Bridging

15 15
 Reflow Profile Process
What Changes will Mitigate Yield Loss
• Incoming package warpage is part of the problem, but the
profile can help reduce the stress to board and package.
• Thermocouples attached next to the part are NOT accurate
solder temperature indicators.
• Low peak reflow delta t across package allows solder to
solidify simultaneously to help uniform collapse.
• Max delta-t of solder joint temperature for FCBGA at peak reflow ≤10°C.

• Prevent depletion of flux activity by following suppliers’

recommendation for temperature soak time.

Well Fabricated Profile Board and Accurate

Reflow Profile is a Plus to Prevent Yield Loss

16 16
FCBGA Rework
PCB Prep for Rework Profile Development: Thermo Couple
Installation (1 of 2)
The Intel reference rework processes specifies to mount Thermo Couple (TC) wire tips into
the PCB pads of the FCBGA (just above PCB surface) to measure time & temperature of
the solder joints.
• Temperatures are measured at the joints for the best repeatability and accuracy,
compared to placing TC’s next to joints, or on the surface of the PCB, or in the air.
• TC’s should be installed in PCB pad/joint using the technique described below:
– Before the component is soldered to the mother board.
– Make a divot on the PCB pad and drill a 342.9 µm (13.5 mils)
hole through the PCB pad.
– Place Kapton* tape over the PCB pad with hole, it will hold the
TC tip flush with the PCB pad top surface.
– Insert the TC tip from the bottom of the board and insure TC For FCBGAs
tip is flush with the top surface of the PCB pad on the board.
– Place Kapton* tape over wire ~ 6.35 mm ( ~ 0.25 in) from Component Body
hole. It will hold the TC tip flush with the PCB pad top surface
while the epoxy is curing in the bake oven.
– Apply epoxy from the bottom side of the board to keep the TC
tip in position, where it will be in contact with the PCB pad
joint.
– Cure board with epoxy in a bake oven. Thermal Couple
– Remove board from the bake oven once epoxy has cured, OB-200* Epoxy Location
remove Kapton* tape covering PCB pad with hole, and the
board is ready to solder down the component.

Intel Method for Thermal Couple Attachment to

Accurately Measure Solder Joint Temperature
17 17
*Other names and brands may be claimed as the property of others.
FCBGA Rework
PCB Prep for Rework Profile Development: Thermo Couple
Installation (2 of 2)

The Intel reference rework processes specifies to mount TC wire tips onto the
FCBGA die and substrate surface to measure peak time & temperature.
• Temperatures are measured on the surface for the best repeatability and
accuracy.
• Below is a FCBGA component illustration showing how to attach TC tips to
the die and substrate surface to monitor the die and substrate reflow
temperatures.
• Attach thermal couple at each corner and center of pad array to monitor
temperature delta t across package.

Thermal Couple Location OB-200*

Epoxy

FCBGA Component

PCB

Intel Method for Thermal Couple Attachment to

Accurately Measure Peak Substrate Temperature
18 18
*Other names and brands may be claimed as the property of others.
Intel Method to Place Flattened TC wire Tip onto Pads for
PoP Profile Board

Step Step Step

1 2 3
Place TC Tip into Squeeze Pliers Remove TC Tip
Pliers to Flatten TC Tip from Pliers

Place TC tips into drill holes at secondary side to PCB to be flush with PCB
pad on Primary side of PCB. Secure TC with OB-200 epoxy on secondary side
of PCB surface.

Die
Bottom Package

Flux PCB pads and place and reflow bottom package to PCB component pads.
Place flattened TC Tips onto interposer pads. Secure TC wire and bottom
package with OB-200 epoxy on primary side of PCB surface.

Top Memory Package

Die
Bottom Package

Dip memory package joints into tacky flux dip well , place memory package
onto interposer pads ,and reflow memory package onto interposer pads.
Place TC Tip on top center surface of memory package. Secure TC tip/wire to
memory package surface and memory package to interposer with OB-200
epoxy. Secure stack to PCB with OBB-200 epoxy on both sides.
19
*Other names and brands may be claimed as the property of others.
 Intel Method to Place Flattened TC wire Tip onto PCB
Pads & Interposer Pads

Step Step Step

1 2 3
Place TC Tip into Squeeze Pliers Remove TC Tip
Pliers to Flatten TC Tip from Pliers

Place flattened TC tips on to the PCB pad on Primary side of PCB. Secure TC
with OB-200 epoxy on PCB surface.

Die
Bottom Package

Flux PCB pads and place and reflow bottom package to PCB component pads.
Place flattened TC Tips onto interposer pads. Secure TC wire and bottom
package with OB-200 epoxy on primary side of PCB surface.

Top Memory Package

Die
Bottom Package

Dip memory package joints into tacky flux dip well , place memory package
onto interposer pads ,and reflow memory package onto interposer pads.
Place TC Tip on top center surface of memory package. Secure TC tip/wire to
memory package surface and memory package to interposer with OB-200
epoxy. Secure stack to PCB with OBB-200 epoxy on both sides.
20 20
*Other names and brands may be claimed as the property of others.
 Intel Method to Place Non Flattened TC wire Tip to
Memory Package Solder Joints

TC Tips are placed into drill holes at secondary side to PCB to be flush with
PCB pad on primary side of PCB pads. Secure TC with OB-200 epoxy on
secondary side of PCB surface.

Top Memory Package

Die
Bottom Package

Flux PCB pads and place bottom package to PCB component pads. Dip
memory package into tacky flux dip well and place onto interposer pads, and
reflow bottom and memory packages.

Top Memory Package

Die
Bottom Package

Place TC Tip onto memory solder joints. Secure TC wire with OB-200 epoxy
onto primary side PCB surface.

Top Memory Package

Die
Bottom Package

Place TC Tip on top center surface of memory package. Secure TC tip/wire to

memory package surface and memory package to interposer with OB-200
epoxy. Secure stack to PCB with OBB-200 epoxy on both sides.
21 21
*Other names and brands may be claimed as the property of others.
Package Rework
Intel® Lead-Free Rework Thermo Profile Graphic (for FCBGA & PoP
packages)

250ºC
245ºC
Max Peak Temp Range 230 – 250ºC Falling Ramp Rate
-0.5 to – 2.0°C/sec

230ºC
Critical Rising Ramp Rate
205-215ºC: 0.35 - 0.75ºC/sec
217ºC

205ºC Time Above ≥ 217°C:

60 – 120 sec
Rising Ramp Rate Body Peak Temperature ≤260°C
below 150ºC: Die Peak Temperature ≤300°C
0.5 – 2.5ºC/sec
Max delta-t Solder Joint Temperature
Peak Reflow ≤10°C

150ºC
Soak Time – 150°C to 217°C
(Paste dependant; consult paste manufacturer)

Board Pre-Heat: Room Temperature – 125

to 150 °C

Critical to Function Parameters to Measure Rework Reflow

Notes:
• Except for body temp, all temperatures are measured with thermo couples 22
22
inside solder joints, for better accuracy.
 General Recommendations for
BGA Rework
Beside those already mentioned and not necessary applying
only to low pitches and large body sizes.
• PCB Pad Site Dress process recommendations:
– Always clip off the used portion of the wick; it behaves as a heat sink.
– Apply liquid flux to the wick to minimize sticking of the wick to the pads.
– Place the soldering iron on the solder wick off to the edge of the pads
being soldered, to heat iron tip and wick prior to de-soldering.
– Do not let the solder iron or wick stop on pads, to prevent pad lift.
– Do not lift the wick up and down on the pads.
– Apply very light pressure, similar to writing with a pencil. Soldering is
achieved by temperature difference, not by tip pressure.
– Apply heat for 2 to 3 seconds after solder melts. Total contact time may
be 6-7 seconds. Excess heating causes solder brittleness and may lift
pads.

Proper PCB Pad Site Dress Technique to Prevent

PCB Pad Lift and Createring

23 23
 Summary
• Rework Yield is affected by
– Package/die size shape
– Room package coplanarity
– Package/PCB dynamic warpage during the solder reflow
process
• Yield loss can be mitagated by
– Material choice
• Flux or Solder paste
• Stencil design
• Reflow pallet
– Process methods and settings
• Thermal couple attachment method
• Thermal Reflow profile Critical to Function Parameters

Solid Understanding of Material and Process will Insure a

High Yield at Rework
24 24
 Conclusions
• Mitigation factors to reduce warpage impact or solder paste
flux activity degradation.
– FCBGA package solder paste volume optimization (Over-print at package
corners) is most effective ways to mitigate solder joint formation defects.
– Rework pallet with top bracket.
• Holds the PCB flat.
• Prevents board warpage.
– Stencil design very important.
• When printing solder paste onto the PCB pads, oblong, square, or even rectangular stencil
apertures may be desirable rather than circular, to maximize the solder paste volume to the PCB
pads.
• A minimum of 203.2 µm (8 mils) air gap is needed between stencil apertures to prevent solder
joint bridging.
• Rotate square apertures by 45 degrees to increase stencil air gap.
– Flux alone can be used on FCBA and PoP packages when
• Stencil printing of solder paste is difficult at very fine pitch lands and/or lack of real estate
around the land pattern.
– Low peak reflow delta t across package allows solder to solidify
simultaneously to help uniform collapse.

A Trend to Thin Core & Die Packages is Driving Increased

Importance of Process Capability to Ensure High Yields
25 25
 Further Work Needed
• Mitigation factors for next steps
– Development rework process for increased
package warpage with reduced pitch.
– Development of new solder paste formulations
which can close or bridge the gap.

More Material and Process Studies Needed to Validate

How to Continue to Ensure High Yield with Packages with
Increased Dynamic Warpage at Reflow Temperatures

26 26