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3.input Files For PD

The document describes the key input files required for physical design of an integrated circuit. These include: 1. A Verilog netlist file containing the logical connectivity and names of standard cells and macros. 2. A constraints file with timing constraints to meet timing requirements. 3. Logical library files containing timing, functionality, and power information for standard cells and macros. 4. Physical library files containing layout and pin information for cells and macros. 5. A technology file describing manufacturing rules and layer properties. 6. TLU+ files containing resistance and capacitance parasitics used to calculate net delays.

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Deepak Kumar S Nadiger
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
695 views

3.input Files For PD

The document describes the key input files required for physical design of an integrated circuit. These include: 1. A Verilog netlist file containing the logical connectivity and names of standard cells and macros. 2. A constraints file with timing constraints to meet timing requirements. 3. Logical library files containing timing, functionality, and power information for standard cells and macros. 4. Physical library files containing layout and pin information for cells and macros. 5. A technology file describing manufacturing rules and layer properties. 6. TLU+ files containing resistance and capacitance parasitics used to calculate net delays.

Uploaded by

Deepak Kumar S Nadiger
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Physical Design – Input Files VLSI GURU

INPUT FILES FOR PD


Following input files are required to start PD:
SI no File Name Extension Lender
1 Verilog Netlist .v Synthesis team
2 Constraints .sdc Synthesis team
3 Logical libraries (Std cells .lib (.db) Vendor
And macros )

4 Physical libraries .lef (.Fram_views) Vendor


(Std cell and macros )

5 Technology File .tf Foundry


6 TLU + file . TLUP Foundary

NETLIST
Netlist: Format is .V
1. It contains Logical connectivity Of all Cells (Std cells, Macros).
2. It contains List of nets Connecting std cells and Macros
3. Each cell has its own instance/cell name and library/ref name

SDC
SDC :Format is .SDC :
These Constraints are timing Constraints .
These Constraints are mainly used to meet timing requirements of design .
Constraints are

1. CLOCK DEFINITIONS: To create different types of clocks


2. Clock uncertainty.
3. Setting Input Delay
4. Setting Output Delay
5. Driving Cell
6. Setting load on output ports
--------------->Exceptions<------------------------
7. Multi cycle path
8. False path
9. Half cycle path
10. Disable timing arcs
11. Case Analysis
Physical Design – Input Files VLSI GURU

LOGICAL LIBRARIES
Logical libraries: format is .lib
1. Timing information of Standard cells, macros.
2. Functionality information of Standard cells.
3. Timing DRV like max transition, max capacitance, max fan-out.
4. In timing information look-up table is used for output transition, Cell delays, Setup, hold
time.
5. Cell delay is Function of input transition and output load. Cell delay is calculated based on
lookup tables.
6. It also has wire load model to calculate resistance and capacitance of wires
7. Functionality is used for Optimization Purpose.
8. It also Contain Power information of Std cells.

Look-Up Table

Above is the table for calculating rise cell delay, Index-1 is input transition values and
index-2 is output load capacitance values.
Physical Design – Input Files VLSI GURU

Wire load models:

PHYSICAL LIBRARIES
Physical libraries: format is .lef (. Fram views for synopsis)
1. It contains physical information of standard cells, macros, pads.
2. Contain the name of the pin, pin location (Co-ordinates) , pin layers, direction of pin (in,
out, inout), uses of pin (Signal, Power, Ground) , height and width of the pin and cell.
3. Size of the cell (Height and width)
4. Symmetry of cell.
Physical Design – Input Files VLSI GURU

TECHNOLOGY FILE:

1. It contains manufacturing grid definition and site/unit tile definition


2. It contains Name, Number conventions of layer and via
3. It contains Physical, electrical characteristics of layer and via
4. In Physical characteristics Min width,Min Spacing,Min Height are present.
5. In Electrical characteristics Max Current Density is present.
6. Colors and pattern of layer and via .
7. Physical Design rules of layer and via
8. Tech file used by the Cadence tool is .techlef format and .tf format by Synopsys tool.

TLU PLUS
TLU+ files: format is .TLUP:
1. R,C parasitics of metal per unit length.
2. These (R,C parasitics) are used for calculating Net Delays.
3. If TLU+ files are not given then these are getting from. ITF file.
4. For Loading TLU+ files we have load two files .
5. Those are Max TLU+, Min TLU+
Physical Design – Input Files VLSI GURU

MAP file.
1. MAP file maps the layer and via names of TLU+ file and .tf file .
UPF- File (Unified Power Format )
1. UPF is designed to reflect the power intent of a design at a relatively high level.
2. UPF scripts describe which power rails should be routed to individual blocks, when blocks are
expected to be powered up or shut down.
3. It describes how voltage levels should be shifted as signals cross from one power domain to
another and whether measures should be taken to retain register and memory-cell contents if the
primary power supply to a domain is removed.

Note : To Store Library and design Information ICC2 uses NDM format .
NDM has all input files in compiled format.

Assignment
1. Open Netlist (.v) and Understand Hierarchical design
2. Open .lib and for cell AND2X4_HVT note following information
a) Leakage power
b) Internal Power table
c) Dynamic power table
d) Rise/fall output transition table
e) Rise/fall cell delay table
f) On output pin Note max_capacitance and max_transition
3. Open. lef file for AND2X4_HVT cell and note
a) Its dimension
b) Allowed Orientation
c) Its pins and Pin layers
4. Open .tf and Note
a) Site row information
b) Manufacturing grid
c) For all routing metal layers note
i) Min spacing
ii) Min width
iii) Pitch
iv) Routing direction

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