Chapter 4 — The Processor October 9, 2022

Computer Architecture
Chapter 4: The Processor

Adapted from Computer Organization the Hardware/Software Interface – 5th

Computer Engineering – CSE – HCMUT

Introduction
•  CPU performance factors
–  Instruction count
•  Determined by ISA and compiler
–  CPI and Cycle time
•  Determined by CPU hardware
•  We will examine two MIPS implementations
–  A simplified version
–  A more realistic pipelined version
•  Simple instruction subset, shows most aspects
–  Memory reference: lw, sw
–  Arithmetic/logical: add, sub, and, or, slt
–  Control transfer: beq, j
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Instruction Execution
•  PC → instruction memory, fetch instruction
•  Register numbers → register file, read registers
•  Depending on instruction class
–  Use ALU to calculate
•  Arithmetic result
•  Memory address for load/store
•  Branch condition (comparison)
–  Access data memory for load/store
–  PC ← target address or PC + 4

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CPU Overview

(số hiệu
thanh ghi)

bộ nhớ lệnh

ALU có thể cộng trừ, nhân chia

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input and output relationship

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Execution Model
•  Instruction fetch: PC → instruction address
•  Instruction decode: register operands → register
file
•  Instruction execute:
–  Load/store: compute a memory address
–  Arithmetic: compute an arithmetic result
•  Write back:
–  Load/store: store a value to a register or a memory
location
–  Arithmetic: store a result of register file
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Multiplexers
n  Can’t just join
wires together
n  Use multiplexers
hai đường tín hiệu
đấu với nhau một
cách rất quái
=> việc xác định
trạng thái kết hợp là
bất khả thi

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Multiplexer

𝐶=𝐴​𝑆 +𝐵𝑆

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Control vs. Data signals

•  Control signal: used for •  Data signal: contains
multiplexer selection or information that is
for directing the operated on by a
operation of a functional unit
functional unit

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Control

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Logic Design Basics

•  Information encoded in binary
–  Low voltage = 0, High voltage = 1
–  One wire per bit
–  Multi-bit data encoded on multi-wire buses
•  Combinational element
–  Operate on data
–  Output is a function of input
•  State (sequential) elements
–  Store information
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Combinational Elements
•  AND-gate •  Adder
–  Y = A & B –  Y = A + B
A A
Y + Y
B
B

•  Multiplexer •  Arithmetic/Logic Unit

–  Y = S ? I1 : I0 –  Y = F(A,B)
A
I0 M
u Y ALU Y
I1 x
B
S F
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Sequential Elements
•  Register: stores data in a circuit
–  Uses a clock signal to determine when to update
the stored value
–  Edge-triggered: update when Clk changes from 0
to 1
Clk
D Q
D

Clk
Q

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Sequential Elements
•  Register with write control
–  Only updates on clock edge when write control
input is 1
–  Used when stored value is required later
Clk

D Q Write

Write D
Clk
Q

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Clocking Methodology
•  Combinational logic transforms data during
clock cycles
–  Between clock edges
–  Input from state elements (a memory or a
register), output to state element
–  Longest delay determines clock period

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Building a Datapath
•  Datapath
–  Elements that process data and addresses
in the CPU
•  Registers, ALUs, mux’s, memories, …
•  We will build a MIPS datapath incrementally
–  Refining the overview design

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Instruction Fetch

Increment by
4 for next
32-bit instruction
register

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R-Format Instructions
•  Ex. add, sub, and, or, slt
•  Read two register operands
•  Perform arithmetic/logical operation
•  Write register result

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Load/Store Instructions
•  Read register operands
•  Calculate address using 16-bit offset
–  Use ALU, but sign-extend offset
•  Load: Read memory and update register
•  Store: Write register value to memory

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Branch Instructions
•  Branch taken: condition is satisfied and the
Program Counter (PC) register becomes the
branch target
•  Branch not taken: PC becomes the address of
the next instruction
•  Datapath:
–  Compute the branch target
–  Compare the registers

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Branch Instructions
•  Read register operands
•  Compare operands
–  Use ALU, subtract and check Zero output
•  Calculate target address
–  Sign-extend displacement
–  Shift left 2 places (word displacement)
–  Add to PC + 4
•  Already calculated by instruction fetch

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Branch Instructions
Just
re-routes
wires

Sign-bit wire
replicated
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Composing the Elements

một lệnh một chu kỳ
•  First-cut datapath does an instruction in one
clock cycle
–  Each datapath element can only do one function at a
time
–  Hence, we need separate instruction and data
memories
•  Use multiplexers where alternate data sources
are used for different instructions
–  ALU input: register value/immediate
–  Register file write data: results from the ALU/Memory

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R-Type/Load/Store Datapath
thiếu lệnh BRANCH

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Full Datapath

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ALU Control
•  ALU used for
–  Load/Store: F = add
–  Branch: F = subtract
–  R-type: F depends on funct field
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than
1100 NOR
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ALU Control
•  Assume 2-bit ALUOp derived from opcode
–  Combinational logic derives ALU control
opcode ALUOp Operation funct ALU function ALU control
lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111

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Multiple Levels of Decoding

•  Instruction opcode + function => ALUOp =>
ALU control lines
–  Smaller main controller
–  Faster main controller (potentially)

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The Main Control Unit

•  Control signals derived from instruction
R-type 0 rs rt rd shamt funct
31:26 25:21 20:16 15:11 10:6 5:0

Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for sign-extend

read except R-type and add
for load and load
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Datapath with Instruction Fields

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Datapath With Control

30

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R-Type Instruction

add $t1, $t2, $t3

31

Load Instruction

lw $t1, offset($t2)

32

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Branch-on-Equal Instruction

beq $t1, $t2, offset

33

Implementing Jumps
•  Jump uses word address
•  Update PC with concatenation of
–  Top 4 bits of old PC
–  26-bit jump address
–  00
•  Need an extra control signal decoded from
opcode
Jump 2 address
31:26 25:0
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Datapath With Jumps Added

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Performance Issues
•  Longest delay determines clock period
–  Critical path: load instruction
–  Instruction memory → register file → ALU → data
memory → register file
•  Not feasible to vary period for different
instructions
•  Violates design principle
–  Making the common case fast
•  We will improve performance by pipelining
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Pipelining Analogy
•  Pipelined laundry: overlapping execution
–  Parallelism improves performance
n  Four loads:
n  Speedup
= 8/3.5 = 2.3
n  Non-stop:
n  Speedup
= 2n/0.5n + 1.5 ≈ 4
= number of stages

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MIPS Pipeline
•  Five stages, one step per stage
1.  IF: Instruction fetch from memory
2.  ID: Instruction decode & register read
3.  EX: Execute operation or calculate address
4.  MEM: Access memory operand
5.  WB: Write result back to register

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Pipeline Performance
•  Assume time for stages is
–  100ps for register read or write
–  200ps for other stages
•  Compare pipelined datapath with single-cycle
datapath
Instr Instr fetch Register ALU op Memory Register Total time
read access write
lw 200ps 100 ps 200ps 200ps 100 ps 800ps
sw 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps

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Pipeline Performance
Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

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Pipeline Speedup
•  If all stages are balanced
–  i.e., all take the same time

•  If not balanced, speedup is less

•  Speedup due to increased throughput
–  Latency (time for each instruction) does not
decrease
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Pipelining and ISA Design

•  MIPS ISA designed for pipelining
–  All instructions are 32-bits
•  Easier to fetch and decode in one cycle
•  c.f. x86: 1- to 17-byte instructions
–  Few and regular instruction formats
•  Can decode and read registers in one step
–  Load/store addressing
•  Can calculate address in 3rd stage, access memory in 4th
stage
–  Alignment of memory operands
•  Memory access takes only one cycle

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Multi-Cycle Pipeline Diagram

•  Form showing resource usage

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Multi-Cycle Pipeline Diagram

•  Traditional form

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Hazards
•  Situations that prevent starting the next
instruction in the next cycle
•  Structure hazards
–  A required resource is busy
•  Data hazard
–  Need to wait for previous instruction to complete
its data read/write
•  Control hazard
–  Deciding on control action depends on previous
instruction
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Structure Hazards
•  Conflict for use of a resource
•  In MIPS pipeline with a single memory
–  Load/store requires data access
–  Instruction fetch would have to stall for that cycle
•  Would cause a pipeline “bubble”
•  Hence, pipelined datapaths require separate
instruction/data memories
–  Or separate instruction/data caches

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Data Hazards
•  An instruction depends on completion of data
access by a previous instruction
–  add $s0, $t0, $t1
sub $t2, $s0, $t3

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Forwarding (aka Bypassing)

•  Use result when it is computed
–  Don’t wait for it to be stored in a register
–  Requires extra connections in the datapath

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Load-Use Data Hazard

•  Can’t always avoid stalls by forwarding
–  If value not computed when needed
–  Can’t forward backward in time!

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Code Scheduling to Avoid Stalls

•  Reorder code to avoid use of load result in the
next instruction
•  C code for A = B + E; C = B + F;
lw $t1, 0($t0) lw $t1, 0($t0)
lw $t2, 4($t0) lw $t2, 4($t0)
stall add $t3, $t1, $t2 lw $t4, 8($t0)
sw $t3, 12($t0) add $t3, $t1, $t2
lw $t4, 8($t0) sw $t3, 12($t0)
stall add $t5, $t1, $t4 add $t5, $t1, $t4
sw $t5, 16($t0) sw $t5, 16($t0)
13 cycles 11 cycles
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Control Hazards
•  Branch determines flow of control
–  Fetching next instruction depends on branch
outcome
–  Pipeline can’t always fetch correct instruction
•  Still working on ID stage of branch
•  In MIPS pipeline
–  Need to compare registers and compute target
early in the pipeline
–  Add hardware to do it in ID stage

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Stall on Branch
•  Wait until branch outcome determined before
fetching next instruction

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Branch Prediction
•  Longer pipelines can’t readily determine
branch outcome early
–  Stall penalty becomes unacceptable
•  Predict outcome of branch
–  Only stall if prediction is wrong
•  In MIPS pipeline
–  Can predict branches not taken
–  Fetch instruction after branch, with no delay

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MIPS with Predict Not Taken

Prediction
correct

Prediction
incorrect

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More-Realistic Branch Prediction

•  Static branch prediction
–  Based on typical branch behavior
–  Example: loop and if-statement branches
•  Predict backward branches taken
•  Predict forward branches not taken
•  Dynamic branch prediction
–  Hardware measures actual branch behavior
•  e.g., record recent history of each branch
–  Assume future behavior will continue the trend
•  When wrong, stall while re-fetching, and update history

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Dynamic Branch Prediction

•  In deeper and superscalar pipelines, branch penalty
is more significant
•  Use dynamic prediction
–  Branch prediction buffer (aka branch history table)
–  Indexed by recent branch instruction addresses
–  Stores outcome (taken/not taken)
–  To execute a branch
•  Check table, expect the same outcome
•  Start fetching from fall-through or target
•  If wrong, flush pipeline and flip prediction

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1-Bit Predictor: Shortcoming

•  Inner loop branches mispredicted twice!
outer: …
…
inner: …
…
beq …, …, inner
…
beq …, …, outer

n  Mispredict as taken on last iteration of

inner loop
n  Then mispredict as not taken on first

iteration of outer loop next time around

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2-Bit Predictor
•  Only change prediction on two successive
mispredictions

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Calculating the Branch Target

•  Even with predictor, still need to calculate the
target address
–  1-cycle penalty for a taken branch
•  Branch target buffer
–  Cache of target addresses
–  Indexed by PC when instruction fetched
•  If hit and instruction is branch predicted taken, can
fetch target immediately

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Pipeline Summary
The BIG Picture
•  Pipelining improves performance by
increasing instruction throughput
–  Executes multiple instructions in parallel
–  Each instruction has the same latency
•  Subject to hazards
–  Structure, data, control
•  Instruction set design affects complexity of
pipeline implementation
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