Vol 53 No 4, October 2019

Part 1: Optimized
Sigma-Delta Modulated
Current Measurement
for Motor Control
Jens Sorensen, Dara O’Sullivan, and Shane O’Meara

Isolated sigma-delta (∑-Δ)-based analog-to-digital converters (ADCs) have timing accuracy, offset/gain errors, and synchronization of multiple feedback
become the preferred method for phase current measurement in high per- channels. Over the years, semiconductor companies have focused on reducing
formance motor and servo drives. The converters have deservedly earned a these nonideal effects in the feedback signal chain, and that trend is likely
reputation for robust galvanic isolation and excellent measurement perfor- to continue. The ADuM7701 is one example of the latest generation of
mance. With every new generation of ADCs, the performance is increased isolated sigma-delta ADCs optimized for phase current measurement. While
even further, but to fully utilize the potential of the latest ADCs, the rest of the performance of the ADC is important, there is a high risk of introducing
the motor drive needs to be designed accordingly. nonideal effects in the rest of the feedback path as well. This article goes
beyond the ADC and primarily discusses the remaining part of feedback
This article is Part 1 in a series of two. Part 1 discusses demodulation of
path. While the main focus is on motor control applications, this article applies
sigma-delta coded data using sinc filters in a motor control application.
to any system that requires tight synchronization of sigma-delta ADCs.
It then takes a close look at different approaches for sinc filter and control
algorithm synchronization. Part 2 of the series proposes a new sinc filter The typical signal chain, when using a sigma-delta ADC, is shown in
structure that improves measurement performance in motor control applica- Figure 1. An analog input voltage is created by letting the phase current
tions. This is followed by a discussion on implementation of sinc filters with pass through a resistive shunt. The sigma-delta ADC converts the analog
HDL code for optimum performance, and, finally, measurement results from signal into a 1-bit data stream and provides galvanic isolation so every-
an FPGA-based 3-phase servo drive are presented. thing that follows the ADC is isolated from the motor phase potential.
Following the converter is demodulation in the form of a filter. The filter
Introduction converts the 1-bit signal into a multibit signal (M-bit) and brings the data
Motor drive manufacturers continue to improve the performance and update rate down through the process of decimation. While the decima-
robustness of their products. Some of the improvements have been realized tion in the filter lowers the data rate, it is typically still too high to match
through more advanced control algorithms and higher computational power. the update rate of the control algorithm. To solve this problem, a final
Other improvements have been accomplished by minimizing nonideal effects downsampling stage is added.
in the feedback circuits such as latency, skewing, and temperature drift.1 Throughout this article it is assumed the filter and decimation stages are
When it comes to feedback for the motor control algorithm, the most critical implemented in an FPGA and that the filter is a third-order sinc filter (sinc3).
part is phase current measurement. As control performance increases,
the system becomes more and more sensitive to nonideal effects such as

Phase Current

Shunt ∑-∆ Converter Filter Downsampling

Analog 1-Bit M-Bit To MC
Input Voltage Digital Digital Algorithm

Figure 1. A sigma-delta signal chain for phase current measurement.

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 0.15

Sinc3
Impulse Sinc3
0.10 Response Step Response
Step
Amplitude

0.05
Time
Decimation Cycle

Group Delay = 1.5 Dec. Cycles

Settling Time = 3 Dec. Cycles

0
0 1 2 3 4 5 6 7 8 9 10 11 12

Sample Number

(a) (b)

Figure 2. (a) Sinc filter impulse response for a filter with a decimation rate of 5. (b) Sinc filter step response and relation to impulse response.

Sinc Filter Synchronization Figure 3 shows a simulated phase current of a 3-phase permanent magnet
Sigma-delta ADCs and sinc filters are criticized for being difficult to control motor driven by a voltage source inverter. The modulation scheme is space
in the time domain and for their lack of a defined sampling instant.2 When vector PWM3 and the switching frequency is 10 kHz. The motor is loaded
compared to a conventional ADC with a dedicated sample-and-hold circuit, to 5 A peak phase current and the rotational speed is 3000 rpm. This setup,
there is some reason for concern. However, there are ways to work around along with 3 pole pairs, results in an electrical fundamental period of 6.67 ms.
this. As will be shown in this section, it is crucial to synchronize the sinc 6
Switching Phase Current
filter to the rest of the system and to sample the phase current at the right
instant. If this is not done correctly, the resulting measurement will suffer 4

from significant distortion.

Phase Current (A) 2
The output from a sinc filter is not a representation of what the input to the
sigma-delta ADC is at that instant. Rather, the output is a weighted average 0
of what the input was during a windowed period in the past. This behavior
is due to the filter’s impulse response. Figure 2a shows the impulse response –2
of a sinc3 with a decimation rate of 5. The figure shows how the filter output
is a weighted sum of the input sequence that gives more weight to samples –4
at the center and less weight to samples at the beginning/end.
Before proceeding, a few basic definitions are needed. The sigma-delta –6
0 1 2 3 4 5 6
ADC clock, also called the modulator clock, is referred to as fmod. The deci- Time (ms)
mation rate (DR) determines the decimation frequency (fdec) and is linked to
Figure 3. Motor phase current with space vector pulse-width modulation.
fmod, as shown in Equation 1:
fmod The phase current can be seen as two components: an average and a
DR = (1)
fdec switching component. For control purposes, only the average component of
The right side of Figure 2 shows the effect the impulse response has on the the current is of interest, so the switching component must be fully removed.
filter’s step response. As the step is applied, the filter output is unaffected, The most common way to extract the average component is to sample the
and it takes 3 full decimation cycles before the filter reaches steady state. signal synchronized to the PWM waveform applied to the motor terminals.
Based on this, some important properties of a sinc3 filter can be stated: This is illustrated in Figure 4. The top signal shows the switching waveform
of a phase current, the middle signal shows a high-side PWM signal for the
XX The group delay is 1.5 decimation cycles long corresponding inverter phase leg, and the lower signal shows the synchroniz-
XX The settling time is 3 decimation cycles long ing signal from the PWM timer. The PWM synchronization signal is asserted
at the beginning and the center of a PWM cycle. For simplicity, it is assumed
These properties are important when it comes to synchronizing the filter to that all three phases run with a duty cycle of 50%, which means there is only
the control system and they will be utilized throughout the article. one rising slope and one falling slope of the current. At the rising edge of the
Before discussing sinc filter synchronization, the characteristics of the input PWM synchronization signal, the current assumes its average value, so if the
signal must be defined. This in turn will define what the filter must be currents are sampled at exactly that moment, the switching component will
synchronized to. be fully suppressed. Effectively, the sample-and-hold circuit is equivalent to
a filter with infinite attenuation at the switching frequency.

2 // Analog Dialogue 53-10, October 2019

 Average Current Sigma-Delta Measurement and Aliasing
With the ideal sample-and-hold ADC, it is possible to extract the fundamen-
Phase
Current tal component because of tight control of the sampling instant. However,
sigma-delta conversion is a continuous sampling process and the ripple
component will inevitably be part of the measurement.
PWM With sigma-delta conversion there is a close link between the decimation
PWM rate and signal-to-noise ratio (SNR). The higher the decimation rate, the
Syncronization more effective number of bits (ENOB) of the output. The downside is, as the
TSW/2 Time
decimation rate increases, the group delay also increases so the designer
must compromise between signal resolution and delay in the feedback
TSW
chain. As a general rule, the delay must be kept small compared to the
control cycle period. For motor control, typical decimation rates fall in the
Figure 4. Measuring phase current at the beginning and center points of a PWM
period attenuates the current ripple. range of 128 to 256, which provides a good compromise between SNR and
group delay.
Figure 5 shows the result of what happens when this kind of sampling is
applied to the waveform appearing in Figure 3. The right side shows a For data sheet specifications, a decimation rate of 256 is commonly used.
close-up of the actual phase current and the sampled current. Note how the For example, ADuM7701 has an ENOB of 14 bits, at a decimation rate of
sample-and-hold process completely removes the ripple. 256. With such a high ENOB number, a very clean measurement is to be
expected. To verify this, suppose the phase current shown in Figure 3 is
A per-unit representation of the sampled current is used where 0 A is measured with a sigma-delta ADC clocked at 20 MHz and that the data
mapped to 0.5 and the full scale is 8 A. This scaling is chosen for easier stream is demodulated by a sinc3 using a decimation rate of 256. The result
comparison to the sigma-delta measurements that follow. The result shown is shown in Figure 6a.
in Figure 5 is the ideal scenario, with only the fundamental component left
after sampling. As such, these data can be considered the benchmark to
which the sigma-delta measurements will be compared.

1 0.75
Ideal Sampled Current Ideal Sampled Current
0.9 Phase Current

0.8 0.7

0.7
Phase Current (–)

Phase Current (–)

0.6 0.65

0.5

0.4 0.6

0.3

0.2 0.55

0.1

0 0.5
0 1 2 3 4 5 6 0.1 0.2 0.3 0.4 0.5 0.6
Time (ms) Time (ms)
(a) (b)

Figure 5. Ideal sampling of phase current: (a) a fundamental period of ideally sampled phase current, (b) a close-up look at phase current and sampled phase current.

1 0.85
Sinc Output Sinc Output
0.9 Phase Current
Sampled Sinc Output
0.8
0.80
0.7
Phase Current (–)

Phase Current (–)

0.6

0.5 0.75

0.4

0.3
0.70
0.2

0.1

0 0.65
0 1 2 3 4 5 6 2.2 2.3 2.4 2.5 2.6 2.7
Time (ms) Time (ms)
(a) (b)

Figure 6. (a) The output from the sinc filter. (b) A close-up look at the actual phase current and decimated output from the sinc filter.

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 1 0.05
Sampled Sinc Output Measurement Error
0.9 0.04

0.8 0.03

0.7 0.02
Phase Current (–)

0.6 0.01

Error (–)
0.5 0

0.4 –0.01

0.3 –0.02

0.2 –0.03

0.1 –0.04

0 –0.05
0 1 2 3 4 5 6 0 1 2 3 4 5 6
Time (ms) Time (ms)
(a) (b)

Figure 7. (a) Sampled output from the sinc filter. (b) Measurement error.

The fundamental component of the phase current is obvious, but the mea- To avoid aliasing, the signal must be free of energy above half the sampling
sured signal is very noisy when compared to the ideal sampling shown in frequency, as per standard sampling theory. If the sigma-delta ADC output
Figure 5a. So while the ADC and sinc filter by themselves provide impres- is downsampled to 10 kHz, any noise at 5 kHz or higher would fold into the
sive ENOB numbers, the quality of the feedback signal is quite poor. The measurement. As shown, there was plenty of 10 kHz switching noise left in
reason for this can be seen in Figure 6b, which shows a close-up of the sinc the signal after the sinc filter. One option to attenuate the 10 kHz noise is to
filter output and the actual phase current. Notice how the 10 kHz switching increase the decimation rate, but doing so would result in an unacceptably
component of the phase current is phase shifted but hardly attenuated by long group delay. A different approach is needed.
the sinc filter. Now, suppose the motor control algorithm is executed once
per PWM period and that the latest sinc filter output is read at the beginning Improving Measurement Through Synchronization
of the period. Effectively, the sinc filter output is downsampled to match the The main problem with the antialiasing approach discussed in the previous
update rate of the control algorithm. The downsampling and resulting signal section is illustrated in Figure 8. The output from the sinc filter is read at
is shown as the sampled sinc output in Figure 6b. Figure 7a shows the result some instant uncorrelated to the switching component of the phase current.
of a full fundamental period that is filtered and sampled at the PWM rate. When the output is read, the filter delivers a weighted average of the input
It is clear the phase current measurement is highly distorted and would signal according to the impulse response. Sometimes this weighted aver-
lead to poor control performance. Increased torque ripple and a need to age spans the low point of the switching waveform and sometimes it spans
reduce the bandwidth of the current control loop should be expected. If the the highpoint. As a result, the signal used as feedback contains significant
measurement in Figure 7a is subtracted from the ideal measurement (Figure 5a), noise with frequencies from 0 Hz to half the PWM frequency.
the error is obtained (see Figure 7b). The error is approximately 7% of the
full-scale signal, which is very far from matching the expected 14 ENOB. Sample Points

Phase
This sigma-delta measurement and aliasing scenario demonstrates a very Current
common operating mode of sigma-delta-based current measurement and
how it has led designers to conclude that sigma-delta ADCs are unsuited
for motor drives. However, the example does not demonstrate the poor Impulse
Response
performance of the ADC itself. Rather, it demonstrates poor performance
of the remaining signal chain because it is not properly set up for phase
Time
current measurement.
Figure 8. The impulse response is uncorrelated to the switching waveform.
The ADC samples the input signal at several megahertz (typically 10 MHz
to 20 MHz), and, with a decimation rate of 256, the sinc filter effectively A sigma-delta ADC samples continuously and the sinc filter outputs multiple
removes the modulation noise. With such a high sampling rate the ripple measurements per PWM cycle (typically 10 to 20). Since each measurement
component of the phase current is present in the filter output and that can spans 3 decimation cycles, the impulse responses overlap. For simplifica-
become a problem in the downsampling stage of the signal chain (see tion, only three of these measurement/impulse responses are shown in
Figure 1). If the ripple component is not sufficiently attenuated, and the Figure 8.
motor control algorithm consumes current feedback at the PWM rate, the
result is aliasing due to downsampling.

4 // Analog Dialogue 53-10, October 2019

 1 0.05
Sampled Sinc Output Measurement Error
0.9 0.04

0.8 0.03

0.7 0.02
Phase Current (–)

0.6 0.01

Error (–)
0.5 0

0.4 –0.01

0.3 –0.02

0.2 –0.03

0.1 –0.04

0 –0.05
0 1 2 3 4 5 6 0 1 2 3 4 5 6
Time (ms) Time (ms)
(a) (b)

Figure 9. (a) Sampled output from the sinc filter when the impulse response is locked to PWM. (b) Measurement error.

The source of the problem is that the impulse response is not locked to the To get rid of the first-order harmonic measurement error, the impulse
switching component of current, which in turn is locked to PWM. The solu- response must always be centered around the beginning or around the
tion is to select the decimation rate so that there is a fixed integer number center of a PWM period where the phase current is exactly at its average
of decimation cycles per PWM period. For example, with a PWM frequency value. Figure 11 shows the impulse response centered at the beginning of a
of 10 kHz, a modulator clock of 20 MHz, and a decimation rate of 200, there switching period. Around this point the switching waveform is symmetrical,
are exactly 10 decimation cycles per PWM period. With a fixed number of so by having an equal number of measurement points on either side, the
decimation cycles per PWM period, the impulse response is locked to PWM ripple component averages out to zero around this point.
at all times and the measurement used for feedback is captured at the same
point within the PWM cycle. The measurement of the phase current in this Sample Points
synchronization scheme is shown in Figure 9a. Phase
Current
It is clear that synchronizing the impulse response to PWM has had a positive
effect. The noise has been eliminated and, at first glance, the result seems
similar to the ideal measurement in Figure 5a. However, when the sigma- Impulse
Response
delta measurement is subtracted from the ideal measurement, the result is
the error signal in Figure 9b. The error magnitude is similar to the one shown
Time
in Figure 7b, but the frequency spectrum has changed. Now the error is a
first-order harmonic that is equivalent to a gain error. The reason for this error Figure 11. The impulse response is locked to the switching period and aligned to the
pattern is illustrated in Figure 10. ideal measurement point.

With the impulse response locked and centered around the instant of aver-
Sample Points age current, the resulting measurement is shown in Figure 12a and the
Phase measurement error is shown in Figure 12b. As the ideally sampled measure-
Current
ment, the signal is free of both white noise and gain error.
The presented results show that the quality of a sigma-delta measurement
Impulse relies on much more than just the decimation rate. The common belief that
Response
increasing the decimation rate will result in higher ENOB is only true in the
absence of aliasing. Controlling the filter update rate and phase with respect
Time
to the input signal is much more important than the decimation rate. As an
Figure 10. The impulse response is locked to a fixed point within the switching period. example, compare Figure 7, which was based on a decimation rate of 256,
and Figure 12, which was based on a decimation rate of 200. Lowering the
While the white noise error component has been eliminated, the signal is
decimation rate improved the measurement significantly.
still distorted because the measurement is biased by the switching com-
ponent. In Figure 10, notice how the sinc filter impulse response gives a
weighted average around the peak of the switching waveform. Depending
on the phase of the impulse response with respect to PWM, the size of the
bias is limited only by the magnitude of the ripple current. As illustrated in
Figure 3, the magnitude of the ripple component changes over a fundamen-
tal period, with the highest ripple at the peak of the fundamental current
and the lowest ripple at zero-crossing. Because of this, the measurement
error is a first-order harmonic component.

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 1 0.05
Sampled Sinc Output Measurement Error
0.9 0.04

0.8 0.03

0.7 0.02
Phase Current (–)

0.6 0.01

Error (–)
0.5 0

0.4 –0.01

0.3 –0.02

0.2 –0.03

0.1 –0.04

0 –0.05
0 1 2 3 4 5 6 0 1 2 3 4 5 6
Time (ms) Time (ms)
(a) (b)

Figure 12. (a) Sampled output from the sinc filter when the impulse response is locked to PWM and centered around the instant of average current. (b) Measurement error.

Summary of Part 1 This concludes Part 1 of this article series. Part 2 will move on to propose
a new sinc filter structure that is particularly suited for motor control
In summary, the conditions for an optimized sigma-delta-based phase
applications and discuss how to best implement sinc filters on an FPGA.
current measurement are:
To verify the ideas discussed in the article series, Part 2 also presents
XX The impulse response of a third-order sinc filter is 3 decimation cycles several measurements performed on an FPGA-based, 3-phase servo drive.
long, meaning it takes 3 decimation cycles for data to propagate through
the filter. References
XX The impulse response of the filter must be centered around the instant 1
Jens Sorensen and Dara O’Sullivan.“A System Approach to Understanding
of average current. the Impact of Nonideal Effects in a Motor Drive Current Loop.”
XX 1.5 decimation cycles of the impulse response must be located before Proceedings of PCIM Europe 2016.
the instant of average current and 1.5 decimation cycles of the impulse 2
Jens Sorensen. “∑-Δ Conversion Used for Motor Control.” Proceedings of
response must be located after the instant of average current. PCIM Europe 2015.
XX The sinc filter generates multiple outputs during a PWM period, but only 3
Ahmet M. Hava, Russel J. Kerkman, and Thomas A. Lipo. “Simple
one of these outputs is used. The rest are ignored.
Analytical and Graphical Methods for Carrier-Based PWM-VSI Drives.”
IEEE Transactions on Power Electronics, January 1999.

About the Author

Jens Sorensen is a system applications engineer at Analog Devices, where he works with motor control solutions for
industrial applications. He received his M.Eng.Sc. from Aalborg University, Denmark. His main interests are control
algorithms, power electronics, and control processors. He can be reached at [email protected].

About the Author

Dara O’Sullivan is a system applications manager with the connected motion and robotics team within the Automation
and Energy Business Unit at Analog Devices. His area of expertise is power conversion, control, and monitoring in industrial
motion control applications. He received his B.E, M.Eng.Sc., and Ph.D. from University College Cork, Ireland, and he has
worked in industrial and renewable energy applications in a range of research, consultancy, and industry positions since
2001. He can be reached at [email protected].

About the Author

Shane O’Meara is a system applications engineer with the Connected Motion and Robotics Team at Analog Devices. His
area of expertise is precision conversion and signal chains for control and monitoring in industrial motion control applica-
tions. He received his B.Eng. from the University of Limerick and joined Analog Devices in 2011. He can be reached at
[email protected].

6 // Analog Dialogue 53-10, October 2019