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Lecture4 Chapter6 - Problem-Solving Session

This document contains problems and solutions related to designing shift registers and counters using logic gates and flip-flops. Problem 6-6 involves designing a 4-bit shift register with parallel load and control inputs for shift and load functions. Problem 6-7 asks to draw the logic diagram of a 4-bit register using 4 D flip-flops and 4:1 multiplexers with mode selection inputs. The final problem asks to design a synchronous modulo-6 up-down counter with a single input, including drawing the state diagram, listing the state transition table, and providing the circuit design using D flip-flops and external logic gates.

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46 views14 pages

Lecture4 Chapter6 - Problem-Solving Session

This document contains problems and solutions related to designing shift registers and counters using logic gates and flip-flops. Problem 6-6 involves designing a 4-bit shift register with parallel load and control inputs for shift and load functions. Problem 6-7 asks to draw the logic diagram of a 4-bit register using 4 D flip-flops and 4:1 multiplexers with mode selection inputs. The final problem asks to design a synchronous modulo-6 up-down counter with a single input, including drawing the state diagram, listing the state transition table, and providing the circuit design using D flip-flops and external logic gates.

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Walrus Produce
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter6: Registers and Counters

Lecture4- Problem-Solving Session


Engr. Arshad Nazir, Asst Prof
Dept of Electrical Engineering
Spring 2022 SEECS 1
Problem6-6: Design a four-bit shift register with parallel load, using D flip-flips. There
are two control inputs: Shift and Load. When Shift=1, the contents of the register are
shifted by one position. New data are transferred into the register when Load=1 and
Shift=0. If both control inputs are equal to 0, the contents of the register do not
change.

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Problem6-7: Draw the logic diagram of a 4-bit register with four D flip-flops and four
4:1 multiplexers with mode selection inputs S1 and S0. The register operates according
to the following function table.

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Problem 6-13: Show that a BCD ripple counter can be constructed from a 4-bit binary
ripple counter with asynchronous Clear input and a NAND gate that detects the
occurrence of the count 1010.

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Problem 6-19: The flip-flop input equations for a BCD counter using T flip-flops are
given in section 6-4. Obtain the input equations for a BCD counter that uses
(a) JK flip-flops and
(b) D flip-flops

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Problem 6-28: Design a 3-bit counter with the following repeated binary sequence: 0,
1, 2, 4, 6. Use D flip-flops. Is your counter self-correcting.

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Problem: Design a synchronous modulo-6 up-down counter with a single input
line x. The counter uses a creeping code, advances following x=0 and regresses for x=1.
it operates as under:-
When x=0: counts up through the sequence 000, 001, 011, 111, 110, 100, and repeat
When x=1: counts down through the sequence 000, 100, 110, 111, 011, 001, and
repeat.
(a) Draw the state diagram
(b) List the state transition table
(c) Design the modulo-6 up-down counter with D flip-flops and external AND, OR, and
NOT gates as required.

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Figure Design of Modulo-6 up-down Counter with D Flip-Flops and external gates

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The End

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