Lab 4
Lab 4
Simulation waveform:
Transcript:
Simulation waveform:
Transcript:
3.Write a Verilog code for 4 bit synchronous loadable up counter and verify using
testbench.
Design code:
module synup_counter(clk,rst,load,din,dout);
input clk,rst,load;
input [3:0]din;
output reg [3:0]dout;
always@(posedge clk)
begin
if(rst)
dout<=4'b0000;
else if(load)
dout<=din;
else
dout<=dout+1'b1;
end
endmodule
Simulation code:
module synup_counter_tb;
reg clk,rst,load;
reg [3:0]din;
wire [3:0]dout;
synup_counter DUT(.clk(clk),.rst(rst),.load(load),.din(din),.dout(dout));
initial
begin
clk=1'b0;
forever #20 clk=~clk;
end
task rst_ip;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
task load_ip(input [3:0]k);
begin
@(negedge clk)
load=1'b1;
din=k;
@(negedge clk)
load=1'b0;
end
endtask
initial
begin
rst_ip;
load_ip(4'b1000);
end
initial $monitor("clk=%b,rst=%b,load=%b,din=%b,dout=%b",clk,rst,load,din,dout);
initial #1000 $finish;
endmodule
Synthesis circuit:
Simulation waveform:
Transcript:
4.Write a Verilog code for JK flip-flop and verify using testbench.
Design code:
module jkflipflop(j,k,clk,rst,q,qb);
input j,k,clk,rst;
output reg q;
output qb;
always@(posedge clk)
begin
if(rst)
q<=0;
else if(j<=0&k<=0)
q<=q;
else if(j<=0&k<=1)
q<=0;
else if(j<=1&k<=0)
q<=1;
else if(j<=1&k<=1)
q<=~q;
end
assign qb=~q;
endmodule
Simulation code:
module jkflipflop_tb;
reg J,K,clk,rst;
wire Q,QB;
jkflipflop DUT(.j(J),.k(K),.clk(clk),.rst(rst),.q(Q),.qb(QB));
initial
begin
clk=0;
forever #20 clk=~clk;
end
initial begin
rst=1;
J<=0;K<=0;
#100;
rst=0;
J<=0;K<=0;
#100;
J<=0;K<=1;
#100;
J<=1;K<=0;
#100;
J<=1;K<=1;
#100;
end
initial $monitor("J=%b,K=%b,clk=%b,rst=%b,Q=%b,QB=%b",J,K,clk,rst,Q,QB);
initial #500 $finish;
endmodule
Synthesis circuit:
Simulation waveform:
Transcript:
5.Implement SR latch using gate level modelling and verify using testbench.
Design code:
module srlatch(s,r,q,qb);
input s,r;
output q,qb;
nand (q,s,qb);
nand (qb,r,q);
endmodule
Simulation code:
module srlatch_tb;
reg s,r;
wire q,qb;
srlatch DUT(.s(s),.r(r),.q(q),.qb(qb));
initial
begin
s<=0;r<=0;
#100;
s<=0;r<=1;
#100;
s<=1;r<=0;
#100;
s<=1;r<=1;
#100;
end
initial $monitor("s=%b,r=%b,q=%b,qb=%b",s,r,q,qb);
initial #500 $finish;
endmodule
Synthesis circuit:
Simulation waveform:
Transcript:
6.Write a rtl code for 4 bit mod12 counter and verify using testbench.
Design code:
module mod12upcont(clk,rst,load,din,dout);
input clk,rst,load;
input [3:0]din;
output reg [3:0]dout;
always@(posedge clk)
begin
if(rst)
dout<=4'b0000;
else if(load && din <=4'b1011)
dout<=din;
else if(dout==4'b1011)
dout<=4'b0000;
else
dout<=dout+1'b1;
end
endmodule
Simulation code;
module mod12upcont_tb;
reg clk,rst,load;
reg [3:0]din;
wire [3:0]dout;
mod12upcont DUT(.clk(clk),.rst(rst),.load(load),.din(din),.dout(dout));
initial
begin
clk=1'b0;
forever #20 clk=~clk;
end
task rst_ip;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
task load_ip(input [3:0]k);
begin
@(negedge clk)
load=1'b1;
din=k;
@(negedge clk)
load=1'b0;
end
endtask
initial begin
rst_ip;
load_ip(4'b0000);
end
initial $monitor("clk=%b,rst=%b,load=%b,din=%b,dout=%b",clk,rst,load,din,dout);
initial #500 $finish;
endmodule
Synthesis circuit:
Simulation waveform:
Transcript:
7.Write a rtl code for 4 bit loadable synchronous up down counter.
Design code:
module synupdown(clk,rst,load,dir,din,dout);
input clk,rst,load,dir;
input [3:0]din;
output reg [3:0]dout;
always@(posedge clk)
begin
if(rst)
dout<=4'b0000;
else if(load)
dout<=din;
else
begin
case(dir)
1'b0:dout<=dout+1'b1;
1'b1:dout<=dout-1'b1;
endcase
end
end
endmodule
Simulation code:
module synupdown_tb;
reg clk,rst,load,dir;
reg [3:0]din;
wire [3:0]dout;
synupdown DUT(.clk(clk),.rst(rst),.load(load),.dir(dir),.din(din),.dout(dout));
initial
begin
clk=1'b0;
forever #20 clk=~clk;
end
task rst_ip;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
task load_ip(input [3:0]k);
begin
@(negedge clk)
load=1'b1;
din=k;
@(negedge clk)
load=1'b0;
end
endtask
initial
begin
rst_ip;
load_ip(4'b1000);
dir=1'b0;
#30;
load_ip(4'b0100);
dir=1'b1;
#40;
end
initial
$monitor("clk=%b,rst=%b,load=%b,dir=%b,din=%b,dout=%b",clk,rst,load,dir,din,dout);
initial #500 $finish;
endmodule
Synthesis circuit:
Simulation waveform:
Transcript:
8.write a rtl code for 4 bit SISO shift register and verify using testbench.
Design code:
module sisomod(clk,clear,si,so);
input clk,si,clear;
output so;
reg so;
begin
if (clear)
so = tmp[3];
end
endmodule
Simulation code:
module sisomod_tb;
reg clk;
reg clear;
reg si;
wire so;
initial begin
clk = 0;
clear = 0;
si = 0;
#5 clear=1'b1;
#5 clear=1'b0;
#10 si=1'b1;
#10 si=1'b0;
#10 si=1'b0;
#10 si=1'b1;
end
endmodule
Synthesis circuit:
Simulation waveform:
Transcript: