100% found this document useful (1 vote)
551 views25 pages

Lab 4

The document describes various sequential logic circuits including flip-flops, counters, and shift registers. It provides Verilog code examples and testbenches to simulate the behavior of D flip-flops, T flip-flops, 4-bit counters, JK flip-flops, and other basic sequential elements. It also includes synthesis results and simulation waveforms for each circuit.

Uploaded by

Santosh Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
100% found this document useful (1 vote)
551 views25 pages

Lab 4

The document describes various sequential logic circuits including flip-flops, counters, and shift registers. It provides Verilog code examples and testbenches to simulate the behavior of D flip-flops, T flip-flops, 4-bit counters, JK flip-flops, and other basic sequential elements. It also includes synthesis results and simulation waveforms for each circuit.

Uploaded by

Santosh Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 25

Lab4: Sequential Logic (Flip-Flop, Counters, Shift registers)

1.Write an RTL description and testbench for D flip-flop.


Design code:
module dflipflop(din,clk,rst,q,qb);
input din,clk,rst;
output reg q;
output qb;
always@(posedge clk)
begin
if(rst)
q<=0;
else
q<=din;
end
assign qb=~q;
endmodule
Simulation code:
module dflipflop_tb;
reg D,clk,rst;
wire Q,QB;
dflipflop DUT(.din(D),.clk(clk),.rst(rst),.q(Q),.qb(QB));
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial begin
rst=1;
D<=0;
#100;
rst=0;
D<=1;
#100;
D<=0;
#100;
D<=1;
#100;
end
initial $monitor("D=%b,clk=%b,rst=%b,Q=%b,QB=%b",D,clk,rst,Q,QB);
initial #500 $finish;
endmodule
Synthesis circuit:

Simulation waveform:
Transcript:

2.Write structural model for T flip-flop using D flip-flop.


Design code:
module tflipflop(t,clk,rst,q,qb);
input t,clk,rst;
output reg q;
output qb;
always@(posedge clk)
begin
if(rst)
q<=0;
else if(t)
q<=~q;
else
q<=q;
end
assign qb=~q;
endmodule
Simulation code:
module tflipflop_tb;
reg T,clk,rst;
wire Q,QB;
tflipflop DUT(.t(T),.clk(clk),.rst(rst),.q(Q),.qb(QB));
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial begin
rst=1;
T<=0;
#100;
rst=0;
T<=1;
#100;
T<=0;
#100;
T<=1;
#100;
T<=0;
#100;
end
initial $monitor("T=%b,clk=%b,rst=%b,Q=%b,QB=%b",T,clk,rst,Q,QB);
initial #600 $finish;
endmodule
Synthesis circuit:

Simulation waveform:

Transcript:
3.Write a Verilog code for 4 bit synchronous loadable up counter and verify using
testbench.
Design code:
module synup_counter(clk,rst,load,din,dout);
input clk,rst,load;
input [3:0]din;
output reg [3:0]dout;
always@(posedge clk)
begin
if(rst)
dout<=4'b0000;
else if(load)
dout<=din;
else
dout<=dout+1'b1;
end
endmodule
Simulation code:
module synup_counter_tb;
reg clk,rst,load;
reg [3:0]din;
wire [3:0]dout;
synup_counter DUT(.clk(clk),.rst(rst),.load(load),.din(din),.dout(dout));
initial
begin
clk=1'b0;
forever #20 clk=~clk;
end
task rst_ip;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
task load_ip(input [3:0]k);
begin
@(negedge clk)
load=1'b1;
din=k;
@(negedge clk)
load=1'b0;
end
endtask
initial
begin
rst_ip;
load_ip(4'b1000);
end
initial $monitor("clk=%b,rst=%b,load=%b,din=%b,dout=%b",clk,rst,load,din,dout);
initial #1000 $finish;
endmodule
Synthesis circuit:
Simulation waveform:

Transcript:
4.Write a Verilog code for JK flip-flop and verify using testbench.
Design code:
module jkflipflop(j,k,clk,rst,q,qb);
input j,k,clk,rst;
output reg q;
output qb;
always@(posedge clk)
begin
if(rst)
q<=0;
else if(j<=0&k<=0)
q<=q;
else if(j<=0&k<=1)
q<=0;
else if(j<=1&k<=0)
q<=1;
else if(j<=1&k<=1)
q<=~q;
end
assign qb=~q;
endmodule
Simulation code:
module jkflipflop_tb;
reg J,K,clk,rst;
wire Q,QB;
jkflipflop DUT(.j(J),.k(K),.clk(clk),.rst(rst),.q(Q),.qb(QB));
initial
begin
clk=0;
forever #20 clk=~clk;
end
initial begin
rst=1;
J<=0;K<=0;
#100;
rst=0;
J<=0;K<=0;
#100;
J<=0;K<=1;
#100;
J<=1;K<=0;
#100;
J<=1;K<=1;
#100;
end
initial $monitor("J=%b,K=%b,clk=%b,rst=%b,Q=%b,QB=%b",J,K,clk,rst,Q,QB);
initial #500 $finish;
endmodule
Synthesis circuit:
Simulation waveform:

Transcript:
5.Implement SR latch using gate level modelling and verify using testbench.
Design code:
module srlatch(s,r,q,qb);
input s,r;
output q,qb;
nand (q,s,qb);
nand (qb,r,q);
endmodule
Simulation code:
module srlatch_tb;
reg s,r;
wire q,qb;
srlatch DUT(.s(s),.r(r),.q(q),.qb(qb));
initial
begin
s<=0;r<=0;
#100;
s<=0;r<=1;
#100;
s<=1;r<=0;
#100;
s<=1;r<=1;
#100;
end
initial $monitor("s=%b,r=%b,q=%b,qb=%b",s,r,q,qb);
initial #500 $finish;
endmodule
Synthesis circuit:

Simulation waveform:

Transcript:
6.Write a rtl code for 4 bit mod12 counter and verify using testbench.
Design code:
module mod12upcont(clk,rst,load,din,dout);
input clk,rst,load;
input [3:0]din;
output reg [3:0]dout;
always@(posedge clk)
begin
if(rst)
dout<=4'b0000;
else if(load && din <=4'b1011)
dout<=din;
else if(dout==4'b1011)
dout<=4'b0000;
else
dout<=dout+1'b1;
end
endmodule
Simulation code;
module mod12upcont_tb;
reg clk,rst,load;
reg [3:0]din;
wire [3:0]dout;
mod12upcont DUT(.clk(clk),.rst(rst),.load(load),.din(din),.dout(dout));
initial
begin
clk=1'b0;
forever #20 clk=~clk;
end
task rst_ip;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
task load_ip(input [3:0]k);
begin
@(negedge clk)
load=1'b1;
din=k;
@(negedge clk)
load=1'b0;
end
endtask
initial begin
rst_ip;
load_ip(4'b0000);
end
initial $monitor("clk=%b,rst=%b,load=%b,din=%b,dout=%b",clk,rst,load,din,dout);
initial #500 $finish;
endmodule
Synthesis circuit:

Simulation waveform:

Transcript:
7.Write a rtl code for 4 bit loadable synchronous up down counter.
Design code:
module synupdown(clk,rst,load,dir,din,dout);
input clk,rst,load,dir;
input [3:0]din;
output reg [3:0]dout;
always@(posedge clk)
begin
if(rst)
dout<=4'b0000;
else if(load)
dout<=din;
else
begin
case(dir)
1'b0:dout<=dout+1'b1;
1'b1:dout<=dout-1'b1;
endcase
end
end
endmodule
Simulation code:
module synupdown_tb;
reg clk,rst,load,dir;
reg [3:0]din;
wire [3:0]dout;
synupdown DUT(.clk(clk),.rst(rst),.load(load),.dir(dir),.din(din),.dout(dout));
initial
begin
clk=1'b0;
forever #20 clk=~clk;
end
task rst_ip;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
task load_ip(input [3:0]k);
begin
@(negedge clk)
load=1'b1;
din=k;
@(negedge clk)
load=1'b0;
end
endtask
initial
begin
rst_ip;
load_ip(4'b1000);
dir=1'b0;
#30;
load_ip(4'b0100);
dir=1'b1;
#40;
end
initial
$monitor("clk=%b,rst=%b,load=%b,dir=%b,din=%b,dout=%b",clk,rst,load,dir,din,dout);
initial #500 $finish;
endmodule
Synthesis circuit:

Simulation waveform:
Transcript:
8.write a rtl code for 4 bit SISO shift register and verify using testbench.
Design code:
module sisomod(clk,clear,si,so);

input clk,si,clear;

output so;

reg so;

reg [3:0] tmp;

always @(posedge clk )

begin

if (clear)

tmp <= 4'b0000;


else

tmp <= tmp << 1;

tmp[0] <= si;

so = tmp[3];

end
endmodule
Simulation code:
module sisomod_tb;

reg clk;

reg clear;

reg si;

wire so;

sisomod DUT (.clk(clk), .clear(clear),.si(si),.so(so));

initial begin

clk = 0;

clear = 0;

si = 0;

#5 clear=1'b1;

#5 clear=1'b0;

#10 si=1'b1;

#10 si=1'b0;
#10 si=1'b0;

#10 si=1'b1;

end

always #5 clk = ~clk;


initial $monitor("clk=%b,clear=%b,si=%b,so=%b",clk,clear,si,so);
initial #150 $stop;

endmodule
Synthesis circuit:

Simulation waveform:
Transcript:

You might also like