ADE 18CS33 Module 4 Notes

Q. Write a note on flip-flop timing.

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Q. Explain switch contact bounce circuits.

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Q. Explain the working of an SR Latch using NOR gate.

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Q. Explain the timing diagram for SR latch.

 When S changes to 1 at time tl, Q changes to 1 a short time () later. ( represents the
response time or delay time of the latch.)
 At time t2, when S changes back to 0, Q does not change.
 At time t3, R changes to 1, and Q changes back to 0 a short time ( ) later. The duration
of the S (or R) input pulse must normally be at least as great as  in order for a change in
the state of Q to occur. If S = 1 for a time less than , the gate output will not change and
the latch will not change state.

Q. Explain the working of an SR Latch using NAND gate.

(PTO)

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Q. Explain the working of clocked SR flip-flop.

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Q. Explain the working of a clocked D flip-flop/ gated D latch.

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Gated D Latch – construction and timing diagram

 When G = 0, S = R = 0, so Q does not change.

 When G = 1 and D = 1, S = 1 and R = 0, so Q is set to 1.
 When G = 1 and D = 0, S = 0 and R = 1, so Q is reset to 0. In other words, when G = 1,
the Q output follows the D input, and when G = 0, the Q output holds the last value of D
(no state change). This type of latch is also referred to as a transparent latch because
when G = 1, the Q output is the same as the D input.

State table and characteristic equation for gated D latch

.
+
The state table shows the next state output (Q ) for each particular combination of gate input (G),
D input and present output (Q).

Plotting this on a K-Map gives an expression for Q+ in terms of G, D and Q.

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Q. Explain the working of an edge-triggered D flip-flop.

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A D flip-flop has two inputs, D (data) and Ck (clock). The small arrowhead on the flip-flop
symbol identifies the clock input. Unlike the D latch, the flip-flop output changes only in
response to the clock, not to a change in D. If the output can change in response to a 0 to 1
transition on the clock input, we say that the flip-flop is triggered on the rising edge (or positive
edge) of the clock. If the output can change in response to a 1 to 0 transition on the clock input,
we say that the flip flop is triggered on the falling edge (or negative edge) of the clock. An
inversion bubble on the clock input indicates a falling-edge trigger (b), and no bubble indicates a
rising-edge trigger (a).The term active edge refers to the clock edge (rising or falling) that
triggers the flip-flop state change.

Timing diagram for Falling edge triggered/negative edge triggered D flip-flop

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The state of a D flip-flop after the active clock edge (Q+) is equal to the input (D) before the
active edge. For example, if D = 1 before the clock pulse, Q = 1 after the active edge, regardless
of the previous value of Q. Therefore, the characteristic equation is Q+ = D. If D changes at most
once following each clock pulse, the output of the flip-flop is the same as the D input, except that
the output changes are delayed until after the active edge of the clock pulse, as illustrated in
figure above.

Rising edge triggered/positive edge triggered D flip-flop

A rising-edge-triggered D flip-flop can be constructed from two gated D latches and an inverter,
as shown in Figure (a).The timing diagram is shown in Figure (b).
When CLK = 0, G1 = 1, and the first latch is transparent so that the P output follows the D input.
Because G2 = 0, the second latch holds the current value of Q.
When CLK changes to 1, G1 changes to 0, and the current value of D is stored in the first latch.
Because G2 = 1, the value of P flows through the second latch to the Q output.

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When CLK changes back to 0, the second latch takes on the value of P and holds it and, then, the
first latch starts following the D input again.
If the first latch starts following the D input before the second latch takes on the value of P, the
flip flop will not function properly. Therefore, the circuit designers must pay careful attention to
timing issues when designing edge-triggered flip-flops.
With this circuit, output state changes occur only following the rising edge of the clock. The
value of D at the time of the rising edge of the clock determines the value of Q, and any extra
changes in D that occur between rising clock edges have no effect on Q.

Q. Explain the working of SR flip-flop with timing diagram.

An S-R flip-flop (Figure above) is similar to an S-R latch in that S = 1 sets the Q output to 1, and
R = 1 resets the Q output to 0.The essential difference is that the flip flop has a clock input, and
the Q output can change only after an active clock edge. The truth table and characteristic
equation for the flip-flop are the same as for the latch, but the interpretation of Q+ is different.
For the latch, Q+ is the value of Q after the propagation delay through the latch, while for the
flip-flop, Q+ is the value that Q assumes after the active clock edge.

The next figure (a) shows an S-R flip-flop constructed from two S-R latches and gates.

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This flip-flop changes state after the rising edge of the clock. The circuit is often referred to as a
master-slave flip-flop.
 When CLK = 0, the S and R inputs set the outputs of the master latch to the appropriate
value while the slave latch holds the previous value of Q.
 When the clock changes from 0 to 1, the value of P is held in the master latch and this
value is transferred to the slave latch. The master latch holds the value of P while CLK =
1, and, hence, Q does not change.
 When the clock changes from 1 to 0, the Q value is latched in the slave, and the master
can process new inputs. Figure (b) shows the timing diagram. Initially, S = 1 and Q
changes to 1 at t1. Then R = 1 and Q changes to 0 at t3.

At first glance, this flip-flop appears to operate just like an edge-triggered flip-flop, but there is a
subtle difference. For a rising-edge-triggered flip-flop the value of the inputs is sensed at the
rising edge of the clock, and the inputs can change while the clock is low. For the master-slave
flip-flop, if the inputs change while the clock is low, the flip-flop output may be incorrect. For
example, in Figure (b) at t4, S = 1 and R = 0, so P changes to 1. Then S changes to 0 at t5, but P
does not change, so at t5, Q changes to 1 after the rising edge of CLK. However, at t5, S = R = 0,
so the state of Q should not change. We can solve this problem if we only allow the S and R
inputs to change while the clock is high.

Q. Explain the working of JK flip-flop with timing diagram.

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The J-K flip-flop is an extended version of the S-R flip-flop. The J-K flip-flop has three inputs—
J, K, and the clock (CK).The J input corresponds to S, and K corresponds to R. That is, if J = 1
and K = 0, the flip-flop output is set to Q = 1 after the active clock edge; and if K = 1 and J = 0,
the flip-flop output is reset to Q = 0 after the active edge. Unlike the S-R flip-flop, a 1 input may
be applied simultaneously to J and K, in which case the flip-flop changes state after the active
clock edge. When J = K = 1, the active edge will cause Q to change from 0 to 1, or from 1 to
0.The next state table and characteristic equation for the J-K flip-flop are given in Figure (b).

This flip-flop changes state a short time (tp) after the rising edge of the clock pulse, provided that
J and K have appropriate values. If J = 1 and K = 0 when Clock = 0, Q will be set to 1 following
the rising edge. If K = 1 and J = 0 when Clock = 0, Q will be set to 0 after the rising edge.
Similarly, if J = K = 1, Q will change state after the rising edge. Referring to Figure (c), because
Q = 0, J = l, and K = 0 before the first rising clock edge, Q changes to 1 at t1. Because Q = 1, J =
0, and K = 1 before the second rising clock edge, Q changes to 0 at t2. Because Q = 0, J = 1, and
K = 1 before the third rising clock edge, Q changes to 1 at t3.

One way to realize the J-K flip-flop is with two S-R latches connected in a master-slave
arrangement, as shown in the next figure. This is the same circuit as for the S-R master-slave
flip-flop, except S and R have been replaced with J and K, and the Q and Q outputs are feeding
back into the input gates. Because S = J.Q‘.Clk‘ and R = K.Q. Clk‘, only one of S and R
inputs to the first latch can be 1 at any given time. If Q = 0 and J = 1, then S = 1 and R= 0,
regardless of the value of K. If Q = 1 and K = 1, then S = 0 and R= 1, regardless of the value of
J.

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Q. Explain the working of JK master-slave flip-flop.

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Q. Explain the working of T flip-flop with timing diagram.

The T flip-flop, also called the toggle flip-flop, is frequently used in building counters.
Most CPLDs and FPGAs can be programmed to implement T flip-flops.
The T flip-flop in Figure (a) has a T input and a clock input. When T = 1 the flip-flop changes
state after the active edge of the clock. When T = 0, no state change occurs.
The next state table and characteristic equation for the T flip-flop are given in Figure (b). The
characteristic equation states that the next state of the flip-flop (Q+) will be 1 if and only if the
present state (Q) is 1 and T = 0 or the present state is 0 and T = 1.

The next figure shows a timing diagram for the T flip-flop. At times t2 and t4 the T input is 1 and
the flip-flop state (Q) changes a short time (tp) after the falling edge of the clock pulse. At times
tl and t3 the T input is 0, and the clock edge does not cause a change of state.

Implementation of T flip-flops

One way to implement a T flip-flop is to connect the J and K inputs of a J-K flip flop together, as
shown in Figure (a). Substituting T for J and K in the J-K characteristic equation gives

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which is the characteristic equation for the T flip-flop.

Another way to realize a T flip-flop is with a D flip-flop and an exclusive-OR gate (figure (b)).
The D input is Q ⊕ T, so Q+ = Q ⊕ T = TQ‘ + T‘Q, which is the characteristic equation for the
T flip-flop.

Q. Derive the characteristic equations, state transition diagrams and excitation tables of SR, JK,
D and T flip-flops.

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(a) SR flip-flop

Characteristic equation of SR FF

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State transition diagram of SR FF

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Excitation Table of SR FF

(b) JK flip-flop

Characteristic equation of JK FF

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State transition diagram of JK FF Excitation Table of JK FF

(c) D flip-flop

Characteristic equation of D FF

Excitation Table of D FF

State transition diagram of D FF

(d) T flip-flop

Characteristic equation of T FF

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State transition diagram of T FF

Excitation Table of T FF

Flip-flops with Additional Inputs

Preset (PreN) and Clear (ClrN)

• Active Low
• Overrides the clock and D inputs
• Asynchronous inputs

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Timing Diagram for D Flip-Flop with Asynchronous Clear and Preset

D Flip-Flop with Clock Enable

Q1.
Assume that the inverter in the given circuit has a propagation delay of 5 ns and the
AND gate has a propagation delay of 10 ns. Draw a timing diagram for the circuit
showing X, Y, and Z. Assume that X is initially 0, Y is initially 1, after 10 ns X
becomes 1 for 80 ns, and then X is 0 again.

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Z responds to X and to Y after 10 ns; Y responds to

Z after 5 ns.

Q2. A latch can be constructed from an OR gate, an AND gate, and an inverter
connected as follows:

(a) What restriction must be placed on R and H so that P will always equal Q
(under steady-state conditions)?
(b) Construct a next-state table and derive the characteristic (next-state) equation
for the latch.
(c) Complete the following timing diagram for the latch.

Answer:

P and Q will oscillate.

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Q3. Design a gated D latch using only NAND gates and one inverter.

Q4. A reset-dominant flip-flop behaves like an S-R flip-flop, except that the input

S = R = 1 is allowed, and the flip-flop is reset when S = R = 1.

(a) Derive the characteristic equation for a reset-dominant flip-flop.

(b) Show how a reset-dominant flip-flop can be constructed by adding gate(s) to
an S-R flip-flop.

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Q5. Complete the following timing diagram for the flip-flop shown below:

Answer:

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Q6.

Answer:

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Q7.

Answer:

Q8.

Answer:

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VHDL:
The two most popular hardware description languages are VHDL and Verilog.

VHDL is a hardware description language that is used to describe the behavior and
structure of digital systems. The acronym VHDL stands for VHSIC Hardware
Description Language, and VHSIC in turn stands for Very High Speed Integrated
Circuit. However, VHDL is a general-purpose hardware description language
which can be used to describe and simulate the operation of a wide variety of
digital systems, ranging in complexity from a few gates to an interconnection of
many complex integrated circuits.

VHDL can describe a digital system at several different levels—behavioral, data

flow, and structural. For example, a binary adder could be described at the
behavioral level in terms of its function of adding two binary numbers, without
giving any implementation details. The same adder could be described at the data
flow level by giving the logic equations for the adder. Finally, the adder could be
described at the structural level by specifying the interconnections of the gates
which make up the adder.

VHDL leads naturally to a top-down design methodology in which the system is

first specified at a high level and tested using a simulator. After the system is
debugged at this level, the design can gradually be refined, eventually leading to a
structural description which is closely related to the actual hardware
implementation. VHDL was designed to be technology independent. If a design is
described in VHDL and implemented in today‘s technology, the same VHDL
description could be used as a starting point for a design in some future
technology.

VHDL Description of Combinational Circuits

The gate circuit of the following figure has five signals: A, B, C, D and E.

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The symbol ―<=‖ is the signal assignment operator which indicates that the value
computed on the right-hand side is assigned to the signal on the left side. A
behavioral description of the circuit in the figure is

 Parentheses are used to specify the order of operator execution.

The two assignment statements in the above figure give a dataflow description of
the circuit where it is assumed that each gate has a 5-ns propagation delay. When
the statements given in figure are simulated, the first statement will be evaluated
any time A or B changes, and the second statement will be evaluated any time C or
D changes. Suppose that initially A = 1, and B = C = D = E = 0. If B changes to 1
at time 0, C will change to 1 at time = 5 ns. Then, E will change to 1 at time = 10
ns.

The same circuit can also be described using structural VHDL code. To do so
requires that a two-input AND-gate component and a two-input OR gate
component be declared and defined. Components may be declared and defined
either in a library or within the architecture part of the VHDL code.

The above statements mean the following:

The port map for Gate1 connects A and B to the AND-gate inputs, and it connects
D to the AND-gate output. Since an instantiation statement is concurrent,
whenever A or B changes, these changes go to the Gate1 inputs, and then the
component computes a new value of D. Similarly, the second statement passes
changes in C or D to the Gate2 inputs, and then the component computes a new
value of E.

VHDL signal assignment statements, such as the ones below:

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are examples of concurrent statements.

 The VHDL simulator monitors the right side of each concurrent statement,
and any time a signal changes, the expression on the right side is
immediately re-evaluated. The new value is assigned to the signal on the left
side after an appropriate delay.

If we write:

this implies that the propagation delays are 0 ns. In this case, the simulator will
assume an infinitesimal delay referred to as Δ (delta).

 Unlike a sequential program, the order of the above concurrent statements is

unimportant. If we write:

the simulation results would be exactly the same as before.

 In general, a signal assignment statement has the form

The expression is evaluated when the statement is executed, and the signal on the
left side is scheduled to change after delay. The square brackets indicate that after
delay is optional; they are not part of the statement. If after delay is omitted, then
the signal is scheduled to be updated after a delta delay.

 VHDL is not case sensitive, that is, capital and lower case letters are treated
the same by the compiler and the simulator.
 Signal names and other VHDL identifiers may contain letters, numbers, and
the underscore character ( _ ).An identifier must start with a letter, and it
cannot end with an underscore. Thus, C123 and ab_23 are legal identifiers,
but 1ABC and ABC_ are not.
 Every VHDL statement must be terminated with a semicolon.

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 Spaces, tabs, and carriage returns are treated in the same way. This means
that a VHDL statement can be continued over several lines, or several
statements can be placed on one line.
 In a line of VHDL code, anything following a double dash (--) is treated as a
comment.
 Words such as and, or, and after are reserved words (or keywords) which
have a special meaning to the VHDL compiler.
 Bit values in VHDL are enclosed in single quotes to distinguish them from
integer values.
 A one-dimensional array of bit signals is referred to as a bit-vector.
 VHDL can also model devices with an ideal (transport) delay. Output
changes caused by input changes to a device exhibiting an ideal (transport)
delay of D time units are delayed by D time units, and the output changes
occur even if they occur within D time units. The VHDL signal assignment
statement that models ideal (transport) delay is

VHDL Models for Multiplexers

1. Consider a 2-to-1 multiplexer (MUX) with two data inputs and one
control
input. The MUX output is F = A‘ . I0 + A . I1

The corresponding VHDL statement is

Alternatively, we can represent the MUX by a conditional signal assignment

statement, as

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This statement executes whenever A, I0, or I1 changes. The MUX output is

I0 when A‗0‘, and else it is I1. In the conditional statement, I0, I1, and F
can either be bits or bit-vectors.

2. Two cascaded MUXes can be represented by a conditional signal assignment

statement. The output MUX selects A when E‗1‘; or else it selects the output
of the first MUX, which is B when D‗1‘, or else it is C.

3. Consider a 4-to-1 MUX with four data inputs and two control inputs, A and B.
The control inputs select which one of the data inputs is transmitted to the
output. The logic equation for the 4-to-1 MUX is

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A third way to model the MUX is to use a selected signal assignment statement.
A&B cannot be used in this type of statement, so we first set Sel equal to A&B.
The value of Sel then selects the MUX input that is assigned to F.

The general form of a selected signal assignment statement is

This concurrent statement executes whenever a signal changes in any of the

expressions. First, expression_s is evaluated. If it equals choice1, signal_s is set
equal to expression1; if it equals choice2, signal_s is set equal to expression2; etc.
If all possible choices for the value of expression_s are given, the last line should
be omitted; otherwise, the last line is required. When it is present, if expression_s
is not equal to any of the enumerated choices, signal_s is set equal to
expression_n. The signal_s is updated after the specified delay-time, or after if
the ―after delay-time‖ is omitted.

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VHDL Modules
To write a complete VHDL module, we must declare all of the input and output
signals using an entity declaration, and then specify the internal operation of the
module using an architecture declaration.

Example: Consider the figure:

The entity declaration gives the name ―two_gates‖ to the module. The port
declaration specifies the inputs and outputs to the module. A, B, and D are input
signals of type bit, and E is an output signal of type bit. The architecture is named
―gates‖. The signal C is declared within the architecture because it is an internal
signal. The two concurrent statements that describe the gates are placed between
the keywords begin and end.

When we describe a system in VHDL, we must specify an entity and an

architecture at the top level, and also specify an entity and architecture for each of
the component modules that are part of the system. Each entity declaration
includes a list of interface signals that can be used to connect to other modules or
to the outside world. We will use entity declarations of the form:

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VHDL Program Structure

 The curly brackets indicate zero or more repetitions of the enclosed clause.
 Input signals are of mode in, output signals are of mode out, and bi-
directional signals are of mode inout.
 The optional initial-value is used to initialize the signals on the associated
list; otherwise, the default initial value is used for the specified type.

Example:

Example: Full Adder

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Example: 4-Bit Full Adder

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