Using As: Dean Elsner, Jay Fenlason & Friends
Using As: Dean Elsner, Jay Fenlason & Friends
Version 2.29.51
The Free Software Foundation Inc. thanks The Nice Computer Company of Australia for
loaning Dean Elsner to write the first (Vax) version of as for Project gnu. The proprietors,
management and staff of TNCCA thank FSF for distracting the boss while they got some
work done.
Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Structure of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2 The GNU Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3 Object File Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.4 Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5 Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6 Output (Object) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.7 Error and Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2 Command-Line Options . . . . . . . . . . . . . . . . . . . . . . . 23
2.1 Enable Listings: ‘-a[cdghlns]’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 ‘--alternate’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 ‘-D’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 Work Faster: ‘-f’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 .include Search Path: ‘-I’ path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 Difference Tables: ‘-K’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7 Include Local Symbols: ‘-L’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8 Configuring listing output: ‘--listing’ . . . . . . . . . . . . . . . . . . . . . . . 24
2.9 Assemble in MRI Compatibility Mode: ‘-M’ . . . . . . . . . . . . . . . . . . . . 25
2.10 Dependency Tracking: ‘--MD’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.11 Output Section Padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.12 Name the Object File: ‘-o’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.13 Join Data and Text Sections: ‘-R’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.14 Display Assembly Statistics: ‘--statistics’ . . . . . . . . . . . . . . . . . 27
2.15 Compatible Output: ‘--traditional-format’. . . . . . . . . . . . . . . . 28
2.16 Announce Version: ‘-v’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.17 Control Warnings: ‘-W’, ‘--warn’, ‘--no-warn’,
‘--fatal-warnings’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.18 Generate Object File in Spite of Errors: ‘-Z’. . . . . . . . . . . . . . . . . . 28
3 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 Preprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Whitespace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5 Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6 Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6.1 Character Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6.1.1 Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6.1.2 Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.6.2 Number Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.6.2.1 Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ii Using as
3.6.2.2 Bignums . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.2.3 Flonums . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1 Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 Giving Symbols Other Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3 Symbol Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.4 The Special Dot Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.5 Symbol Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.5.1 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.5.2 Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.3 Symbol Attributes: a.out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.3.1 Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.3.2 Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.4 Symbol Attributes for COFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.4.1 Primary Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.4.2 Auxiliary Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5.5 Symbol Attributes for SOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6 Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1 Empty Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2 Integer Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2.1 Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2.2 Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2.3 Prefix Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2.4 Infix Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7 Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1 .abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.2 .ABORT (COFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.3 .align abs-expr , abs-expr , abs-expr . . . . . . . . . . . . . . . . . . . . . . 49
7.4 .altmacro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.5 .ascii "string ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6 .asciz "string ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.7 .balign[wl] abs-expr , abs-expr , abs-expr . . . . . . . . . . . . . . . . 50
7.8 Bundle directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.8.1 .bundle_align_mode abs-expr . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.8.2 .bundle_lock and .bundle_unlock . . . . . . . . . . . . . . . . . . . . . . 51
7.9 .byte expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.10 CFI directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
iii
8 Object Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.1 gnu Object Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.1.1 Common gnu attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.1.2 MIPS Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.1.3 PowerPC Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.1.4 IBM z Systems Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.2 Defining New Object Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.1.6 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.1.7 Mapping Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.2 Alpha Dependent Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.2.1 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.2.2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.2.3 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.2.3.1 Special Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.2.3.2 Register Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.2.3.3 Relocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.2.4 Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.2.5 Alpha Assembler Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.2.6 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
9.3 ARC Dependent Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.3.1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.3.2 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.3.2.1 Special Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.3.2.2 Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
9.3.3 ARC Machine Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
9.3.4 ARC Assembler Modifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.5 ARC Pre-defined Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.6 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.4 ARM Dependent Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.4.1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.4.2 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.2.1 Instruction Set Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.2.2 Special Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.2.3 Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.4.2.4 ARM relocation generation . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.4.2.5 NEON Alignment Specifiers . . . . . . . . . . . . . . . . . . . . . . . . 114
9.4.3 Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.4.4 ARM Machine Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.4.5 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.4.6 Mapping Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.4.7 Unwinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.5 AVR Dependent Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.5.1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.5.2 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.5.2.1 Special Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.5.2.2 Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.5.2.3 Relocatable Expression Modifiers . . . . . . . . . . . . . . . . . . . 126
9.5.3 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.5.4 Pseudo Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.6 Blackfin Dependent Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.6.1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.6.2 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.6.3 Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7 CR16 Dependent Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.7.1 CR16 Operand Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
vii
11 Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . 359
AS Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Chapter 1: Overview 1
1 Overview
This manual is a user guide to the gnu assembler as.
Here is a brief summary of how to invoke as. For details, see Chapter 2 [Command-Line
Options], page 23.
as [-a[cdghlns][=file ]] [–alternate] [-D]
[–compress-debug-sections] [–nocompress-debug-sections]
[–debug-prefix-map old =new ]
[–defsym sym =val ] [-f] [-g] [–gstabs]
[–gstabs+] [–gdwarf-2] [–gdwarf-sections]
[–help] [-I dir ] [-J]
[-K] [-L] [–listing-lhs-width=NUM ]
[–listing-lhs-width2=NUM ] [–listing-rhs-width=NUM ]
[–listing-cont-lines=NUM ] [–keep-locals]
[–no-pad-sections]
[-o objfile ] [-R]
[–hash-size=NUM ] [–reduce-memory-overheads]
[–statistics]
[-v] [-version] [–version]
[-W] [–warn] [–fatal-warnings] [-w] [-x]
[-Z] [@FILE]
[–sectname-subst] [–size-check=[error|warning]]
[–elf-stt-common=[no|yes]]
[–target-help] [target-options ]
[–|files ...]
[-mcpu=processor [-sirevision ]]
[-mfdpic]
[-mno-fdpic]
[-mnopic]
[–force-long-branches] [–short-branches]
[–strict-direct-mode] [–print-insn-syntax]
[–print-opcodes] [–generate-example]
Target RX options:
[-mlittle-endian|-mbig-endian]
[-m32bit-doubles|-m64bit-doubles]
[-muse-conventional-section-names]
[-msmall-data-limit]
[-mpid]
[-mrelax]
[-mint-register=number]
[-mgcc-abi|-mrx-abi]
[-mregnames|-mno-regnames]
[-mwarn-areg-zero]
@file Read command-line options from file. The options read are inserted in place
of the original @file option. If file does not exist, or cannot be read, then the
option will be treated literally, and not removed.
Options in file are separated by whitespace. A whitespace character may be
included in an option by surrounding the entire option in either single or double
quotes. Any character (including a backslash) may be included by prefixing the
character to be included with a backslash. The file may itself contain additional
@file options; any such options will be processed recursively.
-a[cdghlmns]
Turn on listings, in any of a variety of ways:
-ac omit false conditionals
-ad omit debugging directives
-ag include general information, like as version and options passed
-ah include high-level source
-al include assembly
-am include macro expansions
-an omit forms processing
-as include symbols
=file set the name of the listing file
You may combine these options; for example, use ‘-aln’ for assembly listing
without forms processing. The ‘=file’ option, if used, must be the last one.
By itself, ‘-a’ defaults to ‘-ahls’.
--alternate
Begin in alternate macro mode. See Section 7.4 [.altmacro], page 50.
--compress-debug-sections
Compress DWARF debug sections using zlib with SHF COMPRESSED from
the ELF ABI. The resulting object file may not be compatible with older linkers
and object file utilities. Note if compression would make a given section larger
then it is not compressed.
--compress-debug-sections=none
--compress-debug-sections=zlib
--compress-debug-sections=zlib-gnu
--compress-debug-sections=zlib-gabi
These options control how DWARF debug sections are com-
pressed. ‘--compress-debug-sections=none’ is equivalent to
‘--nocompress-debug-sections’. ‘--compress-debug-sections=zlib’
and ‘--compress-debug-sections=zlib-gabi’ are equivalent to
‘--compress-debug-sections’. ‘--compress-debug-sections=zlib-gnu’
compresses DWARF debug sections using zlib. The debug sections are
Chapter 1: Overview 7
--size-check=error
--size-check=warning
Issue an error or warning for invalid ELF .size directive.
--elf-stt-common=no
--elf-stt-common=yes
These options control whether the ELF assembler should generate common
symbols with the STT_COMMON type. The default can be controlled by a configure
option ‘--enable-elf-stt-common’.
--help Print a summary of the command line options and exit.
--target-help
Print a summary of all target specific options and exit.
-I dir Add directory dir to the search list for .include directives.
-J Don’t warn about signed overflow.
-K Issue warnings when difference tables altered for long displacements.
-L
--keep-locals
Keep (in the symbol table) local symbols. These symbols start with system-
specific local label prefixes, typically ‘.L’ for ELF systems or ‘L’ for traditional
a.out systems. See Section 5.3 [Symbol Names], page 41.
--listing-lhs-width=number
Set the maximum width, in words, of the output data column for an assembler
listing to number.
--listing-lhs-width2=number
Set the maximum width, in words, of the output data column for continuation
lines in an assembler listing to number.
--listing-rhs-width=number
Set the maximum width of an input source line, as displayed in a listing, to
number bytes.
--listing-cont-lines=number
Set the maximum number of lines printed in a listing for a single line of input
to number + 1.
--no-pad-sections
Stop the assembler for padding the ends of output sections to the alignment of
that section. The default is to pad the sections, but this can waste space which
might be needed on targets which have tight memory constraints.
-o objfile
Name the object-file output from as objfile.
-R Fold the data section into the text section.
--hash-size=number
Set the default size of GAS’s hash tables to a prime number close to number.
Increasing this value can reduce the length of time it takes the assembler to
Chapter 1: Overview 9
perform its tasks, at the expense of increasing the assembler’s memory require-
ments. Similarly reducing this value can reduce the memory requirements at
the expense of speed.
--reduce-memory-overheads
This option reduces GAS’s memory requirements, at the expense of making
the assembly processes slower. Currently this switch is a synonym for
‘--hash-size=4051’, but in the future it may have other effects as well.
--sectname-subst
Honor substitution sequences in section names. See [.section name ], page 73.
--statistics
Print the maximum space (in bytes) and total time (in seconds) used by assem-
bly.
--strip-local-absolute
Remove local absolute symbols from the outgoing symbol table.
-v
-version Print the as version.
--version
Print the as version and exit.
-W
--no-warn
Suppress warning messages.
--fatal-warnings
Treat warnings as errors.
--warn Don’t suppress warning messages or treat them as errors.
-w Ignored.
-x Ignored.
-Z Generate an object file even after errors.
-- | files ...
Standard input, or source files to assemble.
See Section 9.1.1 [AArch64 Options], page 90, for the options available when as is con-
figured for the 64-bit mode of the ARM Architecture (AArch64).
See Section 9.2.2 [Alpha Options], page 95, for the options available when as is configured
for an Alpha processor.
The following options are available when as is configured for an ARC processor.
-mcpu=cpu
This option selects the core processor variant.
-EB | -EL Select either big-endian (-EB) or little-endian (-EL) output.
-mcode-density
Enable Code Density extenssion instructions.
10 Using as
The following options are available when as is configured for the ARM processor family.
-mcpu=processor [+extension ...]
Specify which ARM processor variant is the target.
-march=architecture [+extension ...]
Specify which ARM architecture variant is used by the target.
-mfpu=floating-point-format
Select which Floating Point architecture is the target.
-mfloat-abi=abi
Select which floating point ABI is in use.
-mthumb Enable Thumb only instruction decoding.
-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
Select which procedure calling convention is in use.
-EB | -EL Select either big-endian (-EB) or little-endian (-EL) output.
-mthumb-interwork
Specify that the code has been generated with interworking between Thumb
and ARM code in mind.
-mccs Turns on CodeComposer Studio assembly syntax compatibility mode.
-k Specify that PIC code has been generated.
See Section 9.6.1 [Blackfin Options], page 131, for the options available when as is
configured for the Blackfin processor family.
See the info pages for documentation of the CRIS-specific options.
The following options are available when as is configured for a D10V processor.
-O Optimize output by parallelizing instructions.
The following options are available when as is configured for a D30V processor.
-O Optimize output by parallelizing instructions.
-n Warn when nops are generated.
-N Warn when a nop after a 32-bit multiply instruction is generated.
The following options are available when as is configured for the Adapteva EPIPHANY
series.
See Section 9.11.1 [Epiphany Options], page 150, for the options available when as is
configured for an Epiphany processor.
See Section 9.15.1 [i386-Options], page 162, for the options available when as is configured
for an i386 processor.
The following options are available when as is configured for the Intel 80960 processor.
-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
Specify which variant of the 960 architecture is the target.
-b Add code to collect statistics about branches taken.
Chapter 1: Overview 11
-no-relax
Do not alter compare-and-branch instructions for long displacements; error if
necessary.
The following options are available when as is configured for the Ubicom IP2K series.
-mip2022ext
Specifies that the extended IP2022 instructions are allowed.
-mip2022 Restores the default behaviour, which restricts the permitted instructions to
just the basic IP2022 ones.
The following options are available when as is configured for the Renesas M32C and
M16C processors.
-m32c Assemble M32C instructions.
-m16c Assemble M16C instructions (the default).
-relax Enable support for link-time relaxations.
-h-tick-hex
Support H’00 style hex constants in addition to 0x00 style.
The following options are available when as is configured for the Renesas M32R (formerly
Mitsubishi M32R) series.
--m32rx Specify which processor in the M32R family is the target. The default is nor-
mally the M32R, but this option changes it to the M32RX.
--warn-explicit-parallel-conflicts or --Wp
Produce warning messages when questionable parallel constructs are encoun-
tered.
--no-warn-explicit-parallel-conflicts or --Wnp
Do not produce warning messages when questionable parallel constructs are
encountered.
The following options are available when as is configured for the Motorola 68000 series.
-l Shorten references to undefined symbols, to one word instead of two.
-m68000 | -m68008 | -m68010 | -m68020 | -m68030
| -m68040 | -m68060 | -m68302 | -m68331 | -m68332
| -m68333 | -m68340 | -mcpu32 | -m5200
Specify what processor in the 68000 family is the target. The default is normally
the 68020, but this can be changed at configuration time.
-m68881 | -m68882 | -mno-68881 | -mno-68882
The target machine does (or does not) have a floating-point coprocessor. The
default is to assume a coprocessor for 68020, 68030, and cpu32. Although the
basic 68000 is not compatible with the 68881, a combination of the two can
be specified, since it’s possible to do emulation of the coprocessor instructions
with the main processor.
12 Using as
-m68851 | -mno-68851
The target machine does (or does not) have a memory-management unit co-
processor. The default is to assume an MMU for 68020 and up.
See Section 9.31.1 [Nios II Options], page 243, for the options available when as is
configured for an Altera Nios II processor.
For details about the PDP-11 machine dependent features options, see Section 9.33.1
[PDP-11-Options], page 247.
-mpic | -mno-pic
Generate position-independent (or position-dependent) code. The default is
‘-mpic’.
-mall
-mall-extensions
Enable all instruction set extensions. This is the default.
-mno-extensions
Disable all instruction set extensions.
-mextension | -mno-extension
Enable (or disable) a particular instruction set extension.
-mcpu Enable the instruction set extensions supported by a particular CPU, and dis-
able all other extensions.
-mmachine
Enable the instruction set extensions supported by a particular machine model,
and disable all other extensions.
The following options are available when as is configured for a picoJava processor.
-mb Generate “big endian” format output.
-ml Generate “little endian” format output.
See Section 9.36.1 [PRU Options], page 255, for the options available when as is config-
ured for a PRU processor.
The following options are available when as is configured for the Motorola 68HC11 or
68HC12 series.
-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg
Specify what processor is the target. The default is defined by the configuration
option when building the assembler.
--xgate-ramoffset
Instruct the linker to offset RAM addresses from S12X address space into
XGATE address space.
-mshort Specify to use the 16-bit integer ABI.
-mlong Specify to use the 32-bit integer ABI.
-mshort-double
Specify to use the 32-bit double ABI.
Chapter 1: Overview 13
-mlong-double
Specify to use the 64-bit double ABI.
--force-long-branches
Relative branches are turned into absolute ones. This concerns conditional
branches, unconditional branches and branches to a sub routine.
-S | --short-branches
Do not turn relative branches into absolute ones when the offset is out of range.
--strict-direct-mode
Do not turn the direct addressing mode into extended addressing mode when
the instruction does not support direct addressing mode.
--print-insn-syntax
Print the syntax of instruction in case of error.
--print-opcodes
Print the list of instructions with syntax and then exit.
--generate-example
Print an example of instruction for each possible instruction and then exit. This
option is only useful for testing as.
The following options are available when as is configured for the SPARC architecture:
-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
-Av8plus | -Av8plusa | -Av9 | -Av9a
Explicitly select a variant of the SPARC architecture.
‘-Av8plus’ and ‘-Av8plusa’ select a 32 bit environment. ‘-Av9’ and ‘-Av9a’
select a 64 bit environment.
‘-Av8plusa’ and ‘-Av9a’ enable the SPARC V9 instruction set with Ultra-
SPARC extensions.
-xarch=v8plus | -xarch=v8plusa
For compatibility with the Solaris v9 assembler. These options are equivalent
to -Av8plus and -Av8plusa, respectively.
-bump Warn when the assembler switches to another architecture.
The following options are available when as is configured for the ’c54x architecture.
-mfar-mode
Enable extended addressing mode. All addresses and relocations will assume
extended addressing (usually 23 bits).
-mcpu=CPU_VERSION
Sets the CPU version being compiled for.
-merrors-to-file FILENAME
Redirect error output to a file, for broken systems which don’t support such
behaviour in the shell.
The following options are available when as is configured for a MIPS processor.
14 Using as
-G num This option sets the largest size of an object that can be referenced implicitly
with the gp register. It is only accepted for targets that use ECOFF format,
such as a DECstation running Ultrix. The default value is 8.
-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips32r3
-mips32r5
-mips32r6
-mips64
-mips64r2
-mips64r3
-mips64r5
-mips64r6
Generate code for a particular MIPS Instruction Set Architecture
level. ‘-mips1’ is an alias for ‘-march=r3000’, ‘-mips2’ is an alias for
‘-march=r6000’, ‘-mips3’ is an alias for ‘-march=r4000’ and ‘-mips4’ is an
alias for ‘-march=r8000’. ‘-mips5’, ‘-mips32’, ‘-mips32r2’, ‘-mips32r3’,
‘-mips32r5’, ‘-mips32r6’, ‘-mips64’, ‘-mips64r2’, ‘-mips64r3’, ‘-mips64r5’,
and ‘-mips64r6’ correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64
Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA
processors, respectively.
-march=cpu
Generate code for a particular MIPS CPU.
-mtune=cpu
Schedule and tune for a particular MIPS CPU.
-mfix7000
-mno-fix7000
Cause nops to be inserted if the read of the destination register of an mfhi or
mflo instruction occurs in the following two instructions.
-mfix-rm7000
-mno-fix-rm7000
Cause nops to be inserted if a dmult or dmultu instruction is followed by a load
instruction.
Chapter 1: Overview 15
-mdebug
-no-mdebug
Cause stabs-style debugging output to go into an ECOFF-style .mdebug section
instead of the standard ELF .stabs sections.
-mpdr
-mno-pdr Control generation of .pdr sections.
-mgp32
-mfp32 The register sizes are normally inferred from the ISA and ABI, but these flags
force a certain group of registers to be treated as 32 bits wide at all times.
‘-mgp32’ controls the size of general-purpose registers and ‘-mfp32’ controls the
size of floating-point registers.
-mgp64
-mfp64 The register sizes are normally inferred from the ISA and ABI, but these flags
force a certain group of registers to be treated as 64 bits wide at all times.
‘-mgp64’ controls the size of general-purpose registers and ‘-mfp64’ controls the
size of floating-point registers.
-mfpxx The register sizes are normally inferred from the ISA and ABI, but using this
flag in combination with ‘-mabi=32’ enables an ABI variant which will operate
correctly with floating-point registers which are 32 or 64 bits wide.
-modd-spreg
-mno-odd-spreg
Enable use of floating-point operations on odd-numbered single-precision regis-
ters when supported by the ISA. ‘-mfpxx’ implies ‘-mno-odd-spreg’, otherwise
the default is ‘-modd-spreg’.
-mips16
-no-mips16
Generate code for the MIPS 16 processor. This is equivalent to putting .module
mips16 at the start of the assembly file. ‘-no-mips16’ turns off this option.
-mmips16e2
-mno-mips16e2
Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to
putting .module mips16e2 at the start of the assembly file. ‘-mno-mips16e2’
turns off this option.
-mmicromips
-mno-micromips
Generate code for the microMIPS processor. This is equivalent to putting
.module micromips at the start of the assembly file. ‘-mno-micromips’ turns
off this option. This is equivalent to putting .module nomicromips at the start
of the assembly file.
-msmartmips
-mno-smartmips
Enables the SmartMIPS extension to the MIPS32 instruction set. This is
equivalent to putting .module smartmips at the start of the assembly file.
‘-mno-smartmips’ turns off this option.
16 Using as
-mips3d
-no-mips3d
Generate code for the MIPS-3D Application Specific Extension. This tells the
assembler to accept MIPS-3D instructions. ‘-no-mips3d’ turns off this option.
-mdmx
-no-mdmx Generate code for the MDMX Application Specific Extension. This tells the
assembler to accept MDMX instructions. ‘-no-mdmx’ turns off this option.
-mdsp
-mno-dsp Generate code for the DSP Release 1 Application Specific Extension. This tells
the assembler to accept DSP Release 1 instructions. ‘-mno-dsp’ turns off this
option.
-mdspr2
-mno-dspr2
Generate code for the DSP Release 2 Application Specific Extension. This
option implies ‘-mdsp’. This tells the assembler to accept DSP Release 2 in-
structions. ‘-mno-dspr2’ turns off this option.
-mdspr3
-mno-dspr3
Generate code for the DSP Release 3 Application Specific Extension. This
option implies ‘-mdsp’ and ‘-mdspr2’. This tells the assembler to accept DSP
Release 3 instructions. ‘-mno-dspr3’ turns off this option.
-mmsa
-mno-msa Generate code for the MIPS SIMD Architecture Extension. This tells the as-
sembler to accept MSA instructions. ‘-mno-msa’ turns off this option.
-mxpa
-mno-xpa Generate code for the MIPS eXtended Physical Address (XPA) Extension. This
tells the assembler to accept XPA instructions. ‘-mno-xpa’ turns off this option.
-mmt
-mno-mt Generate code for the MT Application Specific Extension. This tells the as-
sembler to accept MT instructions. ‘-mno-mt’ turns off this option.
-mmcu
-mno-mcu Generate code for the MCU Application Specific Extension. This tells the
assembler to accept MCU instructions. ‘-mno-mcu’ turns off this option.
-minsn32
-mno-insn32
Only use 32-bit instruction encodings when generating code for the microMIPS
processor. This option inhibits the use of any 16-bit instructions. This is equiv-
alent to putting .set insn32 at the start of the assembly file. ‘-mno-insn32’
turns off this option. This is equivalent to putting .set noinsn32 at the start of
the assembly file. By default ‘-mno-insn32’ is selected, allowing all instructions
to be used.
Chapter 1: Overview 17
--construct-floats
--no-construct-floats
The ‘--no-construct-floats’ option disables the construction of double width
floating point constants by loading the two halves of the value into the two
single width floating point registers that make up the double width register.
By default ‘--construct-floats’ is selected, allowing construction of these
floating point constants.
--relax-branch
--no-relax-branch
The ‘--relax-branch’ option enables the relaxation of out-of-range branches.
By default ‘--no-relax-branch’ is selected, causing any out-of-range branches
to produce an error.
-mignore-branch-isa
-mno-ignore-branch-isa
Ignore branch checks for invalid transitions between ISA modes. The semantics
of branches does not provide for an ISA mode switch, so in most cases the ISA
mode a branch has been encoded for has to be the same as the ISA mode of
the branch’s target label. Therefore GAS has checks implemented that verify
in branch assembly that the two ISA modes match. ‘-mignore-branch-isa’
disables these checks. By default ‘-mno-ignore-branch-isa’ is selected, caus-
ing any invalid branch requiring a transition between ISA modes to produce an
error.
-mnan=encoding
Select between the IEEE 754-2008 (‘-mnan=2008’) or the legacy
(‘-mnan=legacy’) NaN encoding format. The latter is the default.
--emulation=name
This option was formerly used to switch between ELF and ECOFF output on
targets like IRIX 5 that supported both. MIPS ECOFF support was removed in
GAS 2.24, so the option now serves little purpose. It is retained for backwards
compatibility.
The available configuration names are: ‘mipself’, ‘mipslelf’ and ‘mipsbelf’.
Choosing ‘mipself’ now has no effect, since the output is always ELF.
‘mipslelf’ and ‘mipsbelf’ select little- and big-endian output respectively,
but ‘-EL’ and ‘-EB’ are now the preferred options instead.
-nocpp as ignores this option. It is accepted for compatibility with the native tools.
--trap
--no-trap
--break
--no-break
Control how to deal with multiplication overflow and division by zero. ‘--trap’
or ‘--no-break’ (which are synonyms) take a trap exception (and only work
for Instruction Set Architecture level 2 and higher); ‘--break’ or ‘--no-trap’
(also synonyms, and the default) take a break exception.
18 Using as
-n When this option is used, as will issue a warning every time it generates a nop
instruction from a macro.
The following options are available when as is configured for an MCore processor.
-jsri2bsr
-nojsri2bsr
Enable or disable the JSRI to BSR transformation. By default this is enabled.
The command line option ‘-nojsri2bsr’ can be used to disable it.
-sifilter
-nosifilter
Enable or disable the silicon filter behaviour. By default this is disabled. The
default can be overridden by the ‘-sifilter’ command line option.
-relax Alter jump instructions for long displacements.
-mcpu=[210|340]
Select the cpu type on the target hardware. This controls which instructions
can be assembled.
-EB Assemble for a big endian target.
-EL Assemble for a little endian target.
See Section 9.25.1 [Meta Options], page 209, for the options available when as is config-
ured for a Meta processor.
See the info pages for documentation of the MMIX-specific options.
See Section 9.30.1 [NDS32 Options], page 238, for the options available when as is
configured for a NDS32 processor.
See Section 9.35.1 [PowerPC-Opts], page 252, for the options available when as is con-
figured for a PowerPC processor.
See Section 9.38.1 [RISC-V-Opts], page 259, for the options available when as is config-
ured for a RISC-V processor.
See the info pages for documentation of the RX-specific options.
The following options are available when as is configured for the s390 processor family.
-m31
-m64 Select the word size, either 31/32 bits or 64 bits.
-mesa
-mzarch Select the architecture mode, either the Enterprise System Architecture (esa)
or the z/Architecture mode (zarch).
-march=processor
Specify which s390 processor variant is the target, ‘g5’ (or ‘arch3’), ‘g6’,
‘z900’ (or ‘arch5’), ‘z990’ (or ‘arch6’), ‘z9-109’, ‘z9-ec’ (or ‘arch7’), ‘z10’
(or ‘arch8’), ‘z196’ (or ‘arch9’), ‘zEC12’ (or ‘arch10’), ‘z13’ (or ‘arch11’), or
‘z14’ (or ‘arch12’).
-mregnames
-mno-regnames
Allow or disallow symbolic names for registers.
Chapter 1: Overview 19
-mwarn-areg-zero
Warn whenever the operand for a base or index register has been specified but
evaluates to zero.
See Section 9.46.1 [TIC6X Options], page 308, for the options available when as is
configured for a TMS320C6000 processor.
See Section 9.47.1 [TILE-Gx Options], page 311, for the options available when as is
configured for a TILE-Gx processor.
See Section 9.51.1 [Visium Options], page 332, for the options available when as is
configured for a Visium processor.
See Section 9.55.1 [Xtensa Options], page 338, for the options available when as is
configured for an Xtensa processor.
The following options are available when as is configured for a Z80 family processor.
-z80 Assemble for Z80 processor.
-r800 Assemble for R800 processor.
-ignore-undocumented-instructions
-Wnud Assemble undocumented Z80 instructions that also work on R800 without warn-
ing.
-ignore-unportable-instructions
-Wnup Assemble all undocumented Z80 instructions without warning.
-warn-undocumented-instructions
-Wud Issue a warning for undocumented Z80 instructions that also work on R800.
-warn-unportable-instructions
-Wup Issue a warning for undocumented Z80 instructions that do not work on R800.
-forbid-undocumented-instructions
-Fud Treat all undocumented instructions as errors.
-forbid-unportable-instructions
-Fup Treat undocumented Z80 instructions that do not work on R800 as errors.
You give as a command line that has zero or more input file names. The input files are
read (from left file name to right). A command line argument (in any position) that has no
special meaning is taken to be an input file name.
If you give as no file names it attempts to read one input file from the as standard input,
which is normally your terminal. You may have to type ctl-D to tell as there is no more
program to assemble.
Use ‘--’ if you need to explicitly name the standard input file in your command line.
If the source is empty, as produces a small, empty object file.
.file 2 "bar.c"
error_assembler_source
.file "foo.c"
.line 30
error_c_source
produces this output:
Assembler messages:
asm.s:2: Error: no such instruction: ‘error_assembler_source’
foo.c:31: Error: no such instruction: ‘error_c_source’
Error messages have the format
file_name:NNN:FATAL:Error Message Text
The file name and line number are derived as for warning messages. The actual message
text may be rather less explanatory because many of them aren’t supposed to happen.
Chapter 2: Command-Line Options 23
2 Command-Line Options
This chapter describes command-line options available in all versions of the gnu assembler;
see Chapter 9 [Machine Dependencies], page 89, for options specific to particular machine
architectures.
If you are invoking as via the gnu C compiler, you can use the ‘-Wa’ option to pass
arguments through to the assembler. The assembler arguments must be separated from
each other (and the ‘-Wa’) by commas. For example:
gcc -c -g -O -Wa,-alh,-L file.c
This passes two options to the assembler: ‘-alh’ (emit a listing to standard output with
high-level and assembly source) and ‘-L’ (retain local symbols in the symbol table).
Usually you do not need to use this ‘-Wa’ mechanism, since many compiler command-
line options are automatically passed to the assembler by the compiler. (You can call the
gnu compiler driver with the ‘-v’ option to see precisely what options it passes to each
compilation pass, including the assembler.)
2.2 ‘--alternate’
Begin in alternate macro mode, see Section 7.4 [.altmacro], page 50.
24 Using as
2.3 ‘-D’
This option has no effect whatsoever, but it is accepted to make it more likely that scripts
written for other assemblers also work with as.
--listing-lhs-width=‘number’
Sets the maximum width, in words, of the first line of the hex byte dump. This
dump appears on the left hand side of the listing output.
--listing-lhs-width2=‘number’
Sets the maximum width, in words, of any further lines of the hex byte dump
for a given input source line. If this value is not specified, it defaults to being
the same as the value specified for ‘--listing-lhs-width’. If neither switch
is used the default is to one.
--listing-rhs-width=‘number’
Sets the maximum width, in characters, of the source line that is displayed
alongside the hex dump. The default value for this parameter is 100. The
source line is displayed on the right hand side of the listing output.
--listing-cont-lines=‘number’
Sets the maximum number of continuation lines of hex dump that will be dis-
played for a given single line of source input. The default value is 4.
• ORG pseudo-op
The m68k MRI ORG pseudo-op begins an absolute section at a given address. This
differs from the usual as .org pseudo-op, which changes the location within the current
section. Absolute sections are not supported by other object file formats. The address
of a section may be assigned within a linker script.
There are some other features of the MRI assembler which are not supported by as,
typically either because they are difficult or because they seem of little consequence. Some
of these may be supported in future releases.
• EBCDIC strings
EBCDIC strings are not supported.
• packed binary coded decimal
Packed binary coded decimal is not supported. This means that the DC.P and DCB.P
pseudo-ops are not supported.
• FEQU pseudo-op
The m68k FEQU pseudo-op is not supported.
• NOOBJ pseudo-op
The m68k NOOBJ pseudo-op is not supported.
• OPT branch control options
The m68k OPT branch control options—B, BRS, BRB, BRL, and BRW—are ignored. as
automatically relaxes all branches, whether forward or backward, to an appropriate
size, so these options serve no purpose.
• OPT list control options
The following m68k OPT list control options are ignored: C, CEX, CL, CRE, E, G, I, M,
MEX, MC, MD, X.
• other OPT options
The following m68k OPT options are ignored: NEST, O, OLD, OP, P, PCO, PCR, PCS, R.
• OPT D option is default
The m68k OPT D option is the default, unlike the MRI assembler. OPT NOD may be used
to turn it off.
• XREF pseudo-op.
The m68k XREF pseudo-op is ignored.
• .debug pseudo-op
The i960 .debug pseudo-op is not supported.
• .extended pseudo-op
The i960 .extended pseudo-op is not supported.
• .list pseudo-op.
The various options of the i960 .list pseudo-op are not supported.
• .optimize pseudo-op
The i960 .optimize pseudo-op is not supported.
• .output pseudo-op
The i960 .output pseudo-op is not supported.
Chapter 2: Command-Line Options 27
• .setreal pseudo-op
The i960 .setreal pseudo-op is not supported.
3 Syntax
This chapter describes the machine-independent syntax allowed in a source file. as syntax is
similar to what many other assemblers use; it is inspired by the BSD 4.2 assembler, except
that as does not assemble Vax bit-fields.
3.1 Preprocessing
The as internal preprocessor:
• adjusts and removes extra whitespace. It leaves one space or tab before the keywords
on a line, and turns any other whitespace on the line into a single space.
• removes all comments, replacing them with a single space, or an appropriate number
of newlines.
• converts character constants into the appropriate numeric values.
It does not do macro processing, include file handling, or anything else you may get
from your C compiler’s preprocessor. You can do include file processing with the .include
directive (see Section 7.43 [.include], page 62). You can use the gnu C compiler driver
to get other “CPP” style preprocessing by giving the input file a ‘.S’ suffix. See Section
“Options Controlling the Kind of Output” in Using GNU CC.
Excess whitespace, comments, and character constants cannot be used in the portions
of the input text that are not preprocessed.
If the first line of an input file is #NO_APP or if you use the ‘-f’ option, whitespace
and comments are not removed from the input file. Within an input file, you can ask for
whitespace and comment removal in specific portions of the by putting a line that says
#APP before the text that may contain whitespace or comments, and putting a line that
says #NO_APP after this text. This feature is mainly intend to support asm statements in
compilers whose output is otherwise free of comments and whitespace.
3.2 Whitespace
Whitespace is one or more blanks or tabs, in any order. Whitespace is used to separate
symbols, and to make programs neater for people to read. Unless within character constants
(see Section 3.6.1 [Character Constants], page 31), any whitespace means the same as
exactly one space.
3.3 Comments
There are two ways of rendering comments to as. In both cases the comment is equivalent
to one space.
Anything from ‘/*’ through the next ‘*/’ is a comment. This means you may not nest
these comments.
/*
The only way to include a newline (’\n’) in a comment
is to use this sort of comment.
*/
Anything from a line comment character up to the next newline is considered a comment
and is ignored. The line comment character is target specific, and some targets multiple
comment characters. Some targets also have line comment characters that only work if they
are the first character on a line. Some targets use a sequence of two characters to introduce
a line comment. Some targets can also change their line comment characters depending
upon command line options that have been used. For more details see the Syntax section
in the documentation for individual targets.
If the line comment character is the hash sign (‘#’) then it still has the special ability to
enable and disable preprocessing (see Section 3.1 [Preprocessing], page 29) and to specify
logical line numbers:
To be compatible with past assemblers, lines that begin with ‘#’ have a special inter-
pretation. Following the ‘#’ should be an absolute expression (see Chapter 6 [Expressions],
page 45): the logical line number of the next line. Then a string (see Section 3.6.1.1 [Strings],
page 31) is allowed: if present it is a new logical file name. The rest of the line, if any,
should be whitespace.
If the first non-whitespace characters on the line are not numeric, the line is ignored.
(Just like a comment.)
# This is an ordinary comment.
# 42-6 "new_file_name" # New logical file name
# This is logical line # 36.
This feature is deprecated, and may disappear from future versions of as.
3.4 Symbols
A symbol is one or more characters chosen from the set of all letters (both upper and
lower case), digits and the three characters ‘_.$’. On most machines, you can also use $
in symbol names; exceptions are noted in Chapter 9 [Machine Dependencies], page 89. No
symbol may begin with a digit. Case is significant. There is no length limit; all characters
are significant. Multibyte characters are supported. Symbols are delimited by characters
not in that set, or by the beginning of a file (since the source program must end with a
newline, the end of a file is not a possible symbol delimiter). See Chapter 5 [Symbols],
page 41.
Symbol names may also be enclosed in double quote " characters. In such cases any
characters are allowed, except for the NUL character. If a double quote character is to be
included in the symbol name it must be preceeded by a backslash \ character.
3.5 Statements
A statement ends at a newline character (‘\n’) or a line separator character. The line
separator character is target specific and described in the Syntax section of each target’s
documentation. Not all targets support a line separator character. The newline or line
separator character is considered to be part of the preceding statement. Newlines and
separators within character constants are an exception: they do not end statements.
It is an error to end any statement with end-of-file: the last character of any input file
should be a newline.
An empty statement is allowed, and may include whitespace. It is ignored.
Chapter 3: Syntax 31
A statement begins with zero or more labels, optionally followed by a key symbol which
determines what kind of statement it is. The key symbol determines the syntax of the rest
of the statement. If the symbol begins with a dot ‘.’ then the statement is an assembler
directive: typically valid for any computer. If the symbol begins with a letter the statement
is an assembly language instruction: it assembles into a machine language instruction.
Different versions of as for different computers recognize different instructions. In fact,
the same symbol may represent a different instruction in a different computer’s assembly
language.
A label is a symbol immediately followed by a colon (:). Whitespace before a label or
after a colon is permitted, but you may not have whitespace between a label’s symbol and
its colon. See Section 5.1 [Labels], page 41.
For HPPA targets, labels need not be immediately followed by a colon, but the definition
of a label must begin in column zero. This also implies that only one label may be defined
on each line.
label: .directive followed by something
another_label: # This is an empty statement.
instruction operand_1, operand_2, ...
3.6 Constants
A constant is a number, written so that its value is known by inspection, without knowing
any context. Like this:
.byte 74, 0112, 092, 0x4A, 0X4a, ’J, ’\J # All the same value.
.ascii "Ring the bell\7" # A string constant.
.octa 0x123456789abcdef0123456789ABCDEF0 # A bignum.
.float 0f-314159265358979323846264338327\
95028841971.693993751E-40 # - pi, a flonum.
3.6.1.1 Strings
A string is written between double-quotes. It may contain double-quotes or null characters.
The way to get special characters into a string is to escape these characters: precede them
with a backslash ‘\’ character. For example ‘\\’ represents one backslash: the first \ is
an escape which tells as to interpret the second character literally as a backslash (which
prevents as from recognizing the second \ as an escape character). The complete list of
escapes follows.
\b Mnemonic for backspace; for ASCII this is octal code 010.
backslash-f
Mnemonic for FormFeed; for ASCII this is octal code 014.
\n Mnemonic for newline; for ASCII this is octal code 012.
\r Mnemonic for carriage-Return; for ASCII this is octal code 015.
32 Using as
\t Mnemonic for horizontal Tab; for ASCII this is octal code 011.
\ digit digit digit
An octal character code. The numeric code is 3 octal digits. For compatibility
with other Unix systems, 8 and 9 are accepted as digits: for example, \008 has
the value 010, and \009 the value 011.
\x hex-digits...
A hex character code. All trailing hex digits are combined. Either upper or
lower case x works.
\\ Represents one ‘\’ character.
\" Represents one ‘"’ character. Needed in strings to represent this character,
because an unescaped ‘"’ would end the string.
\ anything-else
Any other character when escaped by \ gives a warning, but assembles as if the
‘\’ was not present. The idea is that if you used an escape sequence you clearly
didn’t want the literal interpretation of the following character. However as
has no other interpretation, so as knows it is giving you the wrong code and
warns you of the fact.
Which characters are escapable, and what those escapes represent, varies widely among
assemblers. The current set is what we think the BSD 4.2 assembler recognizes, and is
a subset of what most C compilers recognize. If you are in doubt, do not use an escape
sequence.
3.6.1.2 Characters
A single character may be written as a single quote immediately followed by that character.
Some backslash escapes apply to characters, \b, \f, \n, \r, \t, and \" with the same
meaning as for strings, plus \’ for a single quote. So if you want to write the character
backslash, you must write ’\\ where the first \ escapes the second \. As you can see, the
quote is an acute accent, not a grave accent. A newline immediately following an acute
accent is taken as a literal character and does not count as the end of a statement. The
value of a character constant in a numeric expression is the machine’s byte-wide code for
that character. as assumes your character code is ASCII: ’A means 65, ’B means 66, and
so on.
3.6.2.1 Integers
A binary integer is ‘0b’ or ‘0B’ followed by zero or more of the binary digits ‘01’.
An octal integer is ‘0’ followed by zero or more of the octal digits (‘01234567’).
A decimal integer starts with a non-zero digit followed by zero or more digits
(‘0123456789’).
Chapter 3: Syntax 33
A hexadecimal integer is ‘0x’ or ‘0X’ followed by one or more hexadecimal digits chosen
from ‘0123456789abcdefABCDEF’.
Integers have the usual values. To denote a negative integer, use the prefix operator ‘-’
discussed under expressions (see Section 6.2.3 [Prefix Operators], page 45).
3.6.2.2 Bignums
A bignum has the same syntax and semantics as an integer except that the number (or its
negative) takes more than 32 bits to represent in binary. The distinction is made because
in some places integers are permitted while bignums are not.
3.6.2.3 Flonums
A flonum represents a floating point number. The translation is indirect: a decimal floating
point number from the text is converted by as to a generic binary floating point number
of more than sufficient precision. This generic floating point number is converted to a
particular computer’s floating point format (or formats) by a portion of as specialized to
that computer.
A flonum is written by writing (in order)
• The digit ‘0’. (‘0’ is optional on the HPPA.)
• A letter, to tell as the rest of the number is a flonum. e is recommended. Case is not
important.
On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the letter must
be one of the letters ‘DFPRSX’ (in upper or lower case).
On the ARC, the letter must be one of the letters ‘DFRS’ (in upper or lower case).
On the Intel 960 architecture, the letter must be one of the letters ‘DFT’ (in upper or
lower case).
On the HPPA architecture, the letter must be ‘E’ (upper case only).
• An optional sign: either ‘+’ or ‘-’.
• An optional integer part: zero or more decimal digits.
• An optional fractional part: ‘.’ followed by zero or more decimal digits.
• An optional exponent, consisting of:
• An ‘E’ or ‘e’.
• Optional sign: either ‘+’ or ‘-’.
• One or more decimal digits.
At least one of the integer part or the fractional part must be present. The floating point
number has the usual base-10 value.
as does all processing using integers. Flonums are computed independently of any
floating point hardware in the computer running as.
Chapter 4: Sections and Relocation 35
4.1 Background
Roughly, a section is a range of addresses, with no gaps; all data “in” those addresses is
treated the same for some particular purpose. For example there may be a “read only”
section.
The linker ld reads many object files (partial programs) and combines their contents to
form a runnable program. When as emits an object file, the partial program is assumed to
start at address 0. ld assigns the final addresses for the partial program, so that different
partial programs do not overlap. This is actually an oversimplification, but it suffices to
explain how as uses sections.
ld moves blocks of bytes of your program to their run-time addresses. These blocks
slide to their run-time addresses as rigid units; their length does not change and neither
does the order of bytes within them. Such a rigid unit is called a section. Assigning run-
time addresses to sections is called relocation. It includes the task of adjusting mentions of
object-file addresses so they refer to the proper run-time addresses. For the H8/300, and for
the Renesas / SuperH SH, as pads sections if needed to ensure they end on a word (sixteen
bit) boundary.
An object file written by as has at least three sections, any of which may be empty.
These are named text, data and bss sections.
When it generates COFF or ELF output, as can also generate whatever other named
sections you specify using the ‘.section’ directive (see Section 7.78 [.section], page 72).
If you do not use any directives that place output in the ‘.text’ or ‘.data’ sections, these
sections still exist, but are empty.
When as generates SOM or ELF output for the HPPA, as can also generate what-
ever other named sections you specify using the ‘.space’ and ‘.subspace’ directives. See
HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001) for details on
the ‘.space’ and ‘.subspace’ assembler directives.
Additionally, as uses different names for the standard text, data, and bss sections
when generating SOM output. Program text is placed into the ‘$CODE$’ section, data
into ‘$DATA$’, and BSS into ‘$BSS$’.
Within the object file, the text section starts at address 0, the data section follows, and
the bss section follows the data section.
When generating either SOM or ELF output files on the HPPA, the text section starts
at address 0, the data section at address 0x4000000, and the bss section follows the data
section.
To let ld know which data changes when the sections are relocated, and how to change
that data, as also writes to the object file details of the relocation needed. To perform
relocation ld must know, each time an address in the object file is mentioned:
• Where in the object file is the beginning of this reference to an address?
• How long (in bytes) is this reference?
• Which section does the address refer to? What is the numeric value of
(address) − (start-address of section)?
36 Using as
absolute section
Address 0 of this section is always “relocated” to runtime address 0. This
is useful if you want to refer to an address that ld must not change when
relocating. In this sense we speak of absolute addresses being “unrelocatable”:
they do not change during relocation.
undefined section
This “section” is a catch-all for address references to objects not in the preceding
sections.
An idealized example of three relocatable sections follows. The example uses the tradi-
tional section names ‘.text’ and ‘.data’. Memory addresses are on the horizontal axis.
4.4 Sub-Sections
Assembled bytes conventionally fall into two sections: text and data. You may have separate
groups of data in named sections that you want to end up near to each other in the object
file, even though they are not contiguous in the assembler source. as allows you to use
subsections for this purpose. Within each section, there can be numbered subsections with
values from 0 to 8192. Objects assembled into the same subsection go into the object file
38 Using as
together with other objects in the same subsection. For example, a compiler might want
to store constants in the text section, but might not want to have them interspersed with
the program being assembled. In this case, the compiler could issue a ‘.text 0’ before each
section of code being output, and a ‘.text 1’ before each group of constants being output.
Subsections are optional. If you do not use subsections, everything goes in subsection
number zero.
Each subsection is zero-padded up to a multiple of four bytes. (Subsections may be
padded a different amount on different flavors of as.)
Subsections appear in your object file in numeric order, lowest numbered to highest.
(All this to be compatible with other people’s assemblers.) The object file contains no
representation of subsections; ld and other programs that manipulate object files see no
trace of them. They just see all your text subsections as a text section, and all your data
subsections as a data section.
To specify which subsection you want subsequent statements assembled into, use a nu-
meric argument to specify it, in a ‘.text expression ’ or a ‘.data expression ’ statement.
When generating COFF output, you can also use an extra subsection argument with arbi-
trary named sections: ‘.section name , expression ’. When generating ELF output, you
can also use the .subsection directive (see Section 7.89 [SubSection], page 78) to specify
a subsection: ‘.subsection expression ’. Expression should be an absolute expression
(see Chapter 6 [Expressions], page 45). If you just say ‘.text’ then ‘.text 0’ is assumed.
Likewise ‘.data’ means ‘.data 0’. Assembly begins in text 0. For instance:
.text 0 # The default subsection is text 0 anyway.
.ascii "This lives in the first text subsection. *"
.text 1
.ascii "But this lives in the second text subsection."
.data 0
.ascii "This lives in the data section,"
.ascii "in the first data subsection."
.text 0
.ascii "This lives in the first text section,"
.ascii "immediately following the asterisk (*)."
Each section has a location counter incremented by one for every byte assembled into
that section. Because subsections are merely a convenience restricted to as there is no
concept of a subsection location counter. There is no way to directly manipulate a location
counter—but the .align directive changes it, and any label definition captures its current
value. The location counter of the section where statements are being assembled is said to
be the active location counter.
When assembling for a target which supports multiple sections, such as ELF or COFF,
you may switch into the .bss section and define symbols as usual; see Section 7.78
[.section], page 72. You may only assemble zero values into the section. Typically the
section will only contain symbol definitions and .skip directives (see Section 7.83 [.skip],
page 77).
Chapter 5: Symbols 41
5 Symbols
Symbols are a central concept: the programmer uses symbols to name things, the linker
uses symbols to link, and the debugger uses symbols to debug.
Warning: as does not place symbols in the object file in the same order they
were declared. This may break some debuggers.
5.1 Labels
A label is written as a symbol immediately followed by a colon ‘:’. The symbol then
represents the current value of the active location counter, and is, for example, a suitable
instruction operand. You are warned if you use the same symbol to represent two different
locations: the first definition overrides any other definitions.
On the HPPA, the usual form for a label need not be immediately followed by a colon,
but instead must start in column zero. Only one label may be defined on a single line.
To work around this, the HPPA version of as also provides a special directive .label for
defining labels more flexibly.
Local symbols are defined and used within the assembler, but they are normally not
saved in object files. Thus, they are not visible when debugging. You may use the ‘-L’
option (see Section 2.7 [Include Local Symbols], page 24) to retain the local symbols in the
object files.
Local Labels
Local labels are different from local symbols. Local labels help compilers and programmers
use names temporarily. They create symbols which are guaranteed to be unique over the
entire scope of the input source code and which can be referred to by a simple notation.
To define a local label, write a label of the form ‘N:’ (where N represents any non-negative
integer). To refer to the most recent previous definition of that label write ‘Nb’, using the
same number as when you defined the label. To refer to the next definition of a local label,
write ‘Nf’. The ‘b’ stands for “backwards” and the ‘f’ stands for “forwards”.
There is no restriction on how you can use these labels, and you can reuse them too. So
that it is possible to repeatedly define the same local label (using the same number ‘N’),
although you can only refer to the most recently defined local label of that number (for a
backwards reference) or the next definition of a specific local label for a forward reference.
It is also worth noting that the first 10 local labels (‘0:’. . . ‘9:’) are implemented in a slightly
more efficient manner than the others.
Here is an example:
1: branch 1f
2: branch 1b
1: branch 2f
2: branch 1b
Which is the equivalent of:
label_1: branch label_3
label_2: branch label_1
label_3: branch label_4
label_4: branch label_3
Local label names are only a notational device. They are immediately transformed into
more conventional symbol names before the assembler uses them. The symbol names are
stored in the symbol table, appear in error messages, and are optionally emitted to the
object file. The names are constructed using these parts:
local label prefix
All local symbols begin with the system-specific local label prefix. Normally
both as and ld forget symbols that start with the local label prefix. These
labels are used for symbols you are never intended to see. If you use the ‘-L’
option then as retains these symbols in the object file. If you also instruct ld
to retain these symbols, you may use them in debugging.
number This is the number that was used in the local label definition. So if the label is
written ‘55:’ then the number is ‘55’.
C-B This unusual character is included so you do not accidentally invent a symbol
of the same name. The character has ASCII value of ‘\002’ (control-B).
ordinal number
This is a serial number to keep the labels distinct. The first definition of ‘0:’
gets the number ‘1’. The 15th definition of ‘0:’ gets the number ‘15’, and so on.
Chapter 5: Symbols 43
Likewise the first definition of ‘1:’ gets the number ‘1’ and its 15th definition
gets ‘15’ as well.
So for example, the first 1: may be named .L1C-B1, and the 44th 3: may be named
.L3C-B44.
5.5.1 Value
The value of a symbol is (usually) 32 bits. For a symbol which labels a location in the
text, data, bss or absolute sections the value is the number of addresses from the start of
that section to the label. Naturally for text, data and bss sections the value of a symbol
changes as ld changes section base addresses during linking. Absolute symbols’ values do
not change during linking: that is why they are called absolute.
The value of an undefined symbol is treated in a special way. If it is 0 then the symbol
is not defined in this assembler source file, and ld tries to determine its value from other
files linked into the same program. You make this kind of symbol simply by mentioning a
symbol name without defining it. A non-zero value represents a .comm common declaration.
The value is how much common storage to reserve, in bytes (addresses). The symbol refers
to the first address of the allocated storage.
44 Using as
5.5.2 Type
The type attribute of a symbol contains relocation (section) information, any flag settings
indicating that a symbol is external, and (optionally), other information for linkers and
debuggers. The exact format depends on the object-code output format in use.
5.5.3.2 Other
This is an arbitrary 8-bit value. It means nothing to as.
6 Expressions
An expression specifies an address or numeric value. Whitespace may precede and/or follow
an expression.
The result of an expression must be an absolute number, or else an offset into a particular
section. If an expression is not absolute, and there is not enough information when as sees
the expression to know its section, a second pass over the source program might be necessary
to interpret the expression—but the second pass is currently not implemented. as aborts
with an error message in this situation.
6.2.1 Arguments
Arguments are symbols, numbers or subexpressions. In other contexts arguments are some-
times called “arithmetic operands”. In this manual, to avoid confusing them with the
“instruction operands” of the machine language, we use the term “argument” to refer to
parts of expressions only, reserving the word “operand” to refer only to machine instruction
operands.
Symbols are evaluated to yield {section NNN } where section is one of text, data, bss,
absolute, or undefined. NNN is a signed, 2’s complement 32 bit integer.
Numbers are usually integers.
A number can be a flonum or bignum. In this case, you are warned that only the low
order 32 bits are used, and as pretends these 32 bits are an integer. You may write integer-
manipulating instructions that act on exotic constants, compatible with other assemblers.
Subexpressions are a left parenthesis ‘(’ followed by an integer expression, followed by a
right parenthesis ‘)’; or a prefix operator followed by an argument.
6.2.2 Operators
Operators are arithmetic functions, like + or %. Prefix operators are followed by an argu-
ment. Infix operators appear between their arguments. Operators may be preceded and/or
followed by whitespace.
|| Logical Or.
These two logical operations can be used to combine the results of sub
expressions. Note, unlike the comparison operators a true result returns a
value of 1 but a false results does still return 0. Also note that the logical
or operator has a slightly lower precedence than logical and.
In short, it’s only meaningful to add or subtract the offsets in an address; you can only
have a defined section in one of the two arguments.
Chapter 7: Assembler Directives 49
7 Assembler Directives
All assembler directives have names that begin with a period (‘.’). The names are case
insensitive for most targets, and usually written in lower case.
This chapter discusses directives that are available regardless of the target machine
configuration for the gnu assembler. Some machine configurations provide additional di-
rectives. See Chapter 9 [Machine Dependencies], page 89.
7.1 .abort
This directive stops the assembly immediately. It is for compatibility with other assemblers.
The original idea was that the assembly language source would be piped into the assembler.
If the sender of the source quit, it could use this directive tells as to quit also. One day
.abort will not be supported.
7.4 .altmacro
Enable alternate macro mode, enabling:
LOCAL name [ , ... ]
One additional directive, LOCAL, is available. It is used to generate a string
replacement for each of the name arguments, and replace any instances of name
in each macro expansion. The replacement string is unique in the assembly, and
different for each separate macro expansion. LOCAL allows you to write macros
that define symbols, without fear of conflict between separate macro expansions.
String delimiters
You can write strings delimited in these other ways besides "string ":
’string ’ You can delimit strings with single-quote characters.
<string > You can delimit strings with matching angle brackets.
single-character string escape
To include any single character literally in a string (even if the character would
otherwise have some special meaning), you can prefix the character with ‘!’ (an
exclamation mark). For example, you can write ‘<4.3 !> 5.4!!>’ to get the
literal text ‘4.3 > 5.4!’.
Expression results as strings
You can write ‘%expr ’ to evaluate the expression expr and use the result as a
string.
alignment is not done at all. You can omit the fill value (the second argument) entirely by
simply using two commas after the required alignment; this can be useful if you want the
alignment to be filled with no-op instructions when appropriate.
The .balignw and .balignl directives are variants of the .balign directive. The
.balignw directive treats the fill pattern as a two byte word value. The .balignl directives
treats the fill pattern as a four byte longword value. For example, .balignw 4,0x368d will
align to a multiple of 4. If it skips two bytes, they will be filled in with the value 0x368d
(the exact placement of the bytes depends upon the endianness of the processor). If it skips
1 or 3 bytes, the fill value is undefined.
second .bundle_lock directive before the next .bundle_unlock directive has no effect
except that it must be matched by another closing .bundle_unlock so that there is the
same number of .bundle_lock and .bundle_unlock directives.
7.10.3 .cfi_endproc
.cfi_endproc is used at the end of a function where it closes its unwind entry previously
opened by .cfi_startproc, and emits it to .eh_frame.
7.10.5 .cfi_personality_id id
cfi_personality_id defines a personality routine by its index as defined in a compact un-
winding format. Only valid when generating compact EH frames (i.e. with .cfi_sections
eh_frame_entry.
popq %rbx
.cfi_remember_state
.cfi_restore %rbx
popq %r12
.cfi_restore %r12
popq %rbp
.cfi_restore %rbp
.cfi_def_cfa %rsp, 8
ret
label:
.cfi_restore_state
/* Do something else */
That way, the rules for the instructions after label will be the same as before the first
.cfi_restore without having to use multiple .cfi directives.
7.10.22 .cfi_signal_frame
Mark current function as signal trampoline.
7.10.23 .cfi_window_save
SPARC register window has been saved.
boundary (for example, an alignment of 16 means that the least significant 4 bits of the
address should be zero), and for PE as a power of two (for example, an alignment of 5
means aligned to a 32-byte boundary). The alignment must be an absolute expression, and
it must be a power of two. If ld allocates uninitialized memory for the common symbol, it
will use the alignment when placing the symbol. If no alignment is specified, as will set the
alignment to the largest power of two less than or equal to the size of the symbol, up to a
maximum of 16 on ELF, or the default section alignment of 4 on PE1 .
The syntax for .comm differs slightly on the HPPA. The syntax is ‘symbol .comm,
length ’; symbol is optional.
7.15 .dim
This directive is generated by compilers to include auxiliary debugging information in the
symbol table. It is only permitted inside .def/.endef pairs.
7.17 .eject
Force a page break at this point, when generating assembly listings.
1
This is not the same as the executable image file alignment controlled by ld’s ‘--section-alignment’
option; image file sections in PE are aligned to multiples of 4096, which is far too large an alignment for
ordinary variables. It is rather the default alignment for (non-debug) sections within object (‘*.o’) files,
which are less strictly aligned.
Chapter 7: Assembler Directives 57
7.18 .else
.else is part of the as support for conditional assembly; see Section 7.41 [.if], page 60. It
marks the beginning of a section of code to be assembled if the condition for the preceding
.if was false.
7.19 .elseif
.elseif is part of the as support for conditional assembly; see Section 7.41 [.if], page 60.
It is shorthand for beginning a new .if block that would otherwise fill the entire .else
section.
7.20 .end
.end marks the end of the assembly file. as does not process anything in the file past the
.end directive.
7.21 .endef
This directive flags the end of a symbol definition begun with .def.
7.22 .endfunc
.endfunc marks the end of a function specified with .func.
7.23 .endif
.endif is part of the as support for conditional assembly; it marks the end of a block of
code that is only assembled conditionally. See Section 7.41 [.if], page 60.
7.27 .err
If as assembles a .err directive, it will print an error message and, unless the ‘-Z’ option was
used, it will not generate an object file. This can be used to signal an error in conditionally
compiled code.
7.29 .exitm
Exit early from the current macro definition. See Section 7.58 [Macro], page 65.
7.30 .extern
.extern is accepted in the source program—for compatibility with other assemblers—but
it is ignored. as treats all undefined symbols as external.
7.32 .file
There are two different versions of the .file directive. Targets that support DWARF2
line number information use the DWARF2 version of .file. Other targets use the default
version.
Default Version
This version of the .file directive tells as that we are about to start a new logical file.
The syntax is:
.file string
string is the new file name. In general, the filename is recognized whether or not it is
surrounded by quotes ‘"’; but if you wish to specify an empty file name, you must give the
quotes–"". This statement may go away in future: it is only recognized to be compatible
with old as programs.
Chapter 7: Assembler Directives 59
DWARF2 Version
When emitting DWARF2 line number information, .file assigns filenames to the .debug_
line file name table. The syntax is:
.file fileno filename
The fileno operand should be a unique positive integer to use as the index of the entry
in the table. The filename operand is a C string literal.
The detail of filename indices is exposed to the user because the filename table is shared
with the .debug_info section of the DWARF2 debugging information, and thus the user
must know the exact indices that table entries will have.
7.40 .ident
This directive is used by some assemblers to place tags in object files. The behavior of
this directive varies depending on the target. When using the a.out object file format, as
simply accepts the directive for source-file compatibility with existing assemblers, but does
not emit anything for it. When using COFF, comments are emitted to the .comment or
.rdata section, depending on the target. When using ELF, comments are emitted to the
.comment section.
of the line. Strings which contain whitespace should be quoted. The string
comparison is case sensitive.
.ifeq absolute expression
Assembles the following section of code if the argument is zero.
.ifeqs string1 ,string2
Another form of .ifc. The strings must be quoted using double quotes.
.ifge absolute expression
Assembles the following section of code if the argument is greater than or equal
to zero.
.ifgt absolute expression
Assembles the following section of code if the argument is greater than zero.
.ifle absolute expression
Assembles the following section of code if the argument is less than or equal to
zero.
.iflt absolute expression
Assembles the following section of code if the argument is less than zero.
.ifnb text
Like .ifb, but the sense of the test is reversed: this assembles the following
section of code if the operand is non-blank (non-empty).
.ifnc string1 ,string2 .
Like .ifc, but the sense of the test is reversed: this assembles the following
section of code if the two strings are not the same.
.ifndef symbol
.ifnotdef symbol
Assembles the following section of code if the specified symbol has not been
defined. Both spelling variants are equivalent. Note a symbol which has been
referenced but not yet defined is considered to be undefined.
.ifne absolute expression
Assembles the following section of code if the argument is not equal to zero (in
other words, this is equivalent to .if).
.ifnes string1 ,string2
Like .ifeqs, but the sense of the test is reversed: this assembles the following
section of code if the two strings are not the same.
.irpc param,123
move d\param,sp@-
.endr
is equivalent to assembling
move d1,sp@-
move d2,sp@-
move d3,sp@-
For some caveats with the spelling of symbol, see also the discussion at See Section 7.58
[Macro], page 65.
7.49 .lflags
as accepts this directive, for compatibility with other assemblers, but ignores it.
The type argument is optional. If specified, it must be one of the following strings. For
example:
.linkonce same_size
Not all types may be supported on all object file formats.
discard Silently discard duplicate sections. This is the default.
one_only Warn if there are duplicate sections, but still keep only one copy.
same_size
Warn if any of the duplicates have different sizes.
same_contents
Warn if any of the duplicates do not have exactly the same contents.
7.52 .list
Control (in conjunction with the .nolist directive) whether or not assembly listings are
generated. These two directives maintain an internal counter (which is zero initially).
.list increments the counter, and .nolist decrements it. Assembly listings are generated
whenever the counter is greater than zero.
By default, listings are disabled. When you enable them (with the ‘-a’ command line
option; see Chapter 2 [Command-Line Options], page 23), the initial value of the listing
counter is one.
isa value
This directive will set the isa register in the .debug_line state machine to
value, which must be an unsigned integer.
discriminator value
This directive will set the discriminator register in the .debug_line state
machine to value, which must be an unsigned integer.
view value
This option causes a row to be added to .debug_line in reference to the cur-
rent address (which might not be the same as that of the following assembly
instruction), and to associate value with the view register in the .debug_line
state machine. If value is a label, both the view register and the label are set
to the number of prior .loc directives at the same program location. If value
is the literal 0, the view register is set to zero, and the assembler asserts that
there aren’t any prior .loc directives at the same program location. If value
is the literal -0, the assembler arrange for the view register to be reset in this
row, even if there are prior .loc directives at the same program location.
7.58 .macro
The commands .macro and .endm allow you to define macros that generate assembly output.
For example, this definition specifies a macro sum that puts a sequence of numbers into
memory:
.macro sum from=0, to=5
.long \from
.if \to-\from
sum "(\from+1)",\to
66 Using as
.endif
.endm
With that definition, ‘SUM 0,5’ is equivalent to this assembly input:
.long 0
.long 1
.long 2
.long 3
.long 4
.long 5
.macro macname
.macro macname macargs ...
Begin the definition of a macro called macname. If your macro definition
requires arguments, specify their names after the macro name, separated by
commas or spaces. You can qualify the macro argument to indicate whether
all invocations must specify a non-blank value (through ‘:req’), or whether it
takes all of the remaining arguments (through ‘:vararg’). You can supply a
default value for any macro argument by following the name with ‘=deflt ’.
You cannot define two macros with the same macname unless it has been sub-
ject to the .purgem directive (see Section 7.71 [Purgem], page 71) between the
two definitions. For example, these are all valid .macro statements:
.macro comm
Begin the definition of a macro called comm, which takes no argu-
ments.
.macro plus1 p, p1
.macro plus1 p p1
Either statement begins the definition of a macro called plus1,
which takes two arguments; within the macro definition, write ‘\p’
or ‘\p1’ to evaluate the arguments.
.macro reserve_str p1=0 p2
Begin the definition of a macro called reserve_str, with two argu-
ments. The first argument has a default value, but not the second.
After the definition is complete, you can call the macro either as
‘reserve_str a ,b ’ (with ‘\p1’ evaluating to a and ‘\p2’ evaluating
to b), or as ‘reserve_str ,b ’ (with ‘\p1’ evaluating as the default,
in this case ‘0’, and ‘\p2’ evaluating to b).
.macro m p1:req, p2=0, p3:vararg
Begin the definition of a macro called m, with at least three ar-
guments. The first argument must always have a value specified,
but not the second, which instead has a default value. The third
formal will get assigned all remaining arguments specified at invo-
cation time.
When you call a macro, you can specify the argument values either
by position, or by keyword. For example, ‘sum 9,17’ is equivalent
to ‘sum to=17, from=9’.
Chapter 7: Assembler Directives 67
Note that since each of the macargs can be an identifier exactly as any other
one permitted by the target architecture, there may be occasional problems if
the target hand-crafts special meanings to certain characters when they occur
in a special position. For example, if the colon (:) is generally permitted to
be part of a symbol name, but the architecture specific code special-cases it
when occurring as the final character of a symbol (to denote a label), then
the macro parameter replacement code will have no way of knowing that and
consider the whole construct (including the colon) an identifier, and check only
this identifier for being the subject to parameter substitution. So for example
this macro definition:
.macro label l
\l:
.endm
might not work as expected. Invoking ‘label foo’ might not create a label
called ‘foo’ but instead just insert the text ‘\l:’ into the assembler source,
probably generating an error about an unrecognised identifier.
Similarly problems might occur with the period character (‘.’) which is often
allowed inside opcode names (and hence identifier names). So for example
constructing a macro to build an opcode from a base name and a length specifier
like this:
.macro opcode base length
\base.\length
.endm
and invoking it as ‘opcode store l’ will not create a ‘store.l’ instruction but
instead generate some kind of error as the assembler tries to interpret the text
‘\base.\length’.
There are several possible ways around this problem:
Insert white space
If it is possible to use white space characters then this is the simplest
solution. eg:
.macro label l
\l :
.endm
Use ‘\()’ The string ‘\()’ can be used to separate the end of a macro argu-
ment from the following text. eg:
.macro opcode base length
\base\().\length
.endm
Use the alternate macro syntax mode
In the alternative macro syntax mode the ampersand character (‘&’)
can be used as a separator. eg:
.altmacro
.macro label l
l&:
68 Using as
.endm
Note: this problem of correctly identifying string parameters to pseudo ops
also applies to the identifiers used in .irp (see Section 7.46 [Irp], page 62) and
.irpc (see Section 7.47 [Irpc], page 62) as well.
.endm Mark the end of a macro definition.
.exitm Exit early from the current macro definition.
\@ as maintains a counter of how many macros it has executed in this pseudo-
variable; you can copy that number to your output with ‘\@’, but only within
a macro definition.
LOCAL name [ , ... ]
Warning: LOCAL is only available if you select “alternate macro syntax” with
‘--alternate’ or .altmacro. See Section 7.4 [.altmacro], page 50.
7.60 .noaltmacro
Disable alternate macro mode. See Section 7.4 [Altmacro], page 50.
7.61 .nolist
Control (in conjunction with the .list directive) whether or not assembly listings are
generated. These two directives maintain an internal counter (which is zero initially).
.list increments the counter, and .nolist decrements it. Assembly listings are generated
whenever the counter is greater than zero.
can’t use .org to cross sections: if new-lc has the wrong section, the .org directive is
ignored. To be compatible with former assemblers, if the section of new-lc is absolute, as
issues a warning, then pretends the section of new-lc is the same as the current subsection.
.org may only increase the location counter, or leave it unchanged; you cannot use .org
to move the location counter backwards.
Because as tries to assemble programs in one pass, new-lc may not be undefined. If you
really detest this restriction we eagerly await a chance to share your improved assembler.
Beware that the origin is relative to the start of the section, not to the start of the
subsection. This is compatible with other people’s assemblers.
When the location counter (of the current subsection) is advanced, the intervening bytes
are filled with fill which should be an absolute expression. If the comma and fill are omitted,
fill defaults to zero.
7.66 .popsection
This is one of the ELF section stack manipulation directives. The others are .section
(see Section 7.78 [Section], page 72), .subsection (see Section 7.89 [SubSection], page 78),
.pushsection (see Section 7.72 [PushSection], page 71), and .previous (see Section 7.67
[Previous], page 70).
This directive replaces the current section (and subsection) with the top section (and
subsection) on the section stack. This section is popped off the stack.
70 Using as
7.67 .previous
This is one of the ELF section stack manipulation directives. The others are .section
(see Section 7.78 [Section], page 72), .subsection (see Section 7.89 [SubSection], page 78),
.pushsection (see Section 7.72 [PushSection], page 71), and .popsection (see Section 7.66
[PopSection], page 69).
This directive swaps the current section (and subsection) with most recently referenced
section/subsection pair prior to this one. Multiple .previous directives in a row will flip
between two sections (and their subsections). For example:
.section A
.subsection 1
.word 0x1234
.subsection 2
.word 0x5678
.previous
.word 0x9abc
Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into subsection 2 of section
A. Whilst:
.section A
.subsection 1
# Now in section A subsection 1
.word 0x1234
.section B
.subsection 0
# Now in section B subsection 0
.word 0x5678
.subsection 1
# Now in section B subsection 1
.word 0x9abc
.previous
# Now in section B subsection 0
.word 0xdef0
Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 0 of section B and
0x9abc into subsection 1 of section B.
In terms of the section stack, this directive swaps the current section with the top section
on the section stack.
COFF Version
For COFF targets, the .section directive is used in one of the following ways:
.section name [, "flags "]
.section name [, subsection ]
If the optional argument is quoted, it is taken as flags to use for the section. Each flag
is a single character. The following flags are recognized:
b bss section (uninitialized data)
n section is not loaded
w writable section
d data section
Chapter 7: Assembler Directives 73
ELF Version
This is one of the ELF section stack manipulation directives. The others are .subsection
(see Section 7.89 [SubSection], page 78), .pushsection (see Section 7.72 [PushSection],
page 71), .popsection (see Section 7.66 [PopSection], page 69), and .previous (see
Section 7.67 [Previous], page 70).
For ELF targets, the .section directive is used like this:
.section name [, "flags "[, @type [,flag_specific_arguments ]]]
If the ‘--sectname-subst’ command-line option is provided, the name argument may
contain a substitution sequence. Only %S is supported at the moment, and substitutes the
current section name. For example:
.macro exception_code
.section %S.exception
[exception code here]
.previous
.endm
.text
[code]
exception_code
[...]
.section .init
[init code]
exception_code
[...]
The two exception_code invocations above would create the .text.exception and
.init.exception sections respectively. This is useful e.g. to discriminate between ancillary
sections that are tied to setup code to be discarded after use from ancillary sections that
need to stay resident without having to define multiple exception_code macros just for
that purpose.
The optional flags argument is a quoted string which may contain any combination of
the following characters:
74 Using as
a section is allocatable
d section is a GNU MBIND section
e section is excluded from executable and shared library.
w section is writable
x section is executable
M section is mergeable
S section contains zero terminated strings
G section is a member of a section group
T section is used for thread-local-storage
? section is a member of the previously-current section’s group, if any
<number> a numeric value indicating the bits to be set in the ELF section header’s flags
field. Note - if one or more of the alphabetic characters described above is also
included in the flags field, their bit values will be ORed into the resulting value.
<target specific>
some targets extend this list with their own flag characters
Note - once a section’s flags have been set they cannot be changed. There are a few
exceptions to this rule however. Processor and application specific flags can be added to an
already defined section. The .interp, .strtab and .symtab sections can have the allocate
flag (a) set after they are initially defined, and the .note-GNU-stack section may have the
executable (x) flag added.
The optional type argument may contain one of the following constants:
@progbits
section contains data
@nobits section does not contain data (i.e., section only occupies space)
@note section contains data which is used by things other than the program
@init_array
section contains an array of pointers to init functions
@fini_array
section contains an array of pointers to finish functions
@preinit_array
section contains an array of pointers to pre-init functions
@<number>
a numeric value to be set as the ELF section header’s type field.
@<target specific>
some targets extend this list with their own types
Many targets only support the first three section types. The type may be enclosed in
double quotes if necessary.
Chapter 7: Assembler Directives 75
Note on targets where the @ character is the start of a comment (eg ARM) then another
character is used instead. For example the ARM port uses the % character.
Note - some sections, eg .text and .data are considered to be special and have fixed
types. Any attempt to declare them with a different type will generate an error from the
assembler.
If flags contains the M symbol then the type argument must be specified as well as an
extra argument—entsize—like this:
.section name , "flags "M, @type , entsize
Sections with the M flag but not S flag must contain fixed size constants, each entsize
octets long. Sections with both M and S must contain zero terminated strings where each
character is entsize bytes long. The linker may remove duplicates within sections with the
same name, same entity size and same flags. entsize must be an absolute expression. For
sections with both M and S, a string which is a suffix of a larger string is considered a
duplicate. Thus "def" will be merged with "abcdef"; A reference to the first "def" will
be changed to a reference to "abcdef"+3.
If flags contains the G symbol then the type argument must be present along with an
additional field like this:
.section name , "flags "G, @type , GroupName [, linkage ]
The GroupName field specifies the name of the section group to which this particular
section belongs. The optional linkage field can contain:
comdat indicates that only one copy of this section should be retained
.gnu.linkonce
an alias for comdat
Note: if both the M and G flags are present then the fields for the Merge flag should
come first, like this:
.section name , "flags "MG, @type , entsize , GroupName [, linkage ]
If flags contains the ? symbol then it may not also contain the G symbol and the Group-
Name or linkage fields should not be present. Instead, ? says to consider the section that’s
current before this directive. If that section used G, then the new section will use G with
those same GroupName and linkage fields implicitly. If not, then the ? symbol has no effect.
If no flags are specified, the default flags depend upon the section name. If the section
name is not recognized, the default will be for the section to have none of the above flags:
it will not be allocated in memory, nor writable, nor executable. The section will contain
data.
For ELF targets, the assembler supports another type of .section directive for compat-
ibility with the Solaris assembler:
.section "name "[, flags ...]
Note that the section name is quoted. There may be a sequence of comma separated
flags:
#alloc section is allocatable
#write section is writable
#execinstr
section is executable
76 Using as
7.82 .size
This directive is used to set the size associated with a symbol.
COFF Version
For COFF targets, the .size directive is only permitted inside .def/.endef pairs. It is
used like this:
.size expression
ELF Version
For ELF targets, the .size directive is used like this:
Chapter 7: Assembler Directives 77
.popsection (see Section 7.66 [PopSection], page 69), and .previous (see Section 7.67
[Previous], page 70).
This directive replaces the current subsection with name. The current section is not
changed. The replaced subsection is put onto the section stack in place of the then current
top of stack subsection.
7.90 .symver
Use the .symver directive to bind symbols to specific version nodes within a source file.
This is only supported on ELF platforms, and is typically used when assembling files to be
linked into a shared library. There are cases where it may make sense to use this in objects
to be bound into an application itself so as to override a versioned symbol from a shared
library.
For ELF targets, the .symver directive can be used like this:
.symver name , name2@nodename
If the symbol name is defined within the file being assembled, the .symver directive
effectively creates a symbol alias with the name name2@nodename, and in fact the main
reason that we just don’t try and create a regular alias is that the @ character isn’t permitted
in symbol names. The name2 part of the name is the actual name of the symbol by which
it will be externally referenced. The name name itself is merely a name of convenience that
is used so that it is possible to have definitions for multiple versions of a function within
a single source file, and so that the compiler can unambiguously know which version of a
function is being mentioned. The nodename portion of the alias should be the name of a
node specified in the version script supplied to the linker when building a shared library. If
you are attempting to override a versioned symbol from a shared library, then nodename
should correspond to the nodename of the symbol you are trying to override.
If the symbol name is not defined within the file being assembled, all references to name
will be changed to name2@nodename. If no reference to name is made, name2@nodename
will be removed from the symbol table.
Another usage of the .symver directive is:
.symver name , name2@@nodename
In this case, the symbol name must exist and be defined within the file being assembled.
It is similar to name2@nodename. The difference is name2@@nodename will also be used to
resolve references to name2 by the linker.
The third usage of the .symver directive is:
.symver name , name2@@@nodename
When name is not defined within the file being assembled, it is treated as
name2@nodename. When name is defined within the file being assembled, the symbol
name, name, will be changed to name2@@nodename.
7.94 .type
This directive is used to set the type of a symbol.
COFF Version
For COFF targets, this directive is permitted only within .def/.endef pairs. It is used
like this:
.type int
This records the integer int as the type attribute of a symbol table entry.
ELF Version
For ELF targets, the .type directive is used like this:
.type name , type description
This sets the type of symbol name to be either a function symbol or an object symbol.
There are five different syntaxes supported for the type description field, in order to provide
compatibility with various other assemblers.
Because some of the characters used in these syntaxes (such as ‘@’ and ‘#’) are comment
characters for some architectures, some of the syntaxes below do not work on all architec-
tures. The first variant will be accepted by the GNU assembler on all architectures so that
variant should be used for maximum portability, if you do not need to assemble your code
with other assemblers.
The syntaxes supported are:
.type <name> STT_<TYPE_IN_UPPER_CASE>
.type <name>,#<type>
.type <name>,@<type>
.type <name>,%<type>
.type <name>,"<type>"
The types supported are:
STT_FUNC
function Mark the symbol as being a function name.
STT_GNU_IFUNC
gnu_indirect_function
Mark the symbol as an indirect function when evaluated during reloc processing.
(This is only supported on assemblers targeting GNU systems).
Chapter 7: Assembler Directives 81
STT_OBJECT
object Mark the symbol as being a data object.
STT_TLS
tls_object
Mark the symbol as being a thread-local data object.
STT_COMMON
common Mark the symbol as being a common data object.
STT_NOTYPE
notype Does not mark the symbol in any way. It is supported just for completeness.
gnu_unique_object
Marks the symbol as being a globally unique data object. The dynamic linker
will make sure that in the entire process there is just one symbol with this
name and type in use. (This is only supported on assemblers targeting GNU
systems).
Note: Some targets support extra types in addition to those listed above.
are adjusted to contain sym3 minus the address of the long-jump to sym4; and so on, for as
many entries in the original jump table as necessary.
8 Object Attributes
as assembles source files written for a specific architecture into object files for that architec-
ture. But not all object files are alike. Many architectures support incompatible variations.
For instance, floating point arguments might be passed in floating point registers if the
object file requires hardware floating point support—or floating point arguments might be
passed in integer registers if the object file supports processors with no hardware floating
point unit. Or, if two objects are built for different generations of the same architecture,
the combination may require the newer generation at run-time.
This information is useful during and after linking. At link time, ld can warn about
incompatible object files. After link time, tools like gdb can use it to process the linked file
correctly.
Compatibility information is recorded as a series of object attributes. Each attribute has
a vendor, tag, and value. The vendor is a string, and indicates who sets the meaning of the
tag. The tag is an integer, and indicates what property the attribute describes. The value
may be a string or an integer, and indicates how the property affects this object. Missing
attributes are the same as attributes with a zero value or empty string value.
Object attributes were developed as part of the ABI for the ARM Architecture. The file
format is documented in ELF for the ARM Architecture.
Enabling an extension that requires other extensions will automatically cause those ex-
tensions to be enabled. Similarly, disabling an extension that is required by other extensions
will automatically cause those extensions to be disabled.
9.1.3 Syntax
9.1.3.1 Special Characters
The presence of a ‘//’ on a line indicates the start of a comment that extends to the end of
the current line. If a ‘#’ appears as the first character of a line, the whole line is treated as
a comment.
The ‘;’ character can be used instead of a newline to separate statements.
The ‘#’ can be optionally used to indicate immediate operands.
9.1.3.3 Relocations
Relocations for ‘MOVZ’ and ‘MOVK’ instructions can be generated by prefixing the label with
‘#:abs_g2:’ etc. For example to load the 48-bit absolute address of foo into x0:
movz x0, #:abs_g2:foo // bits 32-47, overflow check
movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
Relocations for ‘ADRP’, and ‘ADD’, ‘LDR’ or ‘STR’ instructions can be generated by prefixing
the label with ‘:pg_hi21:’ and ‘#:lo12:’ respectively.
For example to use 33-bit (+/-4GB) pc-relative addressing to load the address of foo into
x0:
adrp x0, :pg_hi21:foo
add x0, x0, #:lo12:foo
Or to load the value of foo into x0:
adrp x0, :pg_hi21:foo
ldr x0, [x0, #:lo12:foo]
Note that ‘:pg_hi21:’ is optional.
adrp x0, foo
is equivalent to
adrp x0, :pg_hi21:foo
.tlsdescldr
Emits a TLSDESC LDR reloc on the next instruction.
.unreq alias-name
This undefines a register alias which was previously defined using the req di-
rective. For example:
foo .req w0
.unreq foo
An error occurs if the name is undefined. Note - this pseudo op can be used to
delete builtin in register name aliases (eg ’w0’). This should only be done if it
is really necessary.
.xword expressions
The .xword directive produces 64 bit values. This is the same as the .dword
directive.
9.1.6 Opcodes
GAS implements all the standard AArch64 opcodes. It also implements several pseudo
opcodes, including several synthetic load instructions.
LDR =
ldr <register> , =<expression>
The constant expression will be placed into the nearest literal pool (if it not
already there) and a PC-relative LDR instruction will be generated.
For more information on the AArch64 instruction set and assembly language notation,
see ‘ARMv8 Instruction Set Overview’ available at http://infocenter.arm.com.
9.2.2 Options
-mcpu This option specifies the target processor. If an attempt is made to assemble an
instruction which will not execute on the target processor, the assembler may
either expand the instruction as a macro or issue an error message. This option
is equivalent to the .arch directive.
The following processor names are recognized: 21064, 21064a, 21066, 21068,
21164, 21164a, 21164pc, 21264, 21264a, 21264b, ev4, ev5, lca45, ev5, ev56,
pca56, ev6, ev67, ev68. The special name all may be used to allow the
assembler to accept instructions valid for any Alpha processor.
In order to support existing practice in OSF/1 with respect to .arch, and exist-
ing practice within MILO (the Linux ARC bootloader), the numbered processor
names (e.g. 21064) enable the processor-specific PALcode instructions, while
the “electro-vlasic” names (e.g. ev4) do not.
-mdebug
-no-mdebug
Enables or disables the generation of .mdebug encapsulation for stabs directives
and procedure descriptors. The default is to automatically enable .mdebug
when the first stabs directive is seen.
-relax This option forces all relocations to be put into the object file, instead of saving
space and resolving some relocations at assembly time. Note that this option
does not propagate all symbol arithmetic into the object file, because not all
symbol arithmetic can be represented. However, the option can still be useful
in specific applications.
-replace
-noreplace
Enables or disables the optimization of procedure calls, both at assemblage and
at link time. These options are only available for VMS targets and -replace
is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual.
-g This option is used when the compiler generates debug information. When gcc
is using mips-tfile to generate debug information for ECOFF, local labels
must be passed through to the object file. Otherwise this option has no effect.
-Gsize A local common symbol larger than size is placed in .bss, while smaller symbols
are placed in .sbss.
-F
-32addr These options are ignored for backward compatibility.
96 Using as
9.2.3 Syntax
The assembler syntax closely follow the Alpha Reference Manual; assembler directives and
general syntax closely follow the OSF/1 and OpenVMS syntax, with a few differences for
ELF.
9.2.3.3 Relocations
Some of these relocations are available for ECOFF, but mostly only for ELF. They are
modeled after the relocation format introduced in Digital Unix 4.0, but there are additions.
The format is ‘!tag ’ or ‘!tag !number ’ where tag is the name of the relocation. In some
cases number is used to relate specific instructions.
The relocation is placed at the end of the instruction like so:
ldah $0,a($29) !gprelhigh
lda $0,a($0) !gprellow
ldq $1,b($29) !literal!100
ldl $2,0($1) !lituse_base!100
!literal
!literal!N
Used with an ldq instruction to load the address of a symbol from the GOT.
A sequence number N is optional, and if present is used to pair lituse relo-
cations with this literal relocation. The lituse relocations are used by the
linker to optimize the code based on the final location of the symbol.
Note that these optimizations are dependent on the data flow of the program.
Therefore, if any lituse is paired with a literal relocation, then all uses of
the register set by the literal instruction must also be marked with lituse
relocations. This is because the original literal instruction may be deleted or
transformed into another instruction.
Also note that there may be a one-to-many relationship between literal and
lituse, but not a many-to-one. That is, if there are two code paths that load
up the same address and feed the value to a single use, then the use may not
use a lituse relocation.
Chapter 9: Machine Dependent Features 97
!lituse_base!N
Used with any memory format instruction (e.g. ldl) to indicate that the literal
is used for an address load. The offset field of the instruction must be zero.
During relaxation, the code may be altered to use a gp-relative load.
!lituse_jsr!N
Used with a register branch format instruction (e.g. jsr) to indicate that the
literal is used for a call. During relaxation, the code may be altered to use a
direct branch (e.g. bsr).
!lituse_jsrdirect!N
Similar to lituse_jsr, but also that this call cannot be vectored through a
PLT entry. This is useful for functions with special calling conventions which
do not allow the normal call-clobbered registers to be clobbered.
!lituse_bytoff!N
Used with a byte mask instruction (e.g. extbl) to indicate that only the low 3
bits of the address are relevant. During relaxation, the code may be altered to
use an immediate instead of a register shift.
!lituse_addr!N
Used with any other instruction to indicate that the original address is in fact
used, and the original ldq instruction may not be altered or deleted. This is
useful in conjunction with lituse_jsr to test whether a weak symbol is defined.
ldq $27,foo($29) !literal!1
beq $27,is_undef !lituse_addr!1
jsr $26,($27),foo !lituse_jsr!1
!lituse_tlsgd!N
Used with a register branch format instruction to indicate that the literal is
the call to __tls_get_addr used to compute the address of the thread-local
storage variable whose descriptor was loaded with !tlsgd!N .
!lituse_tlsldm!N
Used with a register branch format instruction to indicate that the literal is the
call to __tls_get_addr used to compute the address of the base of the thread-
local storage block for the current module. The descriptor for the module must
have been loaded with !tlsldm!N .
!gpdisp!N
Used with ldah and lda to load the GP from the current address, a-la the ldgp
macro. The source register for the ldah instruction must contain the address
of the ldah instruction. There must be exactly one lda instruction paired with
the ldah instruction, though it may appear anywhere in the instruction stream.
The immediate operands must be zero.
bsr $26,foo
ldah $29,0($26) !gpdisp!1
lda $29,0($29) !gpdisp!1
!gprelhigh
Used with an ldah instruction to add the high 16 bits of a 32-bit displacement
from the GP.
98 Using as
!gprellow
Used with any memory format instruction to add the low 16 bits of a 32-bit
displacement from the GP.
!gprel Used with any memory format instruction to add a 16-bit displacement from
the GP.
!samegp Used with any branch format instruction to skip the GP load at the target
address. The referenced symbol must have the same GP as the source object
file, and it must be declared to either not use $27 or perform a standard GP
load in the first two instructions via the .prologue directive.
!tlsgd
!tlsgd!N Used with an lda instruction to load the address of a TLS descriptor for a
symbol in the GOT.
The sequence number N is optional, and if present it used to pair the descriptor
load with both the literal loading the address of the __tls_get_addr function
and the lituse_tlsgd marking the call to that function.
For proper relaxation, both the tlsgd, literal and lituse relocations must
be in the same extended basic block. That is, the relocation with the lowest
address must be executed first at runtime.
!tlsldm
!tlsldm!N
Used with an lda instruction to load the address of a TLS descriptor for the
current module in the GOT.
Similar in other respects to tlsgd.
!gotdtprel
Used with an ldq instruction to load the offset of the TLS symbol within its
module’s thread-local storage block. Also known as the dynamic thread pointer
offset or dtp-relative offset.
!dtprelhi
!dtprello
!dtprel Like gprel relocations except they compute dtp-relative offsets.
!gottprel
Used with an ldq instruction to load the offset of the TLS symbol from the
thread pointer. Also known as the tp-relative offset.
!tprelhi
!tprello
!tprel Like gprel relocations except they compute tp-relative offsets.
The which argument should be either no, indicating that $27 is not used, or
std, indicating that the first two instructions of the function perform a GP
load.
One might use this directive instead of .prologue if you are also using dwarf2
CFI directives.
.gprel32 expression
Computes the difference between the address in expression and the GP for the
current object file, and stores it in 4 bytes. In addition to being smaller than a
full 8 byte address, this also does not require a dynamic relocation when used
in a shared library.
.t_floating expression
Stores expression as an ieee double precision value.
.s_floating expression
Stores expression as an ieee single precision value.
.f_floating expression
Stores expression as a VAX F format value.
.g_floating expression
Stores expression as a VAX G format value.
.d_floating expression
Stores expression as a VAX D format value.
.set feature
Enables or disables various assembler features. Using the positive name of the
feature enables while using ‘nofeature ’ disables.
at Indicates that macro expansions may clobber the assembler tem-
porary ($at or $28) register. Some macros may not be expanded
without this and will generate an error message if noat is in effect.
When at is in effect, a warning will be generated if $at is used by
the programmer.
macro Enables the expansion of macro instructions. Note that variants of
real instructions, such as br label vs br $31,label are considered
alternate forms and not macros.
move
reorder
volatile These control whether and how the assembler may re-order instruc-
tions. Accepted for compatibility with the OSF/1 assembler, but
as does not do instruction scheduling, so these features are ignored.
The following directives are recognized for compatibility with the OSF/1 assembler but
are ignored.
.proc .aproc
.reguse .livereg
.option .aent
.ugen .eflag
.alias .noalias
Chapter 9: Machine Dependent Features 101
9.2.6 Opcodes
For detailed information on the Alpha machine instruction set, see the Alpha Architecture
Handbook located at
ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf
102 Using as
9.3.2 Syntax
9.3.2.1 Special Characters
% A register name can optionally be prefixed by a ‘%’ character. So register %r0
is equivalent to r0 in the assembly code.
# The presence of a ‘#’ character within a line (but not at the start of a line)
indicates the start of a comment that extends to the end of the current line.
Note: if a line starts with a ‘#’ character then it can also be a logical line num-
ber directive (see Section 3.3 [Comments], page 29) or a preprocessor control
command (see Section 3.1 [Preprocessing], page 29).
@ Prefixing an operand with an ‘@’ specifies that the operand is a symbol and not
a register. This is how the assembler disambiguates the use of an ARC register
name as a symbol. So the instruction
mov r0, @r0
moves the address of symbol r0 into register r0.
‘ The ‘‘’ (backtick) character is used to separate statements on a single line.
- Used as a separator to obtain a sequence of commands from a C preprocessor
macro.
104 Using as
bta_link_build
Build configuration for: BTA Registers. Auxiliary register address 0x63.
vecbase_ac_build
Build configuration for: Interrupts. Auxiliary register address 0x68.
rf_build Build configuration for: Core Registers. Auxiliary register address 0x6e.
dccm_build
DCCM RAM Configuration Register. Auxiliary register address 0xc1.
Additional auxiliary register names are defined according to the processor architecture
version and extensions selected by the options.
.extCondCode is_busy,0x14
add.is_busy r1,r2,r3
will only execute the add instruction if the condition code value is 0x14.
.extCoreRegister name , regnum , mode , shortcut
Specifies an extension core register named name as a synonym for the register
numbered regnum. The register number must be between 32 and 59. The third
argument, mode, indicates whether the register is readable and/or writable and
is one of:
r Read only;
w Write only;
r|w Read and write.
The final parameter, shortcut indicates whether the register has a short cut in
the pipeline. The valid values are:
can_shortcut
The register has a short cut in the pipeline;
cannot_shortcut
The register does not have a short cut in the pipeline.
For example:
.extCoreRegister mlo, 57, r , can_shortcut
defines a read only extension core register, mlo, which is register 57, and can
short cut the pipeline.
.extInstruction name , opcode , subopcode , suffixclass , syntaxclass
ARC allows the user to specify extension instructions. These extension in-
structions are not macros; the assembler creates encodings for use of these
instructions according to the specification by the user.
The first argument, name, gives the name of the instruction.
The second argument, opcode, is the opcode to be used (bits 31:27 in the
encoding).
The third argument, subopcode, is the sub-opcode to be used, but the correct
value also depends on the fifth argument, syntaxclass
The fourth argument, suffixclass, determines the kinds of suffixes to be allowed.
Valid values are:
SUFFIX_NONE
No suffixes are permitted;
SUFFIX_COND
Conditional suffixes are permitted;
SUFFIX_FLAG
Flag setting suffixes are permitted.
SUFFIX_COND|SUFFIX_FLAG
Both conditional and flag setting suffices are permitted.
108 Using as
The fifth and final argument, syntaxclass, determines the syntax class for the
instruction. It can have the following values:
SYNTAX_2OP
Two Operand Instruction;
SYNTAX_3OP
Three Operand Instruction.
SYNTAX_1OP
One Operand Instruction.
SYNTAX_NOP
No Operand Instruction.
The syntax class may be followed by ‘|’ and one of the following modifiers.
OP1_MUST_BE_IMM
Modifies syntax class SYNTAX_3OP, specifying that the first operand
of a three-operand instruction must be an immediate (i.e., the result
is discarded). This is usually used to set the flags using specific
instructions and not retain results.
OP1_IMM_IMPLIED
Modifies syntax class SYNTAX_20P, specifying that there is an im-
plied immediate destination operand which does not appear in the
syntax.
For example, if the source code contains an instruction like:
inst r1,r2
the first argument is an implied immediate (that is, the result is
discarded). This is the same as though the source code were: inst
0,r1,r2.
For example, defining a 64-bit multiplier with immediate operands:
.extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
SYNTAX_3OP|OP1_MUST_BE_IMM
which specifies an extension instruction named mp64 with 3 operands. It sets
the flags and can be used with a condition code, for which the first operand is
an immediate, i.e. equivalent to discarding the result of the operation.
A two operands instruction variant would be:
.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
SYNTAX_2OP|OP1_IMM_IMPLIED
which describes a two operand instruction with an implicit first immediate
operand. The result of this operation would be discarded.
.arc_attribute tag , value
Set the ARC object attribute tag to value.
The tag is either an attribute number, or one of the following: Tag_ARC_PCS_
config, Tag_ARC_CPU_base, Tag_ARC_CPU_variation, Tag_ARC_CPU_name,
Chapter 9: Machine Dependent Features 109
9.3.6 Opcodes
For information on the ARC instruction set, see ARC Programmers Reference Manual,
available where you download the processor IP library.
110 Using as
-mfpu=floating-point-format
This option specifies the floating point format to assemble for. The assembler
will issue an error message if an attempt is made to assemble an instruction
which will not execute on the target floating point unit. The following
format options are recognized: softfpa, fpe, fpe2, fpe3, fpa, fpa10, fpa11,
arm7500fe, softvfp, softvfp+vfp, vfp, vfp10, vfp10-r0, vfp9, vfpxd,
vfpv2, vfpv3, vfpv3-fp16, vfpv3-d16, vfpv3-d16-fp16, vfpv3xd, vfpv3xd-
d16, vfpv4, vfpv4-d16, fpv4-sp-d16, fpv5-sp-d16, fpv5-d16, fp-armv8,
arm1020t, arm1020e, arm1136jf-s, maverick, neon, neon-vfpv3, neon-fp16,
neon-vfpv4, neon-fp-armv8, crypto-neon-fp-armv8, neon-fp-armv8.1 and
crypto-neon-fp-armv8.1.
In addition to determining which instructions are assembled, this option also
affects the way in which the .double assembler directive behaves when assem-
bling little-endian code.
The default is dependent on the processor selected. For Architecture 5 or later,
the default is to assemble for VFP instructions; for earlier architectures the
default is to assemble for FPA instructions.
-mthumb This option specifies that the assembler should start assembling Thumb in-
structions; that is, it should behave as though the file starts with a .code 16
directive.
112 Using as
-mthumb-interwork
This option specifies that the output generated by the assembler should be
marked as supporting interworking.
-mimplicit-it=never
-mimplicit-it=always
-mimplicit-it=arm
-mimplicit-it=thumb
The -mimplicit-it option controls the behavior of the assembler when con-
ditional instructions are not enclosed in IT blocks. There are four possible
behaviors. If never is specified, such constructs cause a warning in ARM code
and an error in Thumb-2 code. If always is specified, such constructs are ac-
cepted in both ARM and Thumb-2 code, where the IT instruction is added
implicitly. If arm is specified, such constructs are accepted in ARM code and
cause an error in Thumb-2 code. If thumb is specified, such constructs cause
a warning in ARM code and are accepted in Thumb-2 code. If you omit this
option, the behavior is equivalent to -mimplicit-it=arm.
-mapcs-26
-mapcs-32
These options specify that the output generated by the assembler should be
marked as supporting the indicated version of the Arm Procedure. Calling
Standard.
-matpcs This option specifies that the output generated by the assembler should be
marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled
this option will cause the assembler to create an empty debugging section in
the object file called .arm.atpcs. Debuggers can use this to determine the ABI
being used by.
-mapcs-float
This indicates the floating point variant of the APCS should be used. In this
variant floating point arguments are passed in FP registers rather than integer
registers.
-mapcs-reentrant
This indicates that the reentrant variant of the APCS should be used. This
variant supports position independent code.
-mfloat-abi=abi
This option specifies that the output generated by the assembler should be
marked as using specified floating point ABI. The following values are recog-
nized: soft, softfp and hard.
-meabi=ver
This option specifies which EABI version the produced object files should con-
form to. The following values are recognized: gnu, 4 and 5.
-EB This option specifies that the output generated by the assembler should be
marked as being encoded for a big-endian processor.
Note: If a program is being built for a system with big-endian data and little-
endian instructions then it should be assembled with the ‘-EB’ option, (all of
Chapter 9: Machine Dependent Features 113
it, code and data) and then linked with the ‘--be8’ option. This will reverse
the endianness of the instructions back to little-endian, but leave the data as
big-endian.
-EL This option specifies that the output generated by the assembler should be
marked as being encoded for a little-endian processor.
-k This option specifies that the output of the assembler should be marked as
position-independent code (PIC).
--fix-v4bx
Allow BX instructions in ARMv4 code. This is intended for use with the linker
option of the same name.
-mwarn-deprecated
-mno-warn-deprecated
Enable or disable warnings about using deprecated options or features. The
default is to warn.
-mccs Turns on CodeComposer Studio assembly syntax compatibility mode.
-mwarn-syms
-mno-warn-syms
Enable or disable warnings about symbols that match the names of ARM in-
structions. The default is to warn.
9.4.2 Syntax
9.4.2.1 Instruction Set Syntax
Two slightly different syntaxes are support for ARM and THUMB instructions. The default,
divided, uses the old style where ARM and THUMB instructions had their own, separate
syntaxes. The new, unified syntax, which can be selected via the .syntax directive, and
has the following main features:
• Immediate operands do not require a # prefix.
• The IT instruction may appear, and if it does it is validated against subsequent condi-
tional affixes. In ARM mode it does not generate machine code, in THUMB mode it
does.
• For ARM instructions the conditional affixes always appear at the end of the instruc-
tion. For THUMB instructions conditional affixes can be used, but only inside the
scope of an IT instruction.
• All of the instructions new to the V6T2 architecture (and later) are available. (Only a
few such instructions can be written in the divided syntax).
• The .N and .W suffixes are recognized and honored.
• All instructions set the flags if and only if they have an s affix.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment,
but in this case the line could also be a logical line number directive (see Section 3.3
[Comments], page 29) or a preprocessor control command (see Section 3.1 [Preprocessing],
page 29).
The ‘;’ character can be used instead of a newline to separate statements.
Either ‘#’ or ‘$’ can be used to indicate immediate operands.
*TODO* Explain about /data modifier on symbols.
z .dn d4.f32[1]
vmul x,y,z
This is equivalent to writing the following:
vmul.f32 d2,d3,d4[1]
Aliases created using dn or qn can be destroyed using unreq.
.eabi_attribute tag , value
Set the EABI object attribute tag to value.
The tag is either an attribute number, or one of the following: Tag_
CPU_raw_name, Tag_CPU_name, Tag_CPU_arch, Tag_CPU_arch_profile,
Tag_ARM_ISA_use, Tag_THUMB_ISA_use, Tag_FP_arch, Tag_WMMX_arch,
Tag_Advanced_SIMD_arch, Tag_PCS_config, Tag_ABI_PCS_R9_use,
Tag_ABI_PCS_RW_data, Tag_ABI_PCS_RO_data, Tag_ABI_PCS_GOT_use,
Tag_ABI_PCS_wchar_t, Tag_ABI_FP_rounding, Tag_ABI_FP_denormal,
Tag_ABI_FP_exceptions, Tag_ABI_FP_user_exceptions, Tag_ABI_FP_
number_model, Tag_ABI_align_needed, Tag_ABI_align_preserved,
Tag_ABI_enum_size, Tag_ABI_HardFP_use, Tag_ABI_VFP_args,
Tag_ABI_WMMX_args, Tag_ABI_optimization_goals, Tag_ABI_FP_
optimization_goals, Tag_compatibility, Tag_CPU_unaligned_access,
Tag_FP_HP_extension, Tag_ABI_FP_16bit_format, Tag_MPextension_
use, Tag_DIV_use, Tag_nodefaults, Tag_also_compatible_with,
Tag_conformance, Tag_T2EE_use, Tag_Virtualization_use
The value is either a number, "string", or number, "string" depending on
the tag.
Note - the following legacy values are also accepted by tag: Tag_VFP_arch, Tag_
ABI_align8_needed, Tag_ABI_align8_preserved, Tag_VFP_HP_extension,
.even This directive aligns to an even-numbered address.
.extend expression [, expression ]*
.ldouble expression [, expression ]*
These directives write 12byte long double floating-point values to the output
section. These are not compatible with current ARM processors or ABIs.
.fnend Marks the end of a function with an unwind table entry. The unwind index
table entry is created when this directive is processed.
If no personality routine has been specified then standard personality routine
0 or 1 will be used, depending on the number of unwind opcodes required.
.fnstart Marks the start of a function with an unwind table entry.
.force_thumb
This directive forces the selection of Thumb instructions, even if the target
processor does not support those instructions
.fpu name
Select the floating-point unit to assemble for. Valid values for name are the
same as for the ‘-mfpu’ commandline option.
Chapter 9: Machine Dependent Features 117
.handlerdata
Marks the end of the current function, and the start of the exception table entry
for that function. Anything between this directive and the .fnend directive will
be added to the exception table entry.
Must be preceded by a .personality or .personalityindex directive.
.inst opcode [ , ... ]
.inst.n opcode [ , ... ]
.inst.w opcode [ , ... ]
Generates the instruction corresponding to the numerical value opcode.
.inst.n and .inst.w allow the Thumb instruction size to be specified
explicitly, overriding the normal encoding rules.
.ldouble expression [, expression ]*
See .extend.
.ltorg This directive causes the current contents of the literal pool to be dumped into
the current section (which is assumed to be the .text section) at the current
location (aligned to a word boundary). GAS maintains a separate literal pool
for each section and each sub-section. The .ltorg directive will only affect the
literal pool of the current section and sub-section. At the end of assembly all
remaining, un-empty literal pools will automatically be dumped.
Note - older versions of GAS would dump the current literal pool any time a
section change occurred. This is no longer done, since it prevents accurate
control of the placement of literal pools.
.movsp reg [, #offset ]
Tell the unwinder that reg contains an offset from the current stack pointer. If
offset is not specified then it is assumed to be zero.
.object_arch name
Override the architecture recorded in the EABI object attribute section. Valid
values for name are the same as for the .arch directive. Typically this is useful
when code uses runtime detection of CPU features.
.packed expression [, expression ]*
This directive writes 12-byte packed floating-point values to the output section.
These are not compatible with current ARM processors or ABIs.
.pad #count
Generate unwinder annotations for a stack adjustment of count bytes. A posi-
tive value indicates the function prologue allocated stack space by decrementing
the stack pointer.
.personality name
Sets the personality routine for the current function to name.
.personalityindex index
Sets the personality routine for the current function to the EABI standard
routine number index
.pool This is a synonym for .ltorg.
118 Using as
.save reglist
Generate unwinder annotations to restore the registers in reglist. The format
of reglist is the same as the corresponding store-multiple instruction.
core registers
.save {r4, r5, r6, lr}
stmfd sp!, {r4, r5, r6, lr}
FPA registers
.save f4, 2
sfmfd f4, 2, [sp]!
VFP registers
.save {d8, d9, d10}
fstmdx sp!, {d8, d9, d10}
iWMMXt registers
.save {wr10, wr11}
wstrd wr11, [sp, #-8]!
wstrd wr10, [sp, #-8]!
or
.save wr11
wstrd wr11, [sp, #-8]!
.save wr10
wstrd wr10, [sp, #-8]!
This directive is not necessary when generating EABI objects. On these targets
the encoding is implicit when generating Thumb code.
.thumb_set
This performs the equivalent of a .set directive in that it creates a symbol
which is an alias for another symbol (possibly not yet defined). This directive
also has the added property in that it marks the aliased symbol as being a
thumb function entry point, in the same way that the .thumb_func directive
does.
.tlsdescseq tls-variable
This directive is used to annotate parts of an inlined TLS descriptor trampoline.
Normally the trampoline is provided by the linker, and this directive is not
needed.
.unreq alias-name
This undefines a register alias which was previously defined using the req, dn
or qn directives. For example:
foo .req r0
.unreq foo
An error occurs if the name is undefined. Note - this pseudo op can be used to
delete builtin in register name aliases (eg ’r0’). This should only be done if it
is really necessary.
.unwind_raw offset , byte1 , ...
Insert one of more arbitrary unwind opcode bytes, which are known to adjust
the stack pointer by offset bytes.
For example .unwind_raw 4, 0xb1, 0x01 is equivalent to .save {r0}
.vsave vfp-reglist
Generate unwinder annotations to restore the VFP registers in vfp-reglist using
FLDMD. Also works for VFPv3 registers that are to be restored using VLDM.
The format of vfp-reglist is the same as the corresponding store-multiple in-
struction.
VFP registers
.vsave {d8, d9, d10}
fstmdd sp!, {d8, d9, d10}
VFPv3 registers
.vsave {d15, d16, d17}
vstm sp!, {d15, d16, d17}
Since FLDMX and FSTMX are now deprecated, this directive should be used
in favour of .save for saving VFP registers for ARMv6 and above.
9.4.5 Opcodes
as implements all the standard ARM opcodes. It also implements several pseudo opcodes,
including several synthetic load instructions.
NOP
nop
This pseudo op will always evaluate to a legal ARM instruction that does noth-
ing. Currently it will evaluate to MOV r0, r0.
120 Using as
LDR
ldr <register> , = <expression>
If expression evaluates to a numeric constant then a MOV or MVN instruction
will be used in place of the LDR instruction, if the constant can be generated
by either of these instructions. Otherwise the constant will be placed into the
nearest literal pool (if it not already there) and a PC relative LDR instruction
will be generated.
ADR
adr <register> <label>
This instruction will load the address of label into the indicated register. The
instruction will evaluate to a PC relative ADD or SUB instruction depending
upon where the label is located. If the label is out of range, or if it is not
defined in the same file (and section) as the ADR instruction, then an error will
be generated. This instruction will not make use of the literal pool.
ADRL
adrl <register> <label>
This instruction will load the address of label into the indicated register. The
instruction will evaluate to one or two PC relative ADD or SUB instructions
depending upon where the label is located. If a second instruction is not needed
a NOP instruction will be generated in its place, so that this instruction is
always 8 bytes long.
If the label is out of range, or if it is not defined in the same file (and section)
as the ADRL instruction, then an error will be generated. This instruction will
not make use of the literal pool.
For information on the ARM or Thumb instruction sets, see ARM Software Development
Toolkit Reference Manual, Advanced RISC Machines Ltd.
9.4.7 Unwinding
The ABI for the ARM Architecture specifies a standard format for exception unwind infor-
mation. This information is used when an exception is thrown to determine where control
should be transferred. In particular, the unwind information is used to determine which
Chapter 9: Machine Dependent Features 121
function called the function that threw the exception, and which function called that one,
and so forth. This information is also used to restore the values of callee-saved registers in
the function catching the exception.
If you are writing functions in assembly code, and those functions call other functions
that throw exceptions, you must use assembly pseudo ops to ensure that appropriate ex-
ception unwind information is generated. Otherwise, if one of the functions called by your
assembly code throws an exception, the run-time library will be unable to unwind the stack
through your assembly code and your program will not behave correctly.
To illustrate the use of these pseudo ops, we will examine the code that G++ generates
for the following C++ input:
void callee (int *);
int
caller ()
{
int i;
callee (&i);
return i;
}
This example does not show how to throw or catch an exception from assembly code.
That is a much more complex operation and should always be done in a high-level language,
such as C++, that directly supports exceptions.
The code generated by one particular version of G++ when compiling the example above
is:
_Z6callerv:
.fnstart
.LFB2:
@ Function supports interworking.
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {fp, lr}
.save {fp, lr}
.LCFI0:
.setfp fp, sp, #4
add fp, sp, #4
.LCFI1:
.pad #8
sub sp, sp, #8
.LCFI2:
sub r3, fp, #8
mov r0, r3
bl _Z6calleePi
ldr r3, [fp, #-8]
mov r0, r3
sub sp, fp, #4
122 Using as
the second argument to compute the value of the frame pointer. You should not modify
the frame pointer in the body of the function.
If you do not use a frame pointer, then you should not use the .setfp pseudo op. If you
do not use a frame pointer, then you should avoid modifying the stack pointer outside of
the function prologue. Otherwise, the run-time library will be unable to find saved registers
when it is unwinding the stack.
The pseudo ops described above are sufficient for writing assembly code that calls func-
tions which may throw exceptions. If you need to know more about the object-file format
used to represent unwind information, you may consult the Exception Handling ABI for
the ARM Architecture available from http://infocenter.arm.com.
124 Using as
9.5.2 Syntax
9.5.2.1 Special Characters
The presence of a ‘;’ anywhere on a line indicates the start of a comment that extends to
the end of that line.
If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but
in this case the line can also be a logical line number directive (see Section 3.3 [Comments],
page 29) or a preprocessor control command (see Section 3.1 [Preprocessing], page 29).
The ‘$’ character can be used instead of a newline to separate statements.
lo8
This modifier allows you to use bits 0 through 7 of an address expression as 8
bit relocatable expression.
hi8
This modifier allows you to use bits 7 through 15 of an address expression as
8 bit relocatable expression. This is useful with, for example, the AVR ‘ldi’
instruction and ‘lo8’ modifier.
For example
ldi r26, lo8(sym+10)
ldi r27, hi8(sym+10)
Chapter 9: Machine Dependent Features 127
hh8
This modifier allows you to use bits 16 through 23 of an address expression as
8 bit relocatable expression. Also, can be useful for loading 32 bit constants.
hlo8
Synonym of ‘hh8’.
hhi8
This modifier allows you to use bits 24 through 31 of an expression as 8 bit
expression. This is useful with, for example, the AVR ‘ldi’ instruction and
‘lo8’, ‘hi8’, ‘hlo8’, ‘hhi8’, modifier.
For example
ldi r26, lo8(285774925)
ldi r27, hi8(285774925)
ldi r28, hlo8(285774925)
ldi r29, hhi8(285774925)
; r29,r28,r27,r26 = 285774925
pm_lo8
This modifier allows you to use bits 0 through 7 of an address expression as
8 bit relocatable expression. This modifier useful for addressing data or code
from Flash/Program memory. The using of ‘pm_lo8’ similar to ‘lo8’.
pm_hi8
This modifier allows you to use bits 8 through 15 of an address expression as
8 bit relocatable expression. This modifier useful for addressing data or code
from Flash/Program memory.
pm_hh8
This modifier allows you to use bits 15 through 23 of an address expression as
8 bit relocatable expression. This modifier useful for addressing data or code
from Flash/Program memory.
9.5.3 Opcodes
For detailed information on the AVR machine instruction set, see www.atmel.com/products/AVR.
as implements all the standard AVR opcodes. The following table summarizes the AVR
opcodes, and their arguments.
Legend:
r any register
d ‘ldi’ register (r16-r31)
v ‘movw’ even register (r0, r2, ..., r28, r30)
a ‘fmul’ register (r16-r23)
w ‘adiw’ register (r24,r26,r28,r30)
e pointer registers (X,Y,Z)
b base pointer register and displacement ([YZ]+disp)
z Z pointer register (for [e]lpm Rd,Z[+])
M immediate value from 0 to 255
n immediate value from 0 to 255 ( n = ~M ). Relocation impossible
s immediate value from 0 to 7
P Port address value from 0 to 63. (in, out)
p Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
128 Using as
1001010010001000 clc
1001010011011000 clh
1001010011111000 cli
1001010010101000 cln
1001010011001000 cls
1001010011101000 clt
1001010010111000 clv
1001010010011000 clz
1001010000001000 sec
1001010001011000 seh
1001010001111000 sei
1001010000101000 sen
1001010001001000 ses
1001010001101000 set
1001010000111000 sev
1001010000011000 sez
100101001SSS1000 bclr S
100101000SSS1000 bset S
1001010100001001 icall
1001010000001001 ijmp
1001010111001000 lpm ?
1001000ddddd010+ lpm r,z
1001010111011000 elpm ?
1001000ddddd011+ elpm r,z
0000000000000000 nop
1001010100001000 ret
1001010100011000 reti
1001010110001000 sleep
1001010110011000 break
1001010110101000 wdr
1001010111101000 spm
000111rdddddrrrr adc r,r
000011rdddddrrrr add r,r
001000rdddddrrrr and r,r
000101rdddddrrrr cp r,r
000001rdddddrrrr cpc r,r
000100rdddddrrrr cpse r,r
001001rdddddrrrr eor r,r
001011rdddddrrrr mov r,r
100111rdddddrrrr mul r,r
001010rdddddrrrr or r,r
000010rdddddrrrr sbc r,r
000110rdddddrrrr sub r,r
001001rdddddrrrr clr r
000011rdddddrrrr lsl r
000111rdddddrrrr rol r
001000rdddddrrrr tst r
0111KKKKddddKKKK andi d,M
0111KKKKddddKKKK cbr d,n
1110KKKKddddKKKK ldi d,M
Chapter 9: Machine Dependent Features 129
11101111dddd1111 ser d
0110KKKKddddKKKK ori d,M
0110KKKKddddKKKK sbr d,M
0011KKKKddddKKKK cpi d,M
0100KKKKddddKKKK sbci d,M
0101KKKKddddKKKK subi d,M
1111110rrrrr0sss sbrc r,s
1111111rrrrr0sss sbrs r,s
1111100ddddd0sss bld r,s
1111101ddddd0sss bst r,s
10110PPdddddPPPP in r,P
10111PPrrrrrPPPP out P,r
10010110KKddKKKK adiw w,K
10010111KKddKKKK sbiw w,K
10011000pppppsss cbi p,s
10011010pppppsss sbi p,s
10011001pppppsss sbic p,s
10011011pppppsss sbis p,s
111101lllllll000 brcc l
111100lllllll000 brcs l
111100lllllll001 breq l
111101lllllll100 brge l
111101lllllll101 brhc l
111100lllllll101 brhs l
111101lllllll111 brid l
111100lllllll111 brie l
111100lllllll000 brlo l
111100lllllll100 brlt l
111100lllllll010 brmi l
111101lllllll001 brne l
111101lllllll010 brpl l
111101lllllll000 brsh l
111101lllllll110 brtc l
111100lllllll110 brts l
111101lllllll011 brvc l
111100lllllll011 brvs l
111101lllllllsss brbc s,l
111100lllllllsss brbs s,l
1101LLLLLLLLLLLL rcall L
1100LLLLLLLLLLLL rjmp L
1001010hhhhh111h call h
1001010hhhhh110h jmp h
1001010rrrrr0101 asr r
1001010rrrrr0000 com r
1001010rrrrr1010 dec r
1001010rrrrr0011 inc r
1001010rrrrr0110 lsr r
1001010rrrrr0001 neg r
1001000rrrrr1111 pop r
1001001rrrrr1111 push r
1001010rrrrr0111 ror r
1001010rrrrr0010 swap r
00000001ddddrrrr movw v,v
00000010ddddrrrr muls d,d
000000110ddd0rrr mulsu a,a
000000110ddd1rrr fmul a,a
000000111ddd0rrr fmuls a,a
000000111ddd1rrr fmulsu a,a
130 Using as
-mno-fdpic
-mnopic Disable -mfdpic.
9.6.2 Syntax
Special Characters
Assembler input is free format and may appear anywhere on the line. One
instruction may extend across multiple lines or more than one instruction may
appear on the same line. White space (space, tab, comments or newline) may
appear anywhere between tokens. A token must not have embedded spaces.
Tokens include numbers, register names, keywords, user identifiers, and also
some multicharacter special symbols like "+=", "/*" or "||".
Comments are introduced by the ‘#’ character and extend to the end of the
current line. If the ‘#’ appears as the first character of a line, the whole line is
treated as a comment, but in this case the line can also be a logical line num-
ber directive (see Section 3.3 [Comments], page 29) or a preprocessor control
command (see Section 3.1 [Preprocessing], page 29).
Instruction Delimiting
A semicolon must terminate every instruction. Sometimes a complete instruc-
tion will consist of more than one operation. There are two cases where this
occurs. The first is when two general operations are combined. Normally a
comma separates the different parts, as in
a0= r3.h * r2.l, a1 = r3.l * r2.h ;
The second case occurs when a general instruction is combined with one or two
memory references for joint issue. The latter portions are set off by a "||"
token.
a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
Multiple instructions can occur on the same line. Each must be terminated by
a semicolon character.
132 Using as
Register Names
The assembler treats register names and instruction keywords in a case insensi-
tive manner. User identifiers are case sensitive. Thus, R3.l, R3.L, r3.l and r3.L
are all equivalent input to the assembler.
Register names are reserved and may not be used as program identifiers.
Some operations (such as "Move Register") require a register pair. Register
pairs are always data registers and are denoted using a colon, eg., R3:2. The
larger number must be written firsts. Note that the hardware only supports
odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
Some instructions (such as –SP (Push Multiple)) require a group of adjacent
registers. Adjacent registers are denoted in the syntax by the range enclosed
in parentheses and separated by a colon, eg., (R7:3). Again, the larger number
appears first.
Portions of a particular register may be individually specified. This is written
with a dot (".") following the register name and then a letter denoting the
desired portion. For 32-bit registers, ".H" denotes the most significant ("High")
portion. ".L" denotes the least-significant portion. The subdivisions of the 40-
bit registers are described later.
Accumulators
The set of 40-bit registers A1 and A0 that normally contain data that is being
manipulated. Each accumulator can be accessed in four ways.
one 40-bit register
The register will be referred to as A1 or A0.
one 32-bit register
The registers are designated as A1.W or A0.W.
two 16-bit registers
The registers are designated as A1.H, A1.L, A0.H or A0.L.
one 8-bit register
The registers are designated as A1.X or A0.X for the bits that
extend beyond bit 31.
Data Registers
The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that normally
contain data for manipulation. These are abbreviated as D-register or Dreg.
Data registers can be accessed as 32-bit registers or as two independent 16-bit
registers. The least significant 16 bits of each register is called the "low" half
and is designated with ".L" following the register name. The most significant
16 bits are called the "high" half and is designated with ".H" following the
name.
R7.L, r2.h, r4.L, R0.H
Pointer Registers
The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that normally
contain byte addresses of data structures. These are abbreviated as P-register
or Preg.
Chapter 9: Machine Dependent Features 133
Stack Pointer SP
The stack pointer contains the 32-bit address of the last occupied byte location
in the stack. The stack grows by decrementing the stack pointer.
Frame Pointer FP
The frame pointer contains the 32-bit address of the previous frame pointer in
the stack. It is located at the top of a frame.
Loop Top LT0 and LT1. These registers contain the 32-bit address of the top of a zero
overhead loop.
Loop Count
LC0 and LC1. These registers contain the 32-bit counter of the zero overhead
loop executions.
Loop Bottom
LB0 and LB1. These registers contain the 32-bit address of the bottom of a
zero overhead loop.
Index Registers
The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte addresses
of data structures. Abbreviated I-register or Ireg.
Modify Registers
The set of 32-bit registers (M0, M1, M2, M3) that normally contain offset values
that are added and subtracted to one of the index registers. Abbreviated as
Mreg.
Length Registers
The set of 32-bit registers (L0, L1, L2, L3) that normally contain the length
in bytes of the circular buffer. Abbreviated as Lreg. Clear the Lreg to disable
circular addressing for the corresponding Ireg.
Base Registers
The set of 32-bit registers (B0, B1, B2, B3) that normally contain the base
address in bytes of the circular buffer. Abbreviated as Breg.
Floating Point
The Blackfin family has no hardware floating point but the .float directive gen-
erates ieee floating point numbers for use with software floating point libraries.
Blackfin Opcodes
For detailed information on the Blackfin machine instruction set, see the Black-
fin(r) Processor Instruction Set Reference.
9.6.3 Directives
The following directives are provided for compatibility with the VDSP assembler.
.byte2 Initializes a two byte data object.
This maps to the .short directive.
134 Using as
‘Displacement Operand: l’
24 bits.
For example:
1 movw $_myfun@c,r1
2 movd $_myfun@c,(r2,r1)
3 _myfun_ptr:
.long _myfun@c
loadd _myfun_ptr, (r1,r0)
jal (r1,r0)
This .long directive, the address of _myfunc, shifted right by 1 at link time.
This loads the address of _data1, into global offset table (ie GOT) and its off-
set value from GOT loads into register-pair r2-r1.
This loads the address of _myfun, shifted right by 1, into global off-
set table (ie GOT) and its offset value from GOT loads into register-pair r1-
r0.
9.8.3 Symbols
Some symbols are defined by the assembler. They’re intended to be used in conditional
assembly, for example:
.if ..asm.arch.cris.v32
code for CRIS v32
.elseif ..asm.arch.cris.common_v10_v32
code common to CRIS v32 and CRIS v10
.elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
code for v10
.else
.error "Code needs to be added here."
.endif
These symbols are defined in the assembler, reflecting command-line options, either when
specified or the default. They are always defined, to 0 or 1.
..asm.arch.cris.any_v0_v10
This symbol is non-zero when ‘--march=v0_v10’ is specified or the default.
..asm.arch.cris.common_v10_v32
Set according to the option ‘--march=common_v10_v32’.
..asm.arch.cris.v10
Reflects the option ‘--march=v10’.
..asm.arch.cris.v32
Corresponds to ‘--march=v10’.
Speaking of symbols, when a symbol is used in code, it can have a suffix modifying its
value for use in position-independent code. See Section 9.8.4.2 [CRIS-Pic], page 139.
Chapter 9: Machine Dependent Features 139
9.8.4 Syntax
There are different aspects of the CRIS assembly syntax.
PLTG
Like PLT, but the value is relative to the beginning of the global offset
table. The relocation is ‘R_CRIS_32_PLT_GOTREL’. Example: move.d
fnname:PLTG,$r3
GOTPLT
Similar to ‘PLT’, but the value of the symbol is a 32-bit index into the global
offset table. This is somewhat of a mix between the effect of the ‘GOT’ and
the ‘PLT’ suffix; the difference to ‘GOT’ is that there will be a procedure linkage
table entry created, and that the symbol is assumed to be a function entry
and will be resolved by the run-time resolver as with ‘PLT’. The relocation is
‘R_CRIS_32_GOTPLT’. Example: jsr [$r0+fnname:GOTPLT]
GOTPLT16
A variant of ‘GOTPLT’ giving a 16-bit value. Its relocation name is
‘R_CRIS_16_GOTPLT’. Example: jsr [$r0+fnname:GOTPLT16]
GOTOFF
This suffix must only be attached to a local symbol, but may be used in an
expression adding an offset. The value is the address of the symbol relative to
the start of the global offset table. The relocation name is ‘R_CRIS_32_GOTREL’.
Example: move.d [$r0+localsym:GOTOFF],r3
‘-O’ The D10V can often execute two sub-instructions in parallel. When this option
is used, as will attempt to optimize its output by detecting when instructions
can be executed in parallel.
‘--nowarnswap’
To optimize execution performance, as will sometimes swap the order of in-
structions. Normally this generates a warning. When this option is used, no
warning will be generated when instructions are swapped.
‘--gstabs-packing’
‘--no-gstabs-packing’
as packs adjacent short instructions into a single packed instruction.
‘--no-gstabs-packing’ turns instruction packing off if ‘--gstabs’ is specified
as well; ‘--gstabs-packing’ (the default) turns instruction packing on even
when ‘--gstabs’ is specified.
9.9.2 Syntax
The D10V syntax is based on the syntax in Mitsubishi’s D10V architecture manual. The
differences are detailed below.
9.9.2.2 Sub-Instructions
The D10V assembler takes as input a series of instructions, either one-per-line, or in the
special two-per-line format described in the next section. Some of these instructions will
be short-form or sub-instructions. These sub-instructions can be packed into a single in-
struction. The assembler will do this automatically. It will also detect when it should not
pack instructions. For example, when a label is defined, the next instruction will never be
packaged with the previous one. Whenever a branch and link instruction is called, it will
not be packaged with the next instruction so the return address will be valid. Nops are
automatically inserted when necessary.
Chapter 9: Machine Dependent Features 143
If you do not want the assembler automatically making these decisions, you can control
the packaging and execution type (parallel or sequential) with the special execution symbols
described in the next section.
‘||’ Parallel
The D10V syntax allows either one instruction per line, one instruction per line with the
execution symbol, or two instructions per line. For example
ld2w r2,@r8+ ||
mac a0,r0,r7
Two-line format. Execute these in parallel.
ld2w r2,@r8+
mac a0,r0,r7
Two-line format. Execute these sequentially. Assembler will put them in the
proper containers.
Since ‘$’ has no special meaning, you may use it in symbol names.
144 Using as
9.9.4 Opcodes
For detailed information on the D10V machine instruction set, see D10V Architecture: A
VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). as imple-
ments all the standard D10V opcodes. The only changes are those described in the section
on size modifiers
146 Using as
9.10.2 Syntax
The D30V syntax is based on the syntax in Mitsubishi’s D30V architecture manual. The
differences are detailed below.
9.10.2.2 Sub-Instructions
The D30V assembler takes as input a series of instructions, either one-per-line, or in the
special two-per-line format described in the next section. Some of these instructions will
be short-form or sub-instructions. These sub-instructions can be packed into a single in-
struction. The assembler will do this automatically. It will also detect when it should not
pack instructions. For example, when a label is defined, the next instruction will never be
packaged with the previous one. Whenever a branch and link instruction is called, it will
not be packaged with the next instruction so the return address will be valid. Nops are
automatically inserted when necessary.
If you do not want the assembler automatically making these decisions, you can control
the packaging and execution type (parallel or sequential) with the special execution symbols
described in the next section.
If a ‘#’ appears as the first character of a line, the whole line is treated as a comment, but
in this case the line could also be a logical line number directive (see Section 3.3 [Comments],
page 29) or a preprocessor control command (see Section 3.1 [Preprocessing], page 29).
Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions
listed in the standard one-per-line format will be executed sequentially unless you use the
‘-O’ option.
To specify the executing order, use the following symbols:
‘->’ Sequential with instruction on the left first.
‘<-’ Sequential with instruction on the right first.
‘||’ Parallel
The D30V syntax allows either one instruction per line, one instruction per line with the
execution symbol, or two instructions per line. For example
abs r2,r3 -> abs r4,r5
Execute these sequentially. The instruction on the right is in the right container
and is executed second.
abs r2,r3 <- abs r4,r5
Execute these reverse-sequentially. The instruction on the right is in the right
container, and is executed first.
abs r2,r3 || abs r4,r5
Execute these in parallel.
ldw r2,@(r3,r4) ||
mulx r6,r8,r9
Two-line format. Execute these in parallel.
mulx a0,r8,r9
stw r2,@(r3,r4)
Two-line format. Execute these sequentially unless ‘-O’ option is used. If the
‘-O’ option is used, the assembler will determine if the instructions could be
done in parallel (the above two instructions can be done in parallel), and if so,
emit them as parallel instructions. The assembler will put them in the proper
containers. In the above example, the assembler will put the ‘stw’ instruction
in left container and the ‘mulx’ instruction in the right container.
stw r2,@(r3,r4) ->
mulx a0,r8,r9
Two-line format. Execute the ‘stw’ instruction followed by the ‘mulx’ instruc-
tion sequentially. The first instruction goes in the left container and the second
instruction goes into right container. The assembler will give an error if the
machine ordering constraints are violated.
stw r2,@(r3,r4) <-
mulx a0,r8,r9
Same as previous example, except that the ‘mulx’ instruction is executed before
the ‘stw’ instruction.
Since ‘$’ has no special meaning, you may use it in symbol names.
148 Using as
9.10.4 Opcodes
For detailed information on the D30V machine instruction set, see D30V Architecture: A
VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). as imple-
ments all the standard D30V opcodes. The only changes are those described in the section
on size modifiers
150 Using as
-h-tick-hex
Support H’00 style hex constants in addition to 0x00 style.
-mach=name
Sets the H8300 machine variant. The following machine names are recognised:
h8300h, h8300hn, h8300s, h8300sn, h8300sx and h8300sxn.
9.12.2 Syntax
9.12.2.1 Special Characters
‘;’ is the line comment character.
‘$’ can be used instead of a newline to separate statements. Therefore you may not use
‘$’ in symbol names on the H8/300.
rn Register direct
@rn Register indirect
@(d , rn )
@(d :16, rn )
@(d :24, rn )
Register indirect: 16-bit or 24-bit displacement d from register n. (24-bit dis-
placements are only meaningful on the H8/300H.)
@rn + Register indirect with post-increment
@-rn Register indirect with pre-decrement
152 Using as
@aa
@aa :8
@aa :16
@aa :24 Absolute address aa. (The address size ‘:24’ only makes sense on the H8/300H.)
#xx
#xx :8
#xx :16
#xx :32 Immediate data xx. You may specify the ‘:8’, ‘:16’, or ‘:32’ for clarity, if you
wish; but as neither requires this nor uses it—the data size required is taken
from context.
@@aa
@@aa :8 Memory indirect. You may specify the ‘:8’ for clarity, if you wish; but as
neither requires this nor uses it.
9.12.5 Opcodes
For detailed information on the H8/300 machine instruction set, see H8/300 Series Program-
ming Manual. For information specific to the H8/300H, see H8/300H Series Programming
Manual (Renesas).
as implements all the standard H8/300 opcodes. No additional pseudo-instructions are
needed on this family.
Four H8/300 instructions (add, cmp, mov, sub) are defined with variants using the suffixes
‘.b’, ‘.w’, and ‘.l’ to specify the size of a memory operand. as supports these suffixes, but
does not require them; since one of the operands is always a register, as can deduce the
correct size.
For example, since r0 refers to a 16-bit register,
mov r0,@foo
is equivalent to
mov.w r0,@foo
If you use the size suffixes, as issues a warning when the suffix and the register size do
not match.
154 Using as
9.13.2 Options
as has no machine-dependent command-line options for the HPPA.
9.13.3 Syntax
The assembler syntax closely follows the HPPA instruction set reference manual; assembler
directives and general syntax closely follow the HPPA assembly language reference manual,
with a few noteworthy differences.
First, a colon may immediately follow a label definition. This is simply for compatibility
with how most assembly language programmers write code.
Some obscure expression parsing problems may affect hand written code which uses the
spop instructions, or code which makes significant use of the ! line separator.
as is much less forgiving about missing arguments and other similar oversights than the
HP assembler. as notifies you of missing arguments as syntax errors; this is regarded as a
feature, not a bug.
Finally, as allows you to use an external symbol without explicitly importing the symbol.
Warning: in the future this will be an error for HPPA targets.
Special characters for HPPA targets include:
‘;’ is the line comment character.
‘!’ can be used instead of a newline to separate statements.
Since ‘$’ has no special meaning, you may use it in symbol names.
.endm .liston
.enter .locct
.leave .macro
.listoff
Beyond those implemented for compatibility, as supports one additional assembler di-
rective for the HPPA: .param. It conveys register argument locations for static functions.
Its syntax closely follows the .export directive.
These are the additional directives in as for the HPPA:
.block n
.blockz n
Reserve n bytes of storage, and initialize them to zero.
.call Mark the beginning of a procedure call. Only the special case with no arguments
is allowed.
.callinfo [ param =value , ... ] [ flag , ... ]
Specify a number of parameters and flags that define the environment for a
procedure.
param may be any of ‘frame’ (frame size), ‘entry_gr’ (end of general regis-
ter range), ‘entry_fr’ (end of float register range), ‘entry_sr’ (end of space
register range).
The values for flag are ‘calls’ or ‘caller’ (proc has subroutines), ‘no_calls’
(proc does not call subroutines), ‘save_rp’ (preserve return pointer), ‘save_sp’
(proc preserves stack pointer), ‘no_unwind’ (do not unwind this proc),
‘hpux_int’ (proc is interrupt routine).
.code Assemble into the standard section called ‘$TEXT$’, subsection ‘$CODE$’.
.copyright "string "
In the SOM object format, insert string into the object code, marked as a
copyright string.
.copyright "string "
In the ELF object format, insert string into the object code, marked as a version
string.
.enter Not yet supported; the assembler rejects programs containing this directive.
.entry Mark the beginning of a procedure.
.exit Mark the end of a procedure.
.export name [ ,typ ] [ ,param =r ]
Make a procedure name available to callers. typ, if present, must be one
of ‘absolute’, ‘code’ (ELF only, not SOM), ‘data’, ‘entry’, ‘data’, ‘entry’,
‘millicode’, ‘plabel’, ‘pri_prog’, or ‘sec_prog’.
param, if present, provides either relocation information for the procedure ar-
guments and result, or a privilege level. param may be ‘argwn ’ (where n ranges
from 0 to 3, and indicates one of four one-word arguments); ‘rtnval’ (the pro-
cedure’s result); or ‘priv_lev’ (privilege level). For arguments or the result, r
156 Using as
specifies how to relocate, and must be one of ‘no’ (not relocatable), ‘gr’ (argu-
ment is in general register), ‘fr’ (in floating point register), or ‘fu’ (upper half
of float register). For ‘priv_lev’, r is an integer.
.half n Define a two-byte integer constant n; synonym for the portable as directive
.short.
.import name [ ,typ ]
Converse of .export; make a procedure available to call. The arguments use
the same conventions as the first two arguments for .export.
.label name
Define name as a label for the current assembly location.
.leave Not yet supported; the assembler rejects programs containing this directive.
.origin lc
Advance location counter to lc. Synonym for the as portable directive .org.
.param name [ ,typ ] [ ,param =r ]
Similar to .export, but used for static procedures.
.proc Use preceding the first statement of a procedure.
.procend Use following the last statement of a procedure.
label .reg expr
Synonym for .equ; define label with the absolute expression expr as its value.
.space secname [ ,params ]
Switch to section secname, creating a new section by that name if necessary.
You may only use params when creating a new section, not when switching
to an existing one. secname may identify a section by number rather than by
name.
If specified, the list params declares attributes of the section, identified by key-
words. The keywords recognized are ‘spnum=exp ’ (identify this section by the
number exp, an absolute expression), ‘sort=exp ’ (order sections according to
this sort key when linking; exp is an absolute expression), ‘unloadable’ (sec-
tion contains no loadable data), ‘notdefined’ (this section defined elsewhere),
and ‘private’ (data in this section not available to other programs).
.spnum secnam
Allocate four bytes of storage, and initialize them with the section number of
the section named secnam. (You can define the section number with the HPPA
.space directive.)
.string "str "
Copy the characters in the string str to the object file. See Section 3.6.1.1
[Strings], page 31, for information on escape sequences you can use in as strings.
Warning! The HPPA version of .string differs from the usual as definition:
it does not write a zero byte after copying str.
.stringz "str "
Like .string, but appends a zero byte after copying str to object file.
Chapter 9: Machine Dependent Features 157
9.13.6 Opcodes
For detailed information on the HPPA machine instruction set, see PA-RISC Architecture
and Instruction Set Reference Manual (HP 09740-90039).
Chapter 9: Machine Dependent Features 159
9.14.2 Options
as has no machine-dependent command-line options for the ESA/390.
9.14.3 Syntax
The opcode/operand syntax follows the ESA/390 Principles of Operation manual; assembler
directives and general syntax are loosely based on the prevailing AT&T/SVR4/ELF/Solaris
style notation. HLASM-style directives are not supported for the most part, with the
exception of those described herein.
A leading dot in front of directives is optional, and the case of directives is ignored; thus
for example, .using and USING have the same effect.
A colon may immediately follow a label definition. This is simply for compatibility with
how most assembly language programmers write code.
‘#’ is the line comment character.
‘;’ can be used instead of a newline to separate statements.
Since ‘$’ has no special meaning, you may use it in symbol names.
Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6. By using these
symbolic names, as can detect simple syntax errors. The name rarg or r.arg is a synonym
for r11, rtca or r.tca for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base for
r3 and rpgt or r.pgt for r4.
‘*’ is the current location counter. Unlike ‘.’ it is always relative to the last USING di-
rective. Note that this means that expressions cannot use multiplication, as any occurrence
of ‘*’ will be interpreted as a location counter.
All labels are relative to the last USING. Thus, branches to a label always imply the use
of base+displacement.
Many of the usual forms of address constants / address literals are supported. Thus,
.using *,r3
L r15,=A(some_routine)
LM r6,r7,=V(some_longlong_extern)
A r1,=F’12’
AH r0,=H’42’
ME r6,=E’3.1416’
MD r6,=D’3.14159265358979’
160 Using as
O r6,=XL4’cacad0d0’
.ltorg
should all behave as expected: that is, an entry in the literal pool will be created (or
reused if it already exists), and the instruction operands will be the displacement into the
literal pool using the current base register (as last declared with the .using directive).
is, the constants =A(some_routine), =H’42’ and =E’3.1416’ will all appear
in the .data section.
.data
.using LITPOOL,r4
.text
BASR r3,0
.using *,r3
B START
.long LITPOOL
START:
L r4,4(,r3)
L r15,=A(some_routine)
LTR r15,r15
BNE LABEL
AH r0,=H’42’
LABEL:
ME r6,=E’3.1416’
.data
LITPOOL:
.ltorg
Note that this dual-.using directive semantics extends and is not compatible
with HLASM semantics. Note that this assembler directive does not support
the full range of HLASM semantics.
9.14.6 Opcodes
For detailed information on the ESA/390 machine instruction set, see ESA/390 Principles
of Operation (IBM Publication Number DZ9AR004).
162 Using as
9.15.1 Options
The i386 version of as has a few machine dependent options:
--32 | --x32 | --64
Select the word size, either 32 bits or 64 bits. ‘--32’ implies Intel i386 archi-
tecture, while ‘--x32’ and ‘--64’ imply AMD x86-64 architecture with 32-bit
or 64-bit word-size respectively.
These options are only available with the ELF object file format, and require
that the necessary BFD support has been included (on a 32-bit platform you
have to add –enable-64-bit-bfd to configure enable 64-bit usage and use x86-64
as target platform).
-n By default, x86 GAS replaces multiple nop instructions used for alignment
within code sections with multi-byte nop instructions such as leal
0(%esi,1),%esi. This switch disables the optimization.
--divide On SVR4-derived platforms, the character ‘/’ is treated as a comment character,
which means that it cannot be used in expressions. The ‘--divide’ option turns
‘/’ into a normal character. This does not disable ‘/’ at the beginning of a line
starting a comment, or affect using ‘#’ for starting a comment.
-march=CPU [+EXTENSION ...]
This option specifies the target processor. The assembler will issue an error
message if an attempt is made to assemble an instruction which will not ex-
ecute on the target processor. The following processor names are recognized:
i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii,
pentiumiii, pentium4, prescott, nocona, core, core2, corei7, l1om, k1om,
iamcu, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, bdver2, bdver3,
bdver4, znver1, btver1, btver2, generic32 and generic64.
In addition to the basic instruction set, the assembler can be told to accept
various extension mnemonics. For example, -march=i686+sse4+vmx extends
i686 with sse4 and vmx. The following extensions are currently supported:
8087, 287, 387, 687, no87, no287, no387, no687, mmx, nommx, sse, sse2,
sse3, ssse3, sse4.1, sse4.2, sse4, nosse, nosse2, nosse3, nossse3,
nosse4.1, nosse4.2, nosse4, avx, avx2, noavx, noavx2, adx, rdseed,
prfchw, smap, mpx, sha, rdpid, ptwrite, cet, gfni, vaes, vpclmulqdq,
prefetchwt1, clflushopt, se1, clwb, avx512f, avx512cd, avx512er,
avx512pf, avx512vl, avx512bw, avx512dq, avx512ifma, avx512vbmi,
avx512_4fmaps, avx512_4vnniw, avx512_vpopcntdq, avx512_vbmi2,
avx512_vnni, avx512_bitalg, noavx512f, noavx512cd, noavx512er,
noavx512pf, noavx512vl, noavx512bw, noavx512dq, noavx512ifma,
noavx512vbmi, noavx512_4fmaps, noavx512_4vnniw, noavx512_vpopcntdq,
noavx512_vbmi2, noavx512_vnni, noavx512_bitalg, vmx, vmfunc, smx,
xsave, xsaveopt, xsavec, xsaves, aes, pclmul, fsgsbase, rdrnd, f16c,
Chapter 9: Machine Dependent Features 163
bmi2, fma, movbe, ept, lzcnt, hle, rtm, invpcid, clflush, mwaitx, clzero,
lwp, fma4, xop, cx16, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, svme,
abm and padlock. Note that rather than extending a basic instruction set, the
extension mnemonics starting with no revoke the respective functionality.
When the .arch directive is used with ‘-march’, the .arch directive will take
precedent.
-mtune=CPU
This option specifies a processor to optimize for. When used in conjunction
with the ‘-march’ option, only instructions of the processor specified by the
‘-march’ option will be generated.
Valid CPU values are identical to the processor list of ‘-march=CPU ’.
-msse2avx
This option specifies that the assembler should encode SSE instructions with
VEX prefix.
-msse-check=none
-msse-check=warning
-msse-check=error
These options control if the assembler should check SSE instructions.
‘-msse-check=none ’ will make the assembler not to check SSE instructions,
which is the default. ‘-msse-check=warning ’ will make the assembler issue
a warning for any SSE instruction. ‘-msse-check=error ’ will make the
assembler issue an error for any SSE instruction.
-mavxscalar=128
-mavxscalar=256
These options control how the assembler should encode scalar AVX instruc-
tions. ‘-mavxscalar=128 ’ will encode scalar AVX instructions with 128bit
vector length, which is the default. ‘-mavxscalar=256 ’ will encode scalar AVX
instructions with 256bit vector length.
-mevexlig=128
-mevexlig=256
-mevexlig=512
These options control how the assembler should encode length-ignored (LIG)
EVEX instructions. ‘-mevexlig=128 ’ will encode LIG EVEX instructions
with 128bit vector length, which is the default. ‘-mevexlig=256 ’ and
‘-mevexlig=512 ’ will encode LIG EVEX instructions with 256bit and 512bit
vector length, respectively.
-mevexwig=0
-mevexwig=1
These options control how the assembler should encode w-ignored (WIG) EVEX
instructions. ‘-mevexwig=0 ’ will encode WIG EVEX instructions with evex.w
= 0, which is the default. ‘-mevexwig=1 ’ will encode WIG EVEX instructions
with evex.w = 1.
164 Using as
-mmnemonic=att
-mmnemonic=intel
This option specifies instruction mnemonic for matching instructions. The
.att_mnemonic and .intel_mnemonic directives will take precedent.
-msyntax=att
-msyntax=intel
This option specifies instruction syntax when processing instructions. The
.att_syntax and .intel_syntax directives will take precedent.
-mnaked-reg
This option specifies that registers don’t require a ‘%’ prefix. The .att_syntax
and .intel_syntax directives will take precedent.
-madd-bnd-prefix
This option forces the assembler to add BND prefix to all branches, even if such
prefix was not explicitly specified in the source code.
-mno-shared
On ELF target, the assembler normally optimizes out non-PLT relocations
against defined non-weak global branch targets with default visibility. The
‘-mshared’ option tells the assembler to generate code which may go into a
shared library where all non-weak global branch targets with default visibility
can be preempted. The resulting code is slightly bigger. This option only affects
the handling of branch instructions.
-mbig-obj
On x86-64 PE/COFF target this option forces the use of big object file format,
which allows more than 32768 sections.
-momit-lock-prefix=no
-momit-lock-prefix=yes
These options control how the assembler should encode lock prefix.
This option is intended as a workaround for processors, that fail on
lock prefix. This option can only be safely used with single-core, single-
thread computers ‘-momit-lock-prefix=yes ’ will omit all lock prefixes.
‘-momit-lock-prefix=no ’ will encode lock prefix as usual, which is the
default.
-mfence-as-lock-add=no
-mfence-as-lock-add=yes
These options control how the assembler should encode lfence, mfence and
sfence. ‘-mfence-as-lock-add=yes ’ will encode lfence, mfence and sfence as
‘lock addl $0x0, (%rsp)’ in 64-bit mode and ‘lock addl $0x0, (%esp)’ in 32-
bit mode. ‘-mfence-as-lock-add=no ’ will encode lfence, mfence and sfence as
usual, which is the default.
-mrelax-relocations=no
-mrelax-relocations=yes
These options control whether the assembler should generate relax
relocations, R 386 GOT32X, in 32-bit mode, or R X86 64 GOTPCRELX and
Chapter 9: Machine Dependent Features 165
instructions with 2 immediate operands, such as the ‘enter’ instruction, do not have
reversed order. Section 9.15.16 [i386-Bugs], page 174.
• In AT&T syntax the size of memory operands is determined from the last character of
the instruction mnemonic. Mnemonic suffixes of ‘b’, ‘w’, ‘l’ and ‘q’ specify byte (8-bit),
word (16-bit), long (32-bit) and quadruple word (64-bit) memory references. Intel syn-
tax accomplishes this by prefixing memory operands (not the instruction mnemonics)
with ‘byte ptr’, ‘word ptr’, ‘dword ptr’ and ‘qword ptr’. Thus, Intel ‘mov al, byte
ptr foo ’ is ‘movb foo , %al’ in AT&T syntax.
In 64-bit code, ‘movabs’ can be used to encode the ‘mov’ instruction with the 64-bit
displacement or immediate operand.
• Immediate form long jumps and calls are ‘lcall/ljmp $section , $offset ’ in AT&T
syntax; the Intel syntax is ‘call/jmp far section :offset ’. Also, the far return in-
struction is ‘lret $stack-adjust ’ in AT&T syntax; Intel syntax is ‘ret far stack-
adjust ’.
• The AT&T assembler does not provide support for multiple section programs. Unix
style systems expect all programs to be single sections.
9.15.4 i386-Mnemonics
9.15.4.1 Instruction Naming
Instruction mnemonics are suffixed with one character modifiers which specify the size of
operands. The letters ‘b’, ‘w’, ‘l’ and ‘q’ specify byte, word, long and quadruple word
operands. If no suffix is specified by an instruction then as tries to fill in the missing
suffix based on the destination register operand (the last one by convention). Thus, ‘mov
%ax, %bx’ is equivalent to ‘movw %ax, %bx’; also, ‘mov $1, %bx’ is equivalent to ‘movw $1,
bx’. Note that this is incompatible with the AT&T Unix assembler which assumes that a
missing mnemonic suffix implies long operand size. (This incompatibility does not affect
compiler output since compilers always explicitly specify the mnemonic suffix.)
Almost all instructions have the same names in AT&T and Intel format. There are a few
exceptions. The sign extend and zero extend instructions need two sizes to specify them.
They need a size to sign/zero extend from and a size to zero extend to. This is accomplished
by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend
and zero extend are ‘movs...’ and ‘movz...’ in AT&T syntax (‘movsx’ and ‘movzx’ in Intel
syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix
Chapter 9: Machine Dependent Features 167
before the to suffix. Thus, ‘movsbl %al, %edx’ is AT&T syntax for “move sign extend from
%al to %edx.” Possible suffixes, thus, are ‘bl’ (from byte to long), ‘bw’ (from byte to word),
‘wl’ (from word to long), ‘bq’ (from byte to quadruple word), ‘wq’ (from word to quadruple
word), and ‘lq’ (from long to quadruple word).
Different encoding options can be specified via pseudo prefixes:
• ‘{disp8}’ – prefer 8-bit displacement.
• ‘{disp32}’ – prefer 32-bit displacement.
• ‘{load}’ – prefer load-form instruction.
• ‘{store}’ – prefer store-form instruction.
• ‘{vex2}’ – prefer 2-byte VEX prefix for VEX instruction.
• ‘{vex3}’ – prefer 3-byte VEX prefix for VEX instruction.
• ‘{evex}’ – encode with EVEX prefix.
The Intel-syntax conversion instructions
• ‘cbw’ — sign-extend byte in ‘%al’ to word in ‘%ax’,
• ‘cwde’ — sign-extend word in ‘%ax’ to long in ‘%eax’,
• ‘cwd’ — sign-extend word in ‘%ax’ to long in ‘%dx:%ax’,
• ‘cdq’ — sign-extend dword in ‘%eax’ to quad in ‘%edx:%eax’,
• ‘cdqe’ — sign-extend dword in ‘%eax’ to quad in ‘%rax’ (x86-64 only),
• ‘cqo’ — sign-extend quad in ‘%rax’ to octuple in ‘%rdx:%rax’ (x86-64 only),
are called ‘cbtw’, ‘cwtl’, ‘cwtd’, ‘cltd’, ‘cltq’, and ‘cqto’ in AT&T naming. as accepts
either naming for these instructions.
Far call/jump instructions are ‘lcall’ and ‘ljmp’ in AT&T syntax, but are ‘call far’
and ‘jump far’ in Intel convention.
• the 5 processor control registers ‘%cr0’, ‘%cr2’, ‘%cr3’, ‘%cr4’, and ‘%cr8’.
• the 6 debug registers ‘%db0’, ‘%db1’, ‘%db2’, ‘%db3’, ‘%db6’, and ‘%db7’.
• the 2 test registers ‘%tr6’ and ‘%tr7’.
• the 8 floating point register stack ‘%st’ or equivalently ‘%st(0)’, ‘%st(1)’, ‘%st(2)’,
‘%st(3)’, ‘%st(4)’, ‘%st(5)’, ‘%st(6)’, and ‘%st(7)’. These registers are overloaded
by 8 MMX registers ‘%mm0’, ‘%mm1’, ‘%mm2’, ‘%mm3’, ‘%mm4’, ‘%mm5’, ‘%mm6’ and ‘%mm7’.
• the 8 128-bit SSE registers registers ‘%xmm0’, ‘%xmm1’, ‘%xmm2’, ‘%xmm3’, ‘%xmm4’, ‘%xmm5’,
‘%xmm6’ and ‘%xmm7’.
The AMD x86-64 architecture extends the register set by:
• enhancing the 8 32-bit registers to 64-bit: ‘%rax’ (the accumulator), ‘%rbx’, ‘%rcx’,
‘%rdx’, ‘%rdi’, ‘%rsi’, ‘%rbp’ (the frame pointer), ‘%rsp’ (the stack pointer)
• the 8 extended registers ‘%r8’–‘%r15’.
• the 8 32-bit low ends of the extended registers: ‘%r8d’–‘%r15d’.
• the 8 16-bit low ends of the extended registers: ‘%r8w’–‘%r15w’.
• the 8 8-bit low ends of the extended registers: ‘%r8b’–‘%r15b’.
• the 4 8-bit registers: ‘%sil’, ‘%dil’, ‘%bpl’, ‘%spl’.
• the 8 debug registers: ‘%db8’–‘%db15’.
• the 8 128-bit SSE registers: ‘%xmm8’–‘%xmm15’.
With the AVX extensions more registers were made available:
• the 16 256-bit SSE ‘%ymm0’–‘%ymm15’ (only the first 8 available in 32-bit mode). The
bottom 128 bits are overlaid with the ‘xmm0’–‘xmm15’ registers.
The AVX2 extensions made in 64-bit mode more registers available:
• the 16 128-bit registers ‘%xmm16’–‘%xmm31’ and the 16 256-bit registers ‘%ymm16’–
‘%ymm31’.
The AVX512 extensions added the following registers:
• the 32 512-bit registers ‘%zmm0’–‘%zmm31’ (only the first 8 available in 32-bit mode).
The bottom 128 bits are overlaid with the ‘%xmm0’–‘%xmm31’ registers and the first 256
bits are overlaid with the ‘%ymm0’–‘%ymm31’ registers.
• the 8 mask registers ‘%k0’–‘%k7’.
• Section override prefixes ‘cs’, ‘ds’, ‘ss’, ‘es’, ‘fs’, ‘gs’. These are automatically added
by specifying using the section:memory-operand form for memory references.
• Operand/Address size prefixes ‘data16’ and ‘addr16’ change 32-bit operands/addresses
into 16-bit operands/addresses, while ‘data32’ and ‘addr32’ change 16-bit ones (in a
.code16 section) into 32-bit operands/addresses. These prefixes must appear on the
same line of code as the instruction they modify. For example, in a 16-bit .code16
section, you might write:
addr32 jmpl *(%ebx)
• The bus lock prefix ‘lock’ inhibits interrupts during execution of the instruction it
precedes. (This is only valid with certain instructions; see a 80386 manual for details).
• The wait for coprocessor prefix ‘wait’ waits for the coprocessor to complete the current
instruction. This should never be needed for the 80386/80387 combination.
• The ‘rep’, ‘repe’, and ‘repne’ prefixes are added to string instructions to make them
repeat ‘%ecx’ times (‘%cx’ times if the current address size is 16-bits).
• The ‘rex’ family of prefixes is used by x86-64 to encode extensions to i386 instruction
set. The ‘rex’ prefix has four bits — an operand size overwrite (64) used to change
operand size from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
register set.
You may write the ‘rex’ prefixes directly. The ‘rex64xyz’ instruction emits ‘rex’ prefix
with all the bits set. By omitting the 64, x, y or z you may write other prefixes as well.
Normally, there is no need to write the prefixes explicitly, since gas will automatically
generate them based on the instruction operands.
Instruction mnemonic suffixes specify the operand’s data type. Constructors build these
data types into memory.
• Floating point constructors are ‘.float’ or ‘.single’, ‘.double’, and ‘.tfloat’ for
32-, 64-, and 80-bit formats. These correspond to instruction mnemonic suffixes ‘s’,
‘l’, and ‘t’. ‘t’ stands for 80-bit (ten byte) real. The 80387 only supports this format
via the ‘fldt’ (load 80-bit real to stack top) and ‘fstpt’ (store 80-bit real and pop
stack) instructions.
• Integer constructors are ‘.word’, ‘.long’ or ‘.int’, and ‘.quad’ for the 16-, 32-, and 64-
bit integer formats. The corresponding instruction mnemonic suffixes are ‘s’ (single),
‘l’ (long), and ‘q’ (quad). As with the 80-bit real format, the 64-bit ‘q’ format is only
present in the ‘fildq’ (load quad integer to stack top) and ‘fistpq’ (store quad integer
and pop stack) instructions.
Register to register operations should not use instruction mnemonic suffixes. ‘fstl %st,
%st(1)’ will give a warning, and be assembled as if you wrote ‘fst %st, %st(1)’, since all
register to register operations use 80-bit floating point operands. (Contrast this with ‘fstl
%st, mem’, which converts ‘%st’ from 80-bit to 64-bit floating point format, then stores the
result in the 4 byte location ‘mem’)
Apart from the warning, there are only two other effects on as operation; Firstly, if you
specify a CPU other than ‘i486’, then shift by one instructions such as ‘sarl $1, %eax’
will automatically use a two byte opcode sequence. The larger three byte opcode sequence
is used on the 486 (and when no architecture is specified) because it executes faster on
the 486. Note that you can explicitly request the two byte opcode by writing ‘sarl %eax’.
Secondly, if you specify ‘i8086’, ‘i186’, or ‘i286’, and ‘.code16’ or ‘.code16gcc’ then byte
offset conditional jumps will be promoted when necessary to a two instruction sequence
consisting of a conditional jump of the opposite sense around an unconditional jump to the
target.
Following the CPU architecture (but not a sub-architecture, which are those starting with
a dot), you may specify ‘jumps’ or ‘nojumps’ to control automatic promotion of conditional
jumps. ‘jumps’ is the default, and enables jump promotion; All external jumps will be of
the long variety, and file-local jumps will be promoted as necessary. (see Section 9.15.8
[i386-Jumps], page 170) ‘nojumps’ leaves external conditional jumps as byte offset jumps,
and warns about file-local conditional jumps that as promotes. Unconditional jumps are
treated as for ‘jumps’.
For example
.arch i8086,nojumps
174 Using as
9.15.17 Notes
There is some trickery concerning the ‘mul’ and ‘imul’ instructions that deserves mention.
The 16-, 32-, 64- and 128-bit expanding multiplies (base opcode ‘0xf6’; extension 4 for ‘mul’
and 5 for ‘imul’) can be output only in the one operand form. Thus, ‘imul %ebx, %eax’
does not select the expanding multiply; the expanding multiply would clobber the ‘%edx’
register, and this would confuse gcc output. Use ‘imul %ebx’ to get the 64-bit product in
‘%edx:%eax’.
We have added a two operand form of ‘imul’ when the first operand is an immediate
mode expression and the second operand is a register. This is just a shorthand, so that,
multiplying ‘%eax’ by 69, for example, can be done with ‘imul $69, %eax’ rather than ‘imul
$69, %eax, %eax’.
Chapter 9: Machine Dependent Features 175
.enddual Exit dual instruction mode. While this directive is supported, the preferred
way to use dual instruction mode is to explicitly code the dual bit with the d.
prefix.
.atmp Change the temporary register used when expanding pseudo operations. The
default register is r31.
The .dual, .enddual, and .atmp directives are available only in the Intel syntax mode.
Both syntaxes allow for the standard .align directive. However, the Intel syntax addi-
tionally allows keywords for the alignment parameter: ".align type", where ‘type’ is one
of .short, .long, .quad, .single, .double representing alignments of 2, 4, 16, 4, and 8,
respectively.
-b Add code to collect information about conditional branches taken, for later
optimization using branch prediction bits. (The conditional branch instructions
have branch prediction bits in the CA, CB, and CC architectures.) If BR
represents a conditional branch instruction, the following represents the code
generated by the assembler when ‘-b’ is specified:
call increment routine
.word 0 # pre-counter
Label: BR
call increment routine
.word 0 # post-counter
The counter following a branch records the number of times that branch was
not taken; the difference between the two counters is the number of times the
branch was taken.
A table of every such Label is also generated, so that the external postprocessor
gbr960 (supplied by Intel) can locate all the counters. This table is always
labeled ‘__BRANCH_TABLE__’; this is a local symbol to permit collecting statistics
for many separate object files. The table is word aligned, and begins with a
two-word header. The first word, initialized to 0, is used in maintaining linked
lists of branch tables. The second word is a count of the number of entries
in the table, which follow immediately: each is a word, pointing to one of the
labels illustrated above.
-no-relax
Normally, Compare-and-Branch instructions with targets that require displace-
ments greater than 13 bits (or that have external targets) are replaced with
the corresponding compare (or ‘chkbit’) and branch instructions. You can use
the ‘-no-relax’ option to specify that as should generate errors instead, if the
target displacement is larger than 13 bits.
This option does not affect the Compare-and-Jump instructions; the code emit-
ted for them is always adjusted when necessary (depending on displacement
size), regardless of whether you use ‘-no-relax’.
9.17.4.1 callj
You can write callj to have the assembler or the linker determine the most appropriate
form of subroutine call: ‘call’, ‘bal’, or ‘calls’. If the assembly source contains enough
information—a ‘.leafproc’ or ‘.sysproc’ directive defining the operand—then as trans-
lates the callj; if not, it simply emits the callj, leaving it for the linker to resolve.
9.17.4.2 Compare-and-Branch
The 960 architectures provide combined Compare-and-Branch instructions that permit you
to store the branch target in the lower 13 bits of the instruction word itself. However, if you
specify a branch target far enough away that its address won’t fit in 13 bits, the assembler
can either issue an error, or convert your Compare-and-Branch instruction into separate
instructions to do the compare and the branch.
Whether as gives an error or expands the instruction depends on two choices you can
make: whether you use the ‘-no-relax’ option, and whether you use a “Compare and
Branch” instruction or a “Compare and Jump” instruction. The “Jump” instructions are
always expanded if necessary; the “Branch” instructions are expanded when necessary un-
less you specify -no-relax—in which case as gives an error instead.
These are the Compare-and-Branch instructions, their “Jump” variants, and the instruc-
tion pairs they may expand into:
Compare and
Branch Jump Expanded to
bbc chkbit; bno
bbs chkbit; bo
cmpibe cmpije cmpi; be
cmpibg cmpijg cmpi; bg
cmpibge cmpijge cmpi; bge
cmpibl cmpijl cmpi; bl
cmpible cmpijle cmpi; ble
cmpibno cmpijno cmpi; bno
cmpibne cmpijne cmpi; bne
cmpibo cmpijo cmpi; bo
cmpobe cmpoje cmpo; be
cmpobg cmpojg cmpo; bg
cmpobge cmpojge cmpo; bge
cmpobl cmpojl cmpo; bl
cmpoble cmpojle cmpo; ble
cmpobne cmpojne cmpo; bne
Chapter 9: Machine Dependent Features 181
9.18.2 Syntax
The assembler syntax closely follows the IA-64 Assembly Language Reference Guide.
9.18.2.4 Relocations
In addition to the standard IA-64 relocations, the following relocations are implemented by
as:
184 Using as
@slotcount(V )
Convert the address offset V into a slot count. This pseudo function is available
only on VMS. The expression V must be known at assembly time: it can’t
reference undefined symbols or symbols in different sections.
9.18.3 Opcodes
For detailed information on the IA-64 machine instruction set, see the IA-64 Assembly
Language Reference Guide available at
http://developer.intel.com/design/itanium/arch_spec.htm
Chapter 9: Machine Dependent Features 185
9.20.2 Syntax
9.20.2.1 Register Names
LM32 has 32 x 32-bit general purpose registers ‘r0’, ‘r1’, ... ‘r31’.
The following aliases are defined: ‘gp’ - ‘r26’, ‘fp’ - ‘r27’, ‘sp’ - ‘r28’, ‘ra’ - ‘r29’, ‘ea’
- ‘r30’, ‘ba’ - ‘r31’.
LM32 has the following Control and Status Registers (CSRs).
IE Interrupt enable.
IM Interrupt mask.
IP Interrupt pending.
ICC Instruction cache control.
DCC Data cache control.
CC Cycle counter.
CFG Configuration.
EBA Exception base address.
DC Debug control.
Chapter 9: Machine Dependent Features 187
9.20.3 Opcodes
For detailed information on the LM32 machine instruction set, see http://www.latticesemi.com/products/in
as implements all the standard LM32 opcodes.
Chapter 9: Machine Dependent Features 189
%dsp8
%dsp16
These modifiers override the assembler’s assumptions about how big a sym-
bol’s address is. Normally, when it sees an operand like ‘sym[a0]’ it assumes
‘sym’ may require the widest displacement field (16 bits for ‘-m16c’, 24 bits for
‘-m32c’). These modifiers tell it to assume the address will fit in an 8 or 16 bit
(respectively) unsigned displacement. Note that, of course, if it doesn’t actually
fit you will get linker errors. Example:
mov.w %dsp8(sym)[a0],r1
mov.b #0,%dsp8(sym)[a0]
%hi8
This modifier allows you to load bits 16 through 23 of a 24 bit address into an
8 bit register. This is useful with, for example, the M16C ‘smovf’ instruction,
which expects a 20 bit address in ‘r1h’ and ‘a0’. Example:
mov.b #%hi8(sym),r1h
mov.w #%lo16(sym),a0
smovf.b
%lo16
Likewise, this modifier allows you to load bits 0 through 15 of a 24 bit address
into a 16 bit register.
%hi16
This modifier allows you to load bits 16 through 31 of a 32 bit address into
a 16 bit register. While the M32C family only has 24 bits of address space,
190 Using as
it does support addresses in pairs of 16 bit registers (like ‘a1a0’ for the ‘lde’
instruction). This modifier is for loading the upper half in such cases. Example:
mov.w #%hi16(sym),a1
mov.w #%lo16(sym),a0
...
lde.w [a1a0],r1
-no-warn-explicit-parallel-conflicts
Instructs as not to produce warning messages when questionable parallel in-
structions are encountered.
-Wnp This is a shorter synonym for the -no-warn-explicit-parallel-conflicts option.
-ignore-parallel-conflicts
This option tells the assembler’s to stop checking parallel instructions for con-
straint violations. This ability is provided for hardware vendors testing chip
designs and should not be used under normal circumstances.
-no-ignore-parallel-conflicts
This option restores the assembler’s default behaviour of checking parallel in-
structions to detect constraint violations.
-Ip This is a shorter synonym for the -ignore-parallel-conflicts option.
-nIp This is a shorter synonym for the -no-ignore-parallel-conflicts option.
-warn-unmatched-high
This option tells the assembler to produce a warning message if a .high pseudo
op is encountered without a matching .low pseudo op. The presence of such
an unmatched pseudo op usually indicates a programming error.
-no-warn-unmatched-high
Disables a previously enabled -warn-unmatched-high option.
-Wuh This is a shorter synonym for the -warn-unmatched-high option.
-Wnuh This is a shorter synonym for the -no-warn-unmatched-high option.
as an input register in the right hand instruction. For example in this code
fragment ‘mv r1, r2 || neg r3, r1’ register r1 is the destination of the move
instruction and the input to the neg instruction.
output of 2nd instruction is the same as an input to 1st instruction - is this
intentional ?
This message is only produced if warnings for explicit parallel conflicts have
been enabled. It indicates that the assembler has encountered a parallel in-
struction in which the destination register of the right hand instruction is used
as an input register in the left hand instruction. For example in this code
fragment ‘mv r1, r2 || neg r2, r3’ register r2 is the destination of the neg
instruction and the input to the move instruction.
instruction ‘...’ is for the M32RX only
This message is produced when the assembler encounters an instruction which
is only supported by the M32Rx processor, and the ‘-m32rx’ command line flag
has not been specified to allow assembly of such instructions.
unknown instruction ‘...’
This message is produced when the assembler encounters an instruction which
it does not recognize.
only the NOP instruction can be issued in parallel on the m32r
This message is produced when the assembler encounters a parallel instruction
which does not involve a NOP instruction and the ‘-m32rx’ command line
flag has not been specified. Only the M32Rx processor is able to execute two
instructions in parallel.
instruction ‘...’ cannot be executed in parallel.
This message is produced when the assembler encounters a parallel instruction
which is made up of one or two instructions which cannot be executed in parallel.
Instructions share the same execution pipeline
This message is produced when the assembler encounters a parallel instruction
whose components both use the same execution pipeline.
Instructions write to the same destination register.
This message is produced when the assembler encounters a parallel instruction
where both components attempt to modify the same register. For example these
code fragments will produce this message: ‘mv r1, r2 || neg r1, r3’ ‘jl r0 ||
mv r14, r1’ ‘st r2, @-r1 || mv r1, r3’ ‘mv r1, r2 || ld r0, @r1+’ ‘cmp r1,
r2 || addx r3, r4’ (Both write to the condition bit)
Chapter 9: Machine Dependent Features 195
normal character. In this mode, you must either use C style comments, or start
comments with a ‘#’ character at the beginning of a line.
‘--base-size-default-16 --base-size-default-32’
If you use an addressing mode with a base register without specifying
the size, as will normally use the full 32 bit value. For example, the
addressing mode ‘%a0@(%d0)’ is equivalent to ‘%a0@(%d0:l)’. You may use
the ‘--base-size-default-16’ option to tell as to default to using the 16 bit
value. In this case, ‘%a0@(%d0)’ is equivalent to ‘%a0@(%d0:w)’. You may use
the ‘--base-size-default-32’ option to restore the default behaviour.
‘--disp-size-default-16 --disp-size-default-32’
If you use an addressing mode with a displacement, and the value of the dis-
placement is not known, as will normally assume that the value is 32 bits. For
example, if the symbol ‘disp’ has not been defined, as will assemble the ad-
dressing mode ‘%a0@(disp,%d0)’ as though ‘disp’ is a 32 bit value. You may
use the ‘--disp-size-default-16’ option to tell as to instead assume that
the displacement is 16 bits. In this case, as will assemble ‘%a0@(disp,%d0)’ as
though ‘disp’ is a 16 bit value. You may use the ‘--disp-size-default-32’
option to restore the default behaviour.
‘--pcrel’ Always keep branches PC-relative. In the M680x0 architecture all branches are
defined as PC-relative. However, on some processors they are limited to word
displacements maximum. When as needs a long branch that is not available,
it normally emits an absolute jump instead. This option disables this substitu-
tion. When this option is given and no long branches are available, only word
branches will be emitted. An error message will be generated if a word branch
cannot reach its target. This option has no effect on 68020 and other processors
that have long branches. see Section 9.23.6.1 [Branch Improvement], page 201.
‘-m68000’ as can assemble code for several different members of the Motorola 680x0 family.
The default depends upon how as was configured when it was built; normally,
the default is to assemble code for the 68020 microprocessor. The following
options may be used to change the default. These options control which in-
structions and addressing modes are permitted. The members of the 680x0
family are very similar. For detailed information about the differences, see the
Motorola manuals.
‘-m68000’
‘-m68ec000’
‘-m68hc000’
‘-m68hc001’
‘-m68008’
‘-m68302’
‘-m68306’
‘-m68307’
‘-m68322’
‘-m68356’ Assemble for the 68000. ‘-m68008’, ‘-m68302’, and so on are syn-
onyms for ‘-m68000’, since the chips are the same from the point
of view of the assembler.
Chapter 9: Machine Dependent Features 197
‘-m68020’
‘-m68ec020’
Assemble for the 68020. This is normally the default.
‘-m68030’
‘-m68ec030’
Assemble for the 68030.
‘-m68040’
‘-m68ec040’
Assemble for the 68040.
‘-m68060’
‘-m68ec060’
Assemble for the 68060.
‘-mcpu32’
‘-m68330’
‘-m68331’
‘-m68332’
‘-m68333’
‘-m68334’
‘-m68336’
‘-m68340’
‘-m68341’
‘-m68349’
‘-m68360’ Assemble for the CPU32 family of chips.
‘-m5200’
‘-m5202’
‘-m5204’
‘-m5206’
‘-m5206e’
‘-m521x’
‘-m5249’
‘-m528x’
‘-m5307’
‘-m5407’
‘-m547x’
‘-m548x’
‘-mcfv4’
‘-mcfv4e’ Assemble for the ColdFire family of chips.
‘-m68881’
‘-m68882’ Assemble 68881 floating point instructions. This is the default for
the 68020, 68030, and the CPU32. The 68040 and 68060 always
support floating point instructions.
198 Using as
‘-mno-68881’
Do not assemble 68881 floating point instructions. This is the de-
fault for 68000 and the 68010. The 68040 and 68060 always support
floating point instructions, even if this option is used.
‘-m68851’ Assemble 68851 MMU instructions. This is the default for the
68020, 68030, and 68060. The 68040 accepts a somewhat different
set of MMU instructions; ‘-m68851’ and ‘-m68040’ should not be
used together.
‘-mno-68851’
Do not assemble 68851 MMU instructions. This is the default for
the 68000, 68010, and the CPU32. The 68040 accepts a somewhat
different set of MMU instructions.
9.23.2 Syntax
This syntax for the Motorola 680x0 was developed at mit.
The 680x0 version of as uses instructions names and syntax compatible with the Sun
assembler. Intervening periods are ignored; for example, ‘movl’ is equivalent to ‘mov.l’.
In the following table apc stands for any of the address registers (‘%a0’ through ‘%a7’),
the program counter (‘%pc’), the zero-address relative to the program counter (‘%zpc’), a
suppressed address register (‘%za0’ through ‘%za7’), or it may be omitted entirely. The use
of size means one of ‘w’ or ‘l’, and it may be omitted, along with the leading colon, unless
a scale is also specified. The use of scale means one of ‘1’, ‘2’, ‘4’, or ‘8’, and it may always
be omitted along with the leading colon.
The following addressing modes are understood:
Immediate
‘#number ’
Data Register
‘%d0’ through ‘%d7’
Address Register
‘%a0’ through ‘%a7’
‘%a7’ is also known as ‘%sp’, i.e., the Stack Pointer. %a6 is also known as ‘%fp’,
the Frame Pointer.
Address Register Indirect
‘%a0@’ through ‘%a7@’
Address Register Postincrement
‘%a0@+’ through ‘%a7@+’
Address Register Predecrement
‘%a0@-’ through ‘%a7@-’
Indirect Plus Offset
‘apc @(number )’
Index ‘apc @(number ,register :size :scale )’
The number may be omitted.
Chapter 9: Machine Dependent Features 199
.extend
.ldouble Extended precision (long double) floating point constants.
.even This directive is a special case of the .align directive; it aligns the output to
an even byte boundary.
.arch name
Select the target architecture and extension features. Valid values for name
are the same as for the ‘-march’ command line option. This directive cannot
be specified after any instructions have been assembled. If it is given multiple
times, or in conjunction with the ‘-march’ option, all uses must be for the same
architecture and extension set.
.cpu name
Select the target cpu. Valid values for name are the same as for the ‘-mcpu’
command line option. This directive cannot be specified after any instructions
have been assembled. If it is given multiple times, or in conjunction with the
‘-mopt’ option, all uses must be for the same cpu.
Chapter 9: Machine Dependent Features 201
9.23.6 Opcodes
9.23.6.1 Branch Improvement
Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest
branch instruction that reach the target. Generally these mnemonics are made by substi-
tuting ‘j’ for ‘b’ at the start of a Motorola mnemonic.
The following table summarizes the pseudo-operations. A * flags cases that are more
fully described after the table:
Displacement
+------------------------------------------------------------
| 68020 68000/10, not PC-relative OK
Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP **
+------------------------------------------------------------
jbsr |bsrs bsrw bsrl jsr
jra |bras braw bral jmp
* jXX |bXXs bXXw bXXl bNXs;jmp
* dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp
fjXX | N/A fbXXw fbXXl N/A
XX: condition
NX: negative of condition XX
bNX s oof
jmp foo
oof:
--short-branches
The ‘--short-branches’ option turns off the translation of relative branches
into absolute branches when the branch offset is out of range. By default
as transforms the relative branch (‘bsr’, ‘bgt’, ‘bge’, ‘beq’, ‘bne’, ‘ble’, ‘blt’,
‘bhi’, ‘bcc’, ‘bls’, ‘bcs’, ‘bmi’, ‘bvs’, ‘bvs’, ‘bra’) into an absolute branch when
the offset is out of the -128 .. 127 range. In that case, the ‘bsr’ instruction is
translated into a ‘jsr’, the ‘bra’ instruction is translated into a ‘jmp’ and the
conditional branches instructions are inverted and followed by a ‘jmp’. This
option disables these translations and as will generate an error if a relative
branch is out of range. This option does not affect the optimization associated
to the ‘jbra’, ‘jbsr’ and ‘jbXX’ pseudo opcodes.
--force-long-branches
The ‘--force-long-branches’ option forces the translation of relative branches
into absolute branches. This option does not affect the optimization associated
to the ‘jbra’, ‘jbsr’ and ‘jbXX’ pseudo opcodes.
--print-insn-syntax
You can use the ‘--print-insn-syntax’ option to obtain the syntax description
of the instruction when an error is detected.
--print-opcodes
The ‘--print-opcodes’ option prints the list of all the instructions with their
syntax. The first item of each line represents the instruction name and the
rest of the line indicates the possible operands for that instruction. The list is
printed in alphabetical order. Once the list is printed as exits.
--generate-example
The ‘--generate-example’ option is similar to ‘--print-opcodes’ but it gen-
erates an example for each instruction instead.
9.24.2 Syntax
In the M68HC11 syntax, the instruction name comes first and it may be followed by one
or several operands (up to three). Operands are separated by comma (‘,’). In the normal
mode, as will complain if too many operands are specified for a given instruction. In the
MRI mode (turned on with ‘-M’ option), it will treat them as comments. Example:
inx
lda #23
bset 2,x #4
brclr *bot #8 foo
The presence of a ‘;’ character or a ‘!’ character anywhere on a line indicates the start
of a comment that extends to the end of that line.
A ‘*’ or a ‘#’ character at the start of a line also introduces a line comment, but these
characters do not work elsewhere on the line. If the first character of the line is a ‘#’
then as well as starting a comment, the line could also be logical line number directive
(see Section 3.3 [Comments], page 29) or a preprocessor control command (see Section 3.1
[Preprocessing], page 29).
The M68HC11 assembler does not currently support a line separator character.
The following addressing modes are understood for 68HC11 and 68HC12:
Chapter 9: Machine Dependent Features 205
Immediate
‘#number ’
Address Register
‘number ,X’, ‘number ,Y’
The number may be omitted in which case 0 is assumed.
Direct Addressing mode
‘*symbol ’, or ‘*digits ’
Absolute ‘symbol ’, or ‘digits ’
The M68HC12 has other more complex addressing modes. All of them are supported
and they are represented below:
For example:
ldab 1024,sp
ldd [10,x]
orab 3,+x
stab -2,y-
ldx a,pc
sty [d,sp]
206 Using as
.interrupt symbol
This directive marks the symbol as an interrupt entry point. This information
is then used by the debugger to correctly unwind the frame across interrupts.
.xrefb symbol
This directive is defined for compatibility with the ‘Specification for
Motorola 8 and 16-Bit Assembly Language Input Standard’ and is ignored.
9.24.6 Opcodes
9.24.6.1 Branch Improvement
Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest
branch instruction that reach the target. Generally these mnemonics are made by prepend-
ing ‘j’ to the start of Motorola mnemonic. These pseudo opcodes are not affected by the
‘--short-branches’ or ‘--force-long-branches’ options.
The following table summarizes the pseudo-operations.
Displacement Width
+-------------------------------------------------------------+
| Options |
| --short-branches --force-long-branches |
+--------------------------+----------------------------------+
Op |BYTE WORD | BYTE WORD |
+--------------------------+----------------------------------+
bsr | bsr <pc-rel> <error> | jsr <abs> |
bra | bra <pc-rel> <error> | jmp <abs> |
jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
| jmp <abs> | |
+--------------------------+----------------------------------+
XX: condition
NX: negative of condition XX
jbsr
jbra These are the simplest jump pseudo-operations; they always map to one partic-
ular machine instruction, depending on the displacement to the branch target.
jbXX Here, ‘jbXX ’ stands for an entire family of pseudo-operations, where XX is a
conditional branch or condition-code test. The full list of pseudo-ops in this
family is:
208 Using as
9.25.2 Syntax
9.25.2.1 Special Characters
‘!’ is the line comment character.
You can use ‘;’ instead of a newline to separate statements.
Since ‘$’ has no special meaning, you may use it in symbol names.
9.26.1 Directives
A number of assembler directives are available for MicroBlaze.
.data8 expression ,...
This directive is an alias for .byte. Each expression is assembled into an eight-
bit value.
.data16 expression ,...
This directive is an alias for .hword. Each expression is assembled into an
16-bit value.
.data32 expression ,...
This directive is an alias for .word. Each expression is assembled into an 32-bit
value.
.ent name [,label ]
This directive is an alias for .func denoting the start of function name at
(optional) label.
.end name [,label ]
This directive is an alias for .endfunc denoting the end of function name.
.gpword label ,...
This directive is an alias for .rva. The resolved address of label is stored in
the data section.
.weakext label
Declare that label is a weak external symbol.
.rodata Switch to .rodata section. Equivalent to .section .rodata
.sdata2 Switch to .sdata2 section. Equivalent to .section .sdata2
.sdata Switch to .sdata section. Equivalent to .section .sdata
.bss Switch to .bss section. Equivalent to .section .bss
.sbss Switch to .sbss section. Equivalent to .section .sbss
-mgp32
-mfp32 Some macros have different expansions for 32-bit and 64-bit registers. The
register sizes are normally inferred from the ISA and ABI, but these flags force
a certain group of registers to be treated as 32 bits wide at all times. ‘-mgp32’
controls the size of general-purpose registers and ‘-mfp32’ controls the size of
floating-point registers.
The .set gp=32 and .set fp=32 directives allow the size of registers to
be changed for parts of an object. The default value is restored by .set
gp=default and .set fp=default.
On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-
bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit
registers on a context switch, so it is essential never to use the 64-bit registers.
-mgp64
-mfp64 Assume that 64-bit registers are available. This is provided in the interests of
symmetry with ‘-mgp32’ and ‘-mfp32’.
The .set gp=64 and .set fp=64 directives allow the size of registers to
be changed for parts of an object. The default value is restored by .set
gp=default and .set fp=default.
-mfpxx Make no assumptions about whether 32-bit or 64-bit floating-point registers are
available. This is provided to support having modules compatible with either
‘-mfp32’ or ‘-mfp64’. This option can only be used with MIPS II and above.
The .set fp=xx directive allows a part of an object to be marked as not making
assumptions about 32-bit or 64-bit FP registers. The default value is restored
by .set fp=default.
-modd-spreg
-mno-odd-spreg
Enable use of floating-point operations on odd-numbered single-precision regis-
ters when supported by the ISA. ‘-mfpxx’ implies ‘-mno-odd-spreg’, otherwise
the default is ‘-modd-spreg’
-mips16
-no-mips16
Generate code for the MIPS 16 processor. This is equivalent to putting .module
mips16 at the start of the assembly file. ‘-no-mips16’ turns off this option.
-mmips16e2
-mno-mips16e2
Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to
putting .module mips16e2 at the start of the assembly file. ‘-mno-mips16e2’
turns off this option.
Chapter 9: Machine Dependent Features 213
-mmicromips
-mno-micromips
Generate code for the microMIPS processor. This is equivalent to putting
.module micromips at the start of the assembly file. ‘-mno-micromips’ turns
off this option. This is equivalent to putting .module nomicromips at the start
of the assembly file.
-msmartmips
-mno-smartmips
Enables the SmartMIPS extensions to the MIPS32 instruction set, which pro-
vides a number of new instructions which target smartcard and cryptographic
applications. This is equivalent to putting .module smartmips at the start of
the assembly file. ‘-mno-smartmips’ turns off this option.
-mips3d
-no-mips3d
Generate code for the MIPS-3D Application Specific Extension. This tells the
assembler to accept MIPS-3D instructions. ‘-no-mips3d’ turns off this option.
-mdmx
-no-mdmx Generate code for the MDMX Application Specific Extension. This tells the
assembler to accept MDMX instructions. ‘-no-mdmx’ turns off this option.
-mdsp
-mno-dsp Generate code for the DSP Release 1 Application Specific Extension. This tells
the assembler to accept DSP Release 1 instructions. ‘-mno-dsp’ turns off this
option.
-mdspr2
-mno-dspr2
Generate code for the DSP Release 2 Application Specific Extension. This
option implies ‘-mdsp’. This tells the assembler to accept DSP Release 2 in-
structions. ‘-mno-dspr2’ turns off this option.
-mdspr3
-mno-dspr3
Generate code for the DSP Release 3 Application Specific Extension. This
option implies ‘-mdsp’ and ‘-mdspr2’. This tells the assembler to accept DSP
Release 3 instructions. ‘-mno-dspr3’ turns off this option.
-mmt
-mno-mt Generate code for the MT Application Specific Extension. This tells the as-
sembler to accept MT instructions. ‘-mno-mt’ turns off this option.
-mmcu
-mno-mcu Generate code for the MCU Application Specific Extension. This tells the
assembler to accept MCU instructions. ‘-mno-mcu’ turns off this option.
-mmsa
-mno-msa Generate code for the MIPS SIMD Architecture Extension. This tells the as-
sembler to accept MSA instructions. ‘-mno-msa’ turns off this option.
214 Using as
-mxpa
-mno-xpa Generate code for the MIPS eXtended Physical Address (XPA) Extension. This
tells the assembler to accept XPA instructions. ‘-mno-xpa’ turns off this option.
-mvirt
-mno-virt
Generate code for the Virtualization Application Specific Extension. This tells
the assembler to accept Virtualization instructions. ‘-mno-virt’ turns off this
option.
-minsn32
-mno-insn32
Only use 32-bit instruction encodings when generating code for the microMIPS
processor. This option inhibits the use of any 16-bit instructions. This is equiv-
alent to putting .set insn32 at the start of the assembly file. ‘-mno-insn32’
turns off this option. This is equivalent to putting .set noinsn32 at the start of
the assembly file. By default ‘-mno-insn32’ is selected, allowing all instructions
to be used.
-mfix7000
-mno-fix7000
Cause nops to be inserted if the read of the destination register of an mfhi or
mflo instruction occurs in the following two instructions.
-mfix-rm7000
-mno-fix-rm7000
Cause nops to be inserted if a dmult or dmultu instruction is followed by a load
instruction.
-mfix-loongson2f-jump
-mno-fix-loongson2f-jump
Eliminate instruction fetch from outside 256M region to work around the Loong-
son2F ‘jump’ instructions. Without it, under extreme cases, the kernel may
crash. The issue has been solved in latest processor batches, but this fix has no
side effect to them.
-mfix-loongson2f-nop
-mno-fix-loongson2f-nop
Replace nops by or at,at,zero to work around the Loongson2F ‘nop’ errata.
Without it, under extreme cases, the CPU might deadlock. The issue has been
solved in later Loongson2F batches, but this fix has no side effect to them.
-mfix-vr4120
-mno-fix-vr4120
Insert nops to work around certain VR4120 errata. This option is intended to
be used on GCC-generated code: it is not designed to catch all problems in
hand-written assembler code.
-mfix-vr4130
-mno-fix-vr4130
Insert nops to work around the VR4130 ‘mflo’/‘mfhi’ errata.
Chapter 9: Machine Dependent Features 215
-mfix-24k
-mno-fix-24k
Insert nops to work around the 24K ‘eret’/‘deret’ errata.
-mfix-cn63xxp1
-mno-fix-cn63xxp1
Replace pref hints 0 - 4 and 6 - 24 with hint 28 to work around certain
CN63XXP1 errata.
-m4010
-no-m4010
Generate code for the LSI R4010 chip. This tells the assembler to accept the
R4010-specific instructions (‘addciu’, ‘ffc’, etc.), and to not schedule ‘nop’
instructions around accesses to the ‘HI’ and ‘LO’ registers. ‘-no-m4010’ turns
off this option.
-m4650
-no-m4650
Generate code for the MIPS R4650 chip. This tells the assembler to accept
the ‘mad’ and ‘madu’ instruction, and to not schedule ‘nop’ instructions around
accesses to the ‘HI’ and ‘LO’ registers. ‘-no-m4650’ turns off this option.
-m3900
-no-m3900
-m4100
-no-m4100
For each option ‘-mnnnn ’, generate code for the MIPS Rnnnn chip. This tells
the assembler to accept instructions specific to that chip, and to schedule for
that chip’s hazards.
-march=cpu
Generate code for a particular MIPS CPU. It is exactly equivalent to ‘-mcpu ’,
except that there are more value of cpu understood. Valid cpu value are:
2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181,
4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261,
rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000,
14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, m4k,
m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 24kf2 1, 24kf, 24kf1 1,
24kec, 24kef2 1, 24kef, 24kef1 1, 34kc, 34kf2 1, 34kf, 34kf1 1, 34kn,
74kc, 74kf2 1, 74kf, 74kf1 1, 74kf3 2, 1004kc, 1004kf2 1, 1004kf,
1004kf1 1, interaptiv, interaptiv-mr2, m5100, m5101, p5600, 5kc,
5kf, 20kc, 25kf, sb1, sb1a, i6400, p6600, loongson2e, loongson2f,
loongson3a, octeon, octeon+, octeon2, octeon3, xlr, xlp
For compatibility reasons, ‘n x’ and ‘b fx’ are accepted as synonyms for ‘n f1_1’.
These values are deprecated.
-mtune=cpu
Schedule and tune for a particular MIPS CPU. Valid cpu values are identical
to ‘-march=cpu ’.
216 Using as
-mabi=abi
Record which ABI the source code uses. The recognized arguments are: ‘32’,
‘n32’, ‘o64’, ‘64’ and ‘eabi’.
-msym32
-mno-sym32
Equivalent to adding .set sym32 or .set nosym32 to the beginning of the as-
sembler input. See Section 9.27.3 [MIPS Symbol Sizes], page 219.
-nocpp This option is ignored. It is accepted for command-line compatibility with
other assemblers, which use it to turn off C style preprocessing. With gnu as,
there is no need for ‘-nocpp’, because the gnu assembler itself never runs the
C preprocessor.
-msoft-float
-mhard-float
Disable or enable floating-point instructions. Note that by default floating-
point instructions are always allowed even with CPU targets that don’t have
support for these instructions.
-msingle-float
-mdouble-float
Disable or enable double-precision floating-point operations. Note that by de-
fault double-precision floating-point operations are always allowed even with
CPU targets that don’t have support for these operations.
--construct-floats
--no-construct-floats
The --no-construct-floats option disables the construction of double width
floating point constants by loading the two halves of the value into the two
single width floating point registers that make up the double width register.
This feature is useful if the processor support the FR bit in its status register,
and this bit is known (by the programmer) to be set. This bit prevents the
aliasing of the double width register by the single width registers.
By default --construct-floats is selected, allowing construction of these
floating point constants.
--relax-branch
--no-relax-branch
The ‘--relax-branch’ option enables the relaxation of out-of-range branches.
Any branches whose target cannot be reached directly are converted to a small
instruction sequence including an inverse-condition branch to the physically
next instruction, and a jump to the original target is inserted between the two
instructions. In PIC code the jump will involve further instructions for address
calculation.
The BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T, BPOSGE32 and BPOSGE64 in-
structions are excluded from relaxation, because they have no complementing
counterparts. They could be relaxed with the use of a longer sequence involv-
ing another branch, however this has not been implemented and if their target
turns out of reach, they produce an error even if branch relaxation is enabled.
Chapter 9: Machine Dependent Features 217
-mpdr
-mno-pdr Control generation of .pdr sections. Off by default on IRIX, on elsewhere.
-mshared
-mno-shared
When generating code using the Unix calling conventions (selected by ‘-KPIC’ or
‘-mcall_shared’), gas will normally generate code which can go into a shared
library. The ‘-mno-shared’ option tells gas to generate code which uses the
calling convention, but can not go into a shared library. The resulting code is
slightly more efficient. This option only affects the handling of the ‘.cpload’
and ‘.cpsetup’ pseudo-ops.
When no ‘-G’ option is given, the default limit is 8 bytes. The option ‘-G 0’ prevents
any data from being automatically classified as small.
It is also possible to mark specific objects as small by putting them in the special sections
.sdata and .sbss, which are “small” counterparts of .data and .bss respectively. The
toolchain will treat such data as small regardless of the ‘-G’ setting.
On startup, systems that support a small data area are expected to initialize register
$28, also known as $gp, in such a way that small data can be accessed using a 16-bit offset
from that register. For example, when ‘addr’ is small data, the ‘dla $4,addr’ instruction
above is equivalent to:
daddiu $4,$28,%gp_rel(addr)
Small data is not supported for SVR4-style PIC.
16-bit instructions from that point on in the assembly. The .set noinsn32 directive allows
16-bit instructions to be accepted.
Traditional MIPS assemblers do not support this directive.
directive has been seen then a warning will be raised if it does not match an inferred
setting.
The floating-point ABI is inferred as follows. If ‘-msoft-float’ has been used the
module will be marked as soft-float. If ‘-msingle-float’ has been used then the module
will be marked as single-precision. The remaining ABIs are then selected based on the
FP register width. Double-precision is selected if the width of GP and FP registers match
and the special double-precision variants for 32-bit ABIs are then selected depending on
‘-mfpxx’, ‘-mfp64’ and ‘-mno-odd-spreg’.
The directive .set xpa makes the assembler accept instructions from the XPA Extension
from that point on in the assembly. The .set noxpa directive prevents XPA instructions
from being accepted.
The directive .set mips16e2 makes the assembler accept instructions from the
MIPS16e2 Application Specific Extension from that point on in the assembly, whenever
in MIPS16 mode. The .set nomips16e2 prevents MIPS16e2 instructions from being
accepted, in MIPS16 mode. Neither directive affects the state of MIPS16 mode being
active itself which has separate controls.
Traditional MIPS assemblers do not support these directives.
is in effect, they are instead passed through to the linker, which will allocate as many global
registers as is needed.
9.28.3 Syntax
The assembly syntax is supposed to be upward compatible with that described
in Sections 1.3 and 1.4 of ‘The Art of Computer Programming, Volume 1’. Draft
versions of those chapters as well as other MMIX information is located at
http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html. Most code examples
from the mmixal package located there should work unmodified when assembled and
linked as single files, with a few noteworthy exceptions (see Section 9.28.4 [MMIX-mmixal],
page 231).
Before an instruction is emitted, the current location is aligned to the next four-byte
boundary. If a label is defined at the beginning of the line, its value will be the aligned
value.
In addition to the traditional hex-prefix ‘0x’, a hexadecimal number can also be specified
by the prefix character ‘#’.
After all operands to an MMIX instruction or directive have been specified, the rest of
the line is ignored, treated as a comment.
[Comments], page 29) or a preprocessor control command (see Section 3.1 [Preprocessing],
page 29).
Two other characters, ‘%’ and ‘!’, each start a comment anywhere on the line. Thus you
can’t use the ‘modulus’ and ‘not’ operators in expressions normally associated with these
two characters.
A ‘;’ is a line separator, treated as a new-line, so separate instructions can be specified
on a single line.
9.28.3.2 Symbols
The character ‘:’ is permitted in identifiers. There are two exceptions to it being treated as
any other symbol character: if a symbol begins with ‘:’, it means that the symbol is in the
global namespace and that the current prefix should not be prepended to that symbol (see
[MMIX-prefix], page 231). The ‘:’ is then not considered part of the symbol. For a symbol
in the label position (first on a line), a ‘:’ at the end of a symbol is silently stripped off. A
label is permitted, but not required, to be followed by a ‘:’, as with many other assembly
formats.
The character ‘@’ in an expression, is a synonym for ‘.’, the current location.
In addition to the common forward and backward local symbol formats (see Section 5.3
[Symbol Names], page 41), they can be specified with upper-case ‘B’ and ‘F’, as in ‘8B’ and
‘9F’. A local label defined for the current position is written with a ‘H’ appended to the
number:
3H LDB $0,$1,2
This and traditional local-label formats cannot be mixed: a label must be defined and
referred to using the same format.
There’s a minor caveat: just as for the ordinary local symbols, the local symbols are
translated into ordinary symbols using control characters are to hide the ordinal number
of the symbol. Unfortunately, these symbols are not translated back in error messages.
Thus you may see confusing error messages when local symbols are used. Control charac-
ters ‘\003’ (control-C) and ‘\004’ (control-D) are used for the MMIX-specific local-symbol
syntax.
The symbol ‘Main’ is handled specially; it is always global.
By defining the symbols ‘__.MMIX.start..text’ and ‘__.MMIX.start..data’, the ad-
dress of respectively the ‘.text’ and ‘.data’ segments of the final program can be defined,
though when linking more than one object file, the code or data in the object file containing
the symbol is not guaranteed to be start at that position; just the final executable. See
[MMIX-loc], page 229.
Similarly for special registers, local and global symbols can be used. Also, symbols
equated from numbers and constant expressions are allowed in place of a special reg-
ister, except when either of the options --no-predefined-syms and --fixed-special-
register-names are specified. Then only the special register names above are allowed for
the instructions having a special register operand; GET and PUT.
GREG
This directive reserves a global register, gives it an initial value and optionally
gives it a symbolic name. Some examples:
230 Using as
areg GREG
breg GREG data_value
GREG data_buffer
.greg creg, another_data_value
The symbolic register name can be used in place of a (non-special) register. If a
value isn’t provided, it defaults to zero. Unless the option ‘--no-merge-gregs’
is specified, non-zero registers allocated with this directive may be eliminated
by as; another register with the same value used in its place. Any of the in-
structions ‘CSWAP’, ‘GO’, ‘LDA’, ‘LDBU’, ‘LDB’, ‘LDHT’, ‘LDOU’, ‘LDO’, ‘LDSF’, ‘LDTU’,
‘LDT’, ‘LDUNC’, ‘LDVTS’, ‘LDWU’, ‘LDW’, ‘PREGO’, ‘PRELD’, ‘PREST’, ‘PUSHGO’, ‘STBU’,
‘STB’, ‘STCO’, ‘STHT’, ‘STOU’, ‘STSF’, ‘STTU’, ‘STT’, ‘STUNC’, ‘SYNCD’, ‘SYNCID’,
can have a value nearby an initial value in place of its second and third operands.
Here, “nearby” is defined as within the range 0. . . 255 from the initial value of
such an allocated register.
buffer1 BYTE 0,0,0,0,0
buffer2 BYTE 0,0,0,0,0
...
GREG buffer1
LDOU $42,buffer2
In the example above, the ‘Y’ field of the LDOUI instruction (LDOU with a
constant Z) will be replaced with the global register allocated for ‘buffer1’,
and the ‘Z’ field will have the value 5, the offset from ‘buffer1’ to ‘buffer2’.
The result is equivalent to this code:
buffer1 BYTE 0,0,0,0,0
buffer2 BYTE 0,0,0,0,0
...
tmpreg GREG buffer1
LDOU $42,tmpreg,(buffer2-buffer1)
Global registers allocated with this directive are allocated in order higher-to-
lower within a file. Other than that, the exact order of register allocation and
elimination is undefined. For example, the order is undefined when more than
one file with such directives are linked together. With the options ‘-x’ and
‘--linker-allocated-gregs’, ‘GREG’ directives for two-operand cases like the
one mentioned above can be omitted. Sufficient global registers will then be
allocated by the linker.
BYTE
The ‘BYTE’ directive takes a series of operands separated by a comma. If an
operand is a string (see Section 3.6.1.1 [Strings], page 31), each character of
that string is emitted as a byte. Other operands must be constant expres-
sions without forward references, in the range 0. . . 255. If you need operands
having expressions with forward references, use ‘.byte’ (see Section 7.9 [Byte],
page 52). An operand can be omitted, defaulting to a zero value.
WYDE
TETRA
OCTA
The directives ‘WYDE’, ‘TETRA’ and ‘OCTA’ emit constants of two, four and eight
bytes size respectively. Before anything else happens for the directive, the
Chapter 9: Machine Dependent Features 231
You can’t LOC to a lower address than those already visited (i.e., “backwards”).
A LOC directive must come before any emitted code.
Predefined symbols are visible as file-local symbols after use. (In the ELF file, that
is—the linked mmo file has no notion of a file-local symbol.)
Some mapping of constant expressions to sections in LOC expressions is attempted, but
that functionality is easily confused and should be avoided unless compatibility with mmixal
is required. A LOC expression to ‘0x2000000000000000’ or higher, maps to the ‘.data’
section and lower addresses map to the ‘.text’ section (see [MMIX-loc], page 229).
The code and data areas are each contiguous. Sparse programs with far-away LOC
directives will take up the same amount of space as a contiguous program with zeros filled
in the gaps between the LOC directives. If you need sparse programs, you might try and
get the wanted effect with a linker script and splitting up the code parts into sections (see
Section 7.78 [Section], page 72). Assembly code for this, to be compatible with mmixal,
would look something like:
.if 0
LOC away_expression
.else
.section away,"ax"
.fi
as will not execute the LOC directive and mmixal ignores the lines with .. This construct
can be used generally to help compatibility.
Symbols can’t be defined twice–not even to the same value.
Instruction mnemonics are recognized case-insensitive, though the ‘IS’ and ‘GREG’
pseudo-operations must be specified in upper-case characters.
There’s no unicode support.
The following is a list of programs in ‘mmix.tar.gz’, available at http://www-cs-faculty.stanford.edu/~k
last checked with the version dated 2001-08-25 (md5sum c393470cfc86fac040487d22d2bf0172)
that assemble with mmixal but do not assemble with as:
silly.mms
LOC to a previous address.
sim.mms Redefines symbol ‘Done’.
test.mms Uses the serial operator ‘&’.
Chapter 9: Machine Dependent Features 233
Note that this option can be stacked with the ‘-mn’ option so that the as-
sembler will both warn about missing NOP instructions and then insert them
automatically.
-mY disables warnings about missing NOP instructions.
-md mark the object file as one that requires data to copied from ROM to RAM at
execution startup. Disabled by default.
-mdata-region=region
Select the region data will be placed in. Region placement is performed by the
compiler and linker. The only effect this option will have on the assembler is
that if upper or either is selected, then the symbols to initialise high data and
bss will be defined. Valid region values are:
none
lower
upper
either
9.29.2 Syntax
9.29.2.1 Macros
The macro syntax used on the MSP 430 is like that described in the MSP 430 Family
Assembler Specification. Normal as macros should still work.
Additional built-in macros are:
llo(exp) Extracts least significant word from 32-bit expression ’exp’.
lhi(exp) Extracts most significant word from 32-bit expression ’exp’.
hlo(exp) Extracts 3rd word from 64-bit expression ’exp’.
hhi(exp) Extracts 4rd word from 64-bit expression ’exp’.
They normally being used as an immediate source operand.
mov #llo(1), r10 ; == mov #1, r10
mov #lhi(1), r10 ; == mov #0, r10
bne label A polymorph instruction which is ‘jne label’ or ‘jeq +4; br label’
blt label A polymorph instruction which is ‘jl label’ or ‘jge +4; br label’
bltn label
A polymorph instruction which is ‘jn label’ or ‘jn +2; jmp +4; br label’
bltu label
A polymorph instruction which is ‘jlo label’ or ‘jhs +2; br label’
bge label A polymorph instruction which is ‘jge label’ or ‘jl +4; br label’
bgeu label
A polymorph instruction which is ‘jhs label’ or ‘jlo +4; br label’
bgt label A polymorph instruction which is ‘jeq +2; jge label’ or ‘jeq +6; jl +4; br
label’
bgtu label
A polymorph instruction which is ‘jeq +2; jhs label’ or ‘jeq +6; jlo +4; br
label’
bleu label
A polymorph instruction which is ‘jeq label; jlo label’ or ‘jeq +2; jhs +4;
br label’
ble label A polymorph instruction which is ‘jeq label; jl label’ or ‘jeq +2; jge +4;
br label’
jump label
A polymorph instruction which is ‘jmp label’ or ‘br label’
236 Using as
9.29.5 Opcodes
as implements all the standard MSP 430 opcodes. No additional pseudo-instructions are
needed on this family.
For information on the 430 machine instruction set, see MSP430 User’s Manual, docu-
ment slau049d, Texas Instrument, Inc.
-m[no-]perf-ext
Enable/Disable Performance extension
-m[no-]perf2-ext
Enable/Disable Performance extension 2
-m[no-]string-ext
Enable/Disable String extension
-m[no-]reduced-regs
Enable/Disable Reduced Register configuration (GPR16) option
-m[no-]audio-isa-ext
Enable/Disable AUDIO ISA extension
-m[no-]fpu-sp-ext
Enable/Disable FPU SP extension
-m[no-]fpu-dp-ext
Enable/Disable FPU DP extension
-m[no-]fpu-fma
Enable/Disable FPU fused-multiply-add instructions
-mall-ext
Turn on all extensions and instructions support
9.30.2 Syntax
9.30.2.1 Special Characters
Use ‘#’ at column 1 and ‘!’ anywhere in the line except inside quotes.
Multiple instructions in a line are allowed though not recommended and should be
separated by ‘;’.
Assembler is not case-sensitive in general except user defined label. For example, ‘jral
F1’ is different from ‘jral f1’ while it is the same as ‘JRAL F1’.
Global pointer
Register $r29 is regarded as the global pointer.
Link pointer
Register $r30 is regarded as the link pointer.
Stack pointer
Register $r31 is regarded as the stack pointer.
not rt5,ra5
Alias of ‘nor rt5,ra5,ra5’.
neg rt5,ra5
Alias of ‘subri rt5,ra5,0’.
br rb5 Depending on how it is assembled, it is translated into ‘r5 rb5’ or ‘jr rb5’.
b label Branch to label depending on how it is assembled, it is translated into ‘j8
label’, ‘j label’, or "‘la $ta,label’ ‘br $ta’".
bral rb5 Alias of jral br5 depending on how it is assembled, it is translated into ‘jral5
rb5’ or ‘jral rb5’.
bal fname Alias of jal fname depending on how it is assembled, it is translated into ‘jal
fname’ or "‘la $ta,fname’ ‘bral $ta’".
call fname
Call function fname same as ‘jal fname’.
move rt5,ra5
For 16-bit, this is ‘mov55 rt5,ra5’. For no 16-bit, this is ‘ori rt5,ra5,0’.
move rt5,var
This is the same as ‘l.w rt5,var’.
move rt5,imm32
This is the same as ‘li rt5,imm32’.
pushm ra5,rb5
Push contents of registers from ra5 to rb5 into stack.
push ra5 Push content of register ra5 into stack. (same ‘pushm ra5,ra5’).
push.d var
Push value of double-word variable var into stack.
push.w var
Push value of word variable var into stack.
push.h var
Push value of half-word variable var into stack.
push.b var
Push value of byte variable var into stack.
pusha var Push 32-bit address of variable var into stack.
pushi imm32
Push 32-bit immediate value into stack.
popm ra5,rb5
Pop top of stack values into registers ra5 to rb5.
pop rt5 Pop top of stack value into register. (same as ‘popm rt5,rt5’.)
pop.d var,ra5
Pop value of double-word variable var from stack using register ra5 as 2nd
scratch register. (1st is $ta)
242 Using as
pop.w var,ra5
Pop value of word variable var from stack using register ra5.
pop.h var,ra5
Pop value of half-word variable var from stack using register ra5.
pop.b var,ra5
Pop value of byte variable var from stack using register ra5.
Chapter 9: Machine Dependent Features 243
9.31.2 Syntax
9.31.2.1 Special Characters
‘#’ is the line comment character. ‘;’ is the line separator character.
%hi(expression )
Extract the upper 16 bits of expression.
%lo(expression )
Extract the lower 16 bits of expression.
244 Using as
%gprel(expression )
Subtract the value of the symbol _gp from expression.
The intention of the %gprel relocation is to have a fast small area of memory
which only takes a 16-bit immediate to access.
.section .sdata
fastint:
.int 123
.section .text
ldw r4, %gprel(fastint)(gp)
%call(expression )
%call_lo(expression )
%call_hiadj(expression )
%got(expression )
%got_lo(expression )
%got_hiadj(expression )
%gotoff(expression )
%gotoff_lo(expression )
%gotoff_hiadj(expression )
%tls_gd(expression )
%tls_ie(expression )
%tls_le(expression )
%tls_ldm(expression )
%tls_ldo(expression )
These relocations support the ABI for Linux Systems documented in the Nios
II Processor Reference Handbook.
.set noat Allows assembly code to use at register without warning. Macro or relaxation
expansions generate warnings.
.set at Assembly code using at register generates warnings, and macro expansion and
relaxation are enabled.
.set nobreak
Allows assembly code to use ba and bt registers without warning.
.set break
Turns warnings back on for using ba and bt registers.
.set norelax
Do not replace any branches or calls.
.set relaxsection
Replace identified out-of-range branches with jmp sequences (default).
.set relaxsection
Replace all branch and call instructions with jmp and callr sequences.
.set ... All other .set are the normal use.
9.31.5 Opcodes
as implements all the standard Nios II opcodes documented in the Nios II Processor Ref-
erence Handbook, including the assembler pseudo-instructions.
246 Using as
-mlimited-eis | -mno-limited-eis
Enable (or disable) the use of the limited extended instruction set: MARK, RTT,
SOB, SXT, and XOR.
The -mno-limited-eis options also implies -mno-eis.
-mmfpt | -mno-mfpt
Enable (or disable) the use of the MFPT instruction.
-mmultiproc | -mno-multiproc
Enable (or disable) the use of multiprocessor instructions: TSTSET and WRTLCK.
-mmxps | -mno-mxps
Enable (or disable) the use of the MFPS and MTPS instructions.
-mspl | -mno-spl
Enable (or disable) the use of the SPL instruction.
Enable (or disable) the use of the microcode instructions: LDUB, MED, and XFC.
L2DR L2D
L3DR L3D
SYS TRAP
9.34.2 PJ Syntax
9.34.2.1 Special Characters
The presence of a ‘!’ or ‘/’ on a line indicates the start of a comment that extends to the
end of the current line.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment,
but in this case the line could also be a logical line number directive (see Section 3.3
[Comments], page 29) or a preprocessor control command (see Section 3.1 [Preprocessing],
page 29).
The ‘;’ character can be used to separate statements on the same line.
252 Using as
9.36.2 Syntax
9.36.2.1 Special Characters
‘#’ and ‘;’ are the line comment characters.
.8byte expression
Create an unaligned constant 8 bytes in size.
.16byte expression
Create an unaligned constant 16 bytes in size.
.set no_warn_regname_label
Do not output warnings when a label name matches a register name. Equivalent
to passing the -mno-warn-regname-label command line option.
9.36.5 Opcodes
as implements all the standard PRU core V3 opcodes in the original pasm assembler. Older
cores are not supported by as.
GAS also implements the LDI32 pseudo instruction for loading a 32-bit immediate value
into a register.
ldi32 sp, __stack_top
ldi32 r14, 0x12345678
Chapter 9: Machine Dependent Features 257
%hi16()
When loading a 20-bit (or wider) address into registers, this modifier selects
the 16 most significant bits.
movw ax,#%hi16(_sym)
%hi8()
When loading a 20-bit (or wider) address into registers, this modifier selects
the 8 bits that would go into CS or ES (i.e. bits 23..16).
mov es, #%hi8(_sym)
-mgcc-abi
This option tells the assembler that the old GCC ABI is being used by the
assembled code. With this version of the ABI function arguments that are
passed on the stack are aligned to a 32-bit boundary.
-mrx-abi This option tells the assembler that the official RX ABI is being used by the
assembled code. With this version of the ABI function arguments that are
passed on the stack are aligned to their natural alignments. This option is the
default.
-mcpu=name
This option tells the assembler the target CPU type. Currently the rx100,
rx200, rx600, rx610 and rxv2 are recognised as valid cpu names. Attempting
to assemble an instruction not supported by the indicated cpu type will result
in an error message being generated.
-mno-allow-string-insns
This option tells the assembler to mark the object file that it is building as one
that does not use the string instructions SMOVF, SCMPU, SMOVB, SMOVU, SUNTIL
SWHILE or the RMPA instruction. In addition the mark tells the linker to complain
if an attempt is made to link the binary with another one that does use any of
these instructions.
Note - the inverse of this option, -mallow-string-insns, is not needed. The
assembler automatically detects the use of the the instructions in the source
code and labels the resulting object file appropriately. If no string instructions
are detected then the object file is labelled as being one that can be linked with
either string-using or string-banned object files.
The modifier returns the offset from the gp symbol to the specified symbol as a 16-bit
value. The intent is that this offset should be used in a register+offset move instruction
when generating references to small data. Ie, like this:
mov.W %gp(_foo)[%gpreg], r1
The assembler also supports two meta register names which can be used to refer to
registers whose values may not be known to the programmer. These meta register names
are:
Both registers normally have the value r13, but this can change if some registers have
been reserved for use by interrupt handlers or if both the small data limit and position
independent data features are being used at the same time.
262 Using as
9.40.1 Options
The following table lists all available s390 specific options:
-m31 | -m64
Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
These options are only available with the ELF object file format, and require
that the necessary BFD support has been included (on a 31-bit platform you
must add –enable-64-bit-bfd on the call to the configure script to enable 64-bit
usage and use s390x as target platform).
-mesa | -mzarch
Select the architecture mode, either the Enterprise System Architecture (esa)
mode or the z/Architecture mode (zarch).
The 64-bit instructions are only available with the z/Architecture mode. The
combination of ‘-m64’ and ‘-mesa’ results in a warning message.
-march=CPU
This option specifies the target processor. The following processor names are
recognized: g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-
ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10) and z13
(or arch11).
Assembling an instruction that is not supported on the target processor results
in an error message.
The processor names starting with arch refer to the edition number in the
Principle of Operations manual. They can be used as alternate processor names
and have been added for compatibility with the IBM XL compiler.
arch3, g5 and g6 cannot be used with the ‘-mzarch’ option since the
z/Architecture mode is not supported on these processor levels.
There is no arch4 option supported. arch4 matches -march=arch5 -mesa.
-mregnames
Allow symbolic names for registers.
-mno-regnames
Do not allow symbolic names for registers.
-mwarn-areg-zero
Warn whenever the operand for a base or index register has been specified but
evaluates to zero. This can indicate the misuse of general purpose register 0 as
an address register.
264 Using as
Certain characters at the end of the mnemonic may describe a property of the instruction:
c the instruction uses a 8-bit character operand
There are many exceptions to the scheme outlined in the above lists, in particular for
the privileged instructions. For non-privileged instruction it works quite well, for example
the instruction ‘clgfr’ c: compare instruction, l: unsigned operands, g: 64-bit operands, f:
32- to 64-bit extension, r: register operands. The instruction compares an 64-bit value in a
register with the zero extended 32-bit value from a second register. For a complete list of
all mnemonics see appendix B in the Principles of Operation.
Dn(Ln,Bn)
the address for operand number n is formed from the content of general register
Bn called the base register and the displacement field Dn. The length of the
operand n is specified by the field Ln.
The base registers Bn and the index registers Xn of a storage operand can be skipped.
If Bn and Xn are skipped, a zero will be stored to the operand field. The notation changes
as follows:
Dn(0,Bn) Dn(Bn)
Dn(0,0) Dn
Dn(0) Dn
Dn(Ln,0) Dn(Ln)
An instruction is two, four, or six bytes in length and must be aligned on a 2 byte
boundary. The first two bits of the instruction specify the length of the instruction, 00
268 Using as
indicates a two byte instruction, 01 and 10 indicates a four byte instruction, and 11 indicates
a six byte instruction.
The following table lists the s390 instruction formats that are available with the ‘.insn’
pseudo directive:
E format
+-------------+
| OpCode |
+-------------+
0 15
RI format: <insn> R1,I2
+--------+----+----+------------------+
| OpCode | R1 |OpCd| I2 |
+--------+----+----+------------------+
0 8 12 16 31
RIE format: <insn> R1,R3,I2
+--------+----+----+------------------+--------+--------+
| OpCode | R1 | R3 | I2 |////////| OpCode |
+--------+----+----+------------------+--------+--------+
0 8 12 16 32 40 47
RIL format: <insn> R1,I2
+--------+----+----+------------------------------------+
| OpCode | R1 |OpCd| I2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
RILU format: <insn> R1,U2
+--------+----+----+------------------------------------+
| OpCode | R1 |OpCd| U2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
RIS format: <insn> R1,I2,M3,D4(B4)
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 36 47
RR format: <insn> R1,R2
+--------+----+----+
| OpCode | R1 | R2 |
+--------+----+----+
0 8 12 15
RRE format: <insn> R1,R2
+------------------+--------+----+----+
| OpCode |////////| R1 | R2 |
+------------------+--------+----+----+
Chapter 9: Machine Dependent Features 269
0 16 24 28 31
RRF format: <insn> R1,R2,R3,M4
+------------------+----+----+----+----+
| OpCode | R3 | M4 | R1 | R2 |
+------------------+----+----+----+----+
0 16 20 24 28 31
RRS format: <insn> R1,R2,M3,D4(B4)
+--------+----+----+----+-------------+----+----+--------+
| OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
+--------+----+----+----+-------------+----+----+--------+
0 8 12 16 20 32 36 40 47
RS format: <insn> R1,R3,D2(B2)
+--------+----+----+----+-------------+
| OpCode | R1 | R3 | B2 | D2 |
+--------+----+----+----+-------------+
0 8 12 16 20 31
RSE format: <insn> R1,R3,D2(B2)
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
RSI format: <insn> R1,R3,I2
+--------+----+----+------------------------------------+
| OpCode | R1 | R3 | I2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
RSY format: <insn> R1,R3,D2(B2)
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
RX format: <insn> R1,D2(X2,B2)
+--------+----+----+----+-------------+
| OpCode | R1 | X2 | B2 | D2 |
+--------+----+----+----+-------------+
0 8 12 16 20 31
RXE format: <insn> R1,D2(X2,B2)
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
RXF format: <insn> R1,R3,D2(X2,B2)
+--------+----+----+----+-------------+----+---+--------+
270 Using as
For the complete list of all instruction format variants see the Principles of Operation
manuals.
In the mnemonic for a branch instruction the condition code string <m> can be any of
the following:
o jump on overflow / if ones
h jump on A high
p jump on plus
l jump on A low
m jump on minus
e jump on A equal B
For the compare and branch, and compare and trap instructions there are 12 condition
code strings that can be used as part of the mnemonic in place of a mask operand in the
instruction format:
In the mnemonic for a compare and branch and compare and trap instruction the con-
dition code string <m> can be any of the following:
h jump on A high
l jump on A low
e jump on A equal B
@pltoff The @pltoff modifier can be used for 16-bit immediate fields. The symbol term is
replaced with the offset from the start of the PLT to the address of the symbol.
@gotntpoff
The @gotntpoff modifier can be used for displacement fields. The symbol is
added to the static TLS block and the negated offset to the symbol in the
static TLS block is added to the GOT. The symbol term is replaced with the
offset to the GOT slot from the start of the GOT.
@indntpoff
The @indntpoff modifier can be used for 32-bit pc-relative immediate fields. The
symbol is added to the static TLS block and the negated offset to the symbol
in the static TLS block is added to the GOT. The symbol term is replaced with
the pc-relative offset to the GOT slot from the current instruction address.
For more information about the thread local storage modifiers ‘gotntpoff’ and
‘indntpoff’ see the ELF extension documentation ‘ELF Handling For Thread-Local
Storage’.
:lit2 The literal pool entry is created as a 16 bit value. The operand modifier @got
may be used in the original expression. The term ‘x@got:lit2’ will put the got
offset for the global symbol x to the literal pool as 16 bit value.
:lit4 The literal pool entry is created as a 32-bit value. The operand modifier @got
and @plt may be used in the original expression. The term ‘x@got:lit4’ will
put the got offset for the global symbol x to the literal pool as a 32-bit value.
The term ‘x@plt:lit4’ will put the plt offset for the global symbol x to the
literal pool as a 32-bit value.
:lit8 The literal pool entry is created as a 64-bit value. The operand modifier @got
and @plt may be used in the original expression. The term ‘x@got:lit8’ will
put the got offset for the global symbol x to the literal pool as a 64-bit value.
The term ‘x@plt:lit8’ will put the plt offset for the global symbol x to the
literal pool as a 64-bit value.
The assembler directive ‘.ltorg’ is used to emit all literal pool entries to the current
position.
with the offset from the start of the GOT to the jump slot for the
symbol.
@plt The @plt modifier can be used for .long and .quad. A procedure
linkage table entry us generated for the symbol. The symbol term
is replaced with the address of the PLT entry for the symbol.
@pltoff The @pltoff modifier can be used for .short, .long and .quad. The
symbol term is replaced with the offset from the start of the PLT
to the address of the symbol.
@tlsgd
@tlsldm The @tlsgd and @tlsldm modifier can be used for .long and .quad.
A tls index structure for the symbol is added to the GOT. The
symbol term is replaced with the offset from the start of the GOT
to the tls index structure.
@gotntpoff
@indntpoff
The @gotntpoff and @indntpoff modifier can be used for .long and
.quad. The symbol is added to the static TLS block and the negated
offset to the symbol in the static TLS block is added to the GOT.
For @gotntpoff the symbol term is replaced with the offset from the
start of the GOT to the GOT slot, for @indntpoff the symbol term
is replaced with the address of the GOT slot.
@dtpoff The @dtpoff modifier can be used for .long and .quad. The symbol
term is replaced with the offset of the symbol relative to the start
of the TLS block it is contained in.
@ntpoff The @ntpoff modifier can be used for .long and .quad. The symbol
term is replaced with the offset of the symbol relative to the TCB
pointer.
For more information about the thread local storage modifiers see the ELF
extension documentation ‘ELF Handling For Thread-Local Storage’.
.ltorg This directive causes the current contents of the literal pool to be dumped to
the current location (Section 9.40.3.8 [s390 Literal Pool Entries], page 275).
.machine STRING [+EXTENSION ]...
This directive allows changing the machine for which code is generated. string
may be any of the -march= selection options, or push, or pop. .machine push
saves the currently selected cpu, which may be restored with .machine pop. Be
aware that the cpu string has to be put into double quotes in case it contains
characters not appropriate for identifiers. So you have to write "z9-109" instead
of just z9-109. Extensions can be specified after the cpu name, separated by
plus characters. Valid extensions are: htm, nohtm, vx, novx. They extend the
basic instruction set with features from a higher cpu level, or remove support
for a feature from the given cpu level.
Example: z13+nohtm allows all instructions of the z13 cpu except instructions
from the HTM facility.
278 Using as
.machinemode string
This directive allows to change the architecture mode for which code is be-
ing generated. string may be esa, zarch, zarch_nohighgprs, push, or pop.
.machinemode zarch_nohighgprs can be used to prevent the highgprs flag
from being set in the ELF header of the output file. This is useful in situations
where the code is gated with a runtime check which makes sure that the code is
only executed on kernels providing the highgprs feature. .machinemode push
saves the currently selected mode, which may be restored with .machinemode
pop.
set nor1 Let the assembler to generate warnings if the source program uses r1. (Default)
.sdata Tell the assembler to add subsequent data into the sdata section
.rdata Tell the assembler to add subsequent data into the rdata section
.frame "frame-register", "offset", "return-pc-register"
Describe a stack frame. "frame-register" is the frame register, "offset" is the dis-
tance from the frame register to the virtual frame pointer, "return-pc-register"
is the return program register. You must use ".ent" before ".frame" and only
one ".frame" can be used per ".ent".
.mask "bitmask", "frameoffset"
Indicate which of the integer registers are saved in the current function’s stack
frame, this is for the debugger to explain the frame chain.
.ent "proc-name"
Set the beginning of the procedure "proc name". Use this directive when you
want to generate information for the debugger.
.end proc-name
Set the end of a procedure. Use this directive to generate information for the
debugger.
.bss Switch the destination of following statements into the bss section, which is
used for data that is uninitialized anywhere.
--renesas
Disable optimization with section symbol for compatibility with Renesas as-
sembler.
--allow-reg-prefix
Allow ’$’ as a register name prefix.
--isa=sh4 | sh4a
Specify the sh4 or sh4a instruction set.
--isa=dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
--isa=all
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
-h-tick-hex
Support H’00 style hex constants in addition to 0x00 style.
9.42.2 Syntax
9.42.2.1 Special Characters
‘!’ is the line comment character.
You can use ‘;’ instead of a newline to separate statements.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment,
but in this case the line could also be a logical line number directive (see Section 3.3
[Comments], page 29) or a preprocessor control command (see Section 3.1 [Preprocessing],
page 29).
Since ‘$’ has no special meaning, you may use it in symbol names.
282 Using as
SH2E and SH3E support single-precision floating point calculations as well as entirely
PCAPI compatible emulation of double-precision floating point calculations. SH2E and
SH3E instructions are a subset of the floating point calculations conforming to the IEEE754
standard.
In addition to single-precision and double-precision floating-point operation capability,
the on-chip FPU of SH4 has a 128-bit graphic engine that enables 32-bit floating-point
data to be processed 128 bits at a time. It also supports 4 * 4 array operations and inner
product operations. Also, a superscalar architecture is employed that enables simultaneous
execution of two instructions (including FPU instructions), providing performance of up to
twice that of conventional architectures at the same frequency.
9.42.5 Opcodes
For detailed information on the SH machine instruction set, see SH-Microcomputer User’s
Manual (Renesas) or SH-4 32-bit CPU Core Architecture (SuperH) and SuperH (SH) 64-Bit
RISC Series (SuperH).
as implements all the standard SH opcodes. No additional pseudo-instructions are
needed on this family. Note, however, that because as supports a simpler form of PC-
relative addressing, you may simply write (for example)
mov.l bar,r0
where other assemblers might require an explicit displacement to bar from the program
counter:
mov.l @(disp , PC)
284 Using as
9.43.2 Syntax
9.43.2.1 Special Characters
‘!’ is the line comment character.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment,
but in this case the line could also be a logical line number directive (see Section 3.3
[Comments], page 29) or a preprocessor control command (see Section 3.1 [Preprocessing],
page 29).
Chapter 9: Machine Dependent Features 285
.abi [32|64]
Specify the ABI for the following instructions. Note that you cannot use this di-
rective unless you specified an ABI on the command line, and the ABIs specified
must match.
9.43.4 Opcodes
For detailed information on the SH64 machine instruction set, see SuperH 64 bit RISC
Series Architecture Manual (SuperH, Inc.).
as implements all the standard SH64 opcodes. In addition, the following pseudo-opcodes
may be expanded into one or more alternate opcodes:
movi If the value doesn’t fit into a standard movi opcode, as will replace the movi
with a sequence of movi and shori opcodes.
pt This expands to a sequence of movi and shori opcode, followed by a ptrel
opcode, or to a pta or ptb opcode, depending on the label referenced.
Chapter 9: Machine Dependent Features 287
9.44.3.3 Constants
Several Sparc instructions take an immediate operand field for which mnemonic names
exist. Two such examples are ‘membar’ and ‘prefetch’. Another example are the set of V9
memory access instruction that allow specification of an address space identifier.
The ‘membar’ instruction specifies a memory barrier that is the defined by the operand
which is a bitmask. The supported mask mnemonics are:
• ‘#Sync’ requests that all operations (including nonmemory reference operations) ap-
pearing prior to the membar must have been performed and the effects of any excep-
tions become visible before any instructions after the membar may be initiated. This
corresponds to membar cmask field bit 2.
• ‘#MemIssue’ requests that all memory reference operations appearing prior to the
membar must have been performed before any memory operation after the membar
may be initiated. This corresponds to membar cmask field bit 1.
• ‘#Lookaside’ requests that a store appearing prior to the membar must complete before
any load following the membar referencing the same address can be initiated. This
corresponds to membar cmask field bit 0.
• ‘#StoreStore’ defines that the effects of all stores appearing prior to the membar in-
struction must be visible to all processors before the effect of any stores following the
membar. Equivalent to the deprecated stbar instruction. This corresponds to membar
mmask field bit 3.
292 Using as
• ‘#LoadStore’ defines all loads appearing prior to the membar instruction must have
been performed before the effect of any stores following the membar is visible to any
other processor. This corresponds to membar mmask field bit 2.
• ‘#StoreLoad’ defines that the effects of all stores appearing prior to the membar in-
struction must be visible to all processors before loads following the membar may be
performed. This corresponds to membar mmask field bit 1.
• ‘#LoadLoad’ defines that all loads appearing prior to the membar instruction must have
been performed before any loads following the membar may be performed. This corre-
sponds to membar mmask field bit 0.
The actual behavior of a given prefetch function code is processor specific. If a processor
does not implement a given prefetch function code, it will treat the prefetch instruction
as a nop.
For instructions that accept an immediate address space identifier, as provides many
mnemonics corresponding to V9 defined as well as UltraSPARC and Niagara extended
values. For example, ‘#ASI_P’ and ‘#ASI_BLK_INIT_QUAD_LDD_AIUS’. See the V9 and
processor specific manuals for details.
9.44.3.4 Relocations
ELF relocations are available as defined in the 32-bit and 64-bit Sparc ELF specifications.
R_SPARC_HI22 is obtained using ‘%hi’ and R_SPARC_LO10 is obtained using ‘%lo’. Like-
wise R_SPARC_HIX22 is obtained from ‘%hix’ and R_SPARC_LOX10 is obtained using ‘%lox’.
For example:
sethi %hi(symbol), %g1
or %g1, %lo(symbol), %g1
Several relocations exist to allow the link editor to potentially optimize GOT data refer-
ences. The R_SPARC_GOTDATA_OP_HIX22 relocation can obtained by enclosing an operand
inside of ‘%gdop_hix22’. The R_SPARC_GOTDATA_OP_LOX10 relocation can obtained by en-
closing an operand inside of ‘%gdop_lox10’. Likewise, R_SPARC_GOTDATA_OP can be ob-
tained by enclosing an operand inside of ‘%gdop’. For example, assuming the GOT base is
in register %l7:
sethi %gdop_hix22(symbol), %l1
xor %l1, %gdop_lox10(symbol), %l1
ld [%l7 + %l1], %l2, %gdop(symbol)
There are many relocations that can be requested for access to thread local storage
variables. All of the Sparc TLS mnemonics are supported:
• R_SPARC_TLS_GD_HI22 is requested using ‘%tgd_hi22’.
• R_SPARC_TLS_GD_LO10 is requested using ‘%tgd_lo10’.
• R_SPARC_TLS_GD_ADD is requested using ‘%tgd_add’.
• R_SPARC_TLS_GD_CALL is requested using ‘%tgd_call’.
• R_SPARC_TLS_LDM_HI22 is requested using ‘%tldm_hi22’.
• R_SPARC_TLS_LDM_LO10 is requested using ‘%tldm_lo10’.
• R_SPARC_TLS_LDM_ADD is requested using ‘%tldm_add’.
• R_SPARC_TLS_LDM_CALL is requested using ‘%tldm_call’.
• R_SPARC_TLS_LDO_HIX22 is requested using ‘%tldo_hix22’.
• R_SPARC_TLS_LDO_LOX10 is requested using ‘%tldo_lox10’.
• R_SPARC_TLS_LDO_ADD is requested using ‘%tldo_add’.
• R_SPARC_TLS_IE_HI22 is requested using ‘%tie_hi22’.
• R_SPARC_TLS_IE_LO10 is requested using ‘%tie_lo10’.
• R_SPARC_TLS_IE_LD is requested using ‘%tie_ld’.
• R_SPARC_TLS_IE_LDX is requested using ‘%tie_ldx’.
• R_SPARC_TLS_IE_ADD is requested using ‘%tie_add’.
• R_SPARC_TLS_LE_HIX22 is requested using ‘%tle_hix22’.
• R_SPARC_TLS_LE_LOX10 is requested using ‘%tle_lox10’.
Here are some example TLS model sequences.
First, General Dynamic:
sethi %tgd_hi22(symbol), %l1
add %l1, %tgd_lo10(symbol), %l1
add %l7, %l1, %o0, %tgd_add(symbol)
call __tls_get_addr, %tgd_call(symbol)
nop
Local Dynamic:
sethi %tldm_hi22(symbol), %l1
add %l1, %tldm_lo10(symbol), %l1
add %l7, %l1, %o0, %tldm_add(symbol)
call __tls_get_addr, %tldm_call(symbol)
Chapter 9: Machine Dependent Features 295
nop
st %o1, [%o0]
sta %o2, [%o0] %asi
sll %o3, 3, %o3
srl %o4, 8, %o4
sra %o5, 12, %o5
cas [%o0], %o1, %o2
casa [%o0] %asi, %o1, %o2
clr %g1
And in 64-bit mode as will emit:
ldx [%o0], %o1
ldxa [%o0] %asi, %o2
stx %o1, [%o0]
stxa %o2, [%o0] %asi
sllx %o3, 3, %o3
srlx %o4, 8, %o4
srax %o5, 12, %o5
casx [%o0], %o1, %o2
casxa [%o0] %asi, %o1, %o2
clrx %g1
Finally, the ‘.nword’ translating directive is supported as well. It is documented in the
section on Sparc machine directives.
.reserve This must be followed by a symbol name, a positive number, and "bss". This
behaves somewhat like .lcomm, but the syntax is different.
.seg This must be followed by "text", "data", or "data1". It behaves like .text,
.data, or .data 1.
.skip This is functionally identical to the .space directive.
.word On the Sparc, the .word directive produces 32 bit values, instead of the 16 bit
values it produces on many other machines.
.xword On the Sparc V9 processor, the .xword directive produces 64 bit values.
298 Using as
9.45.2 Blocking
A blocked section or memory block is guaranteed not to cross the blocking boundary (usually
a page, or 128 words) if it is smaller than the blocking size, or to start on a page boundary
if it is larger than the blocking size.
.asg "x",SYM1
.asg "SYM1",SYM2
.asg "SYM2",x
add x,a ; final code assembled is "add x, a"
Macro parameters are converted to subsyms; a side effect of this is the normal as ’\ARG’
dereferencing syntax is unnecessary. Subsyms defined within a macro will have global
scope, unless the .var directive is used to identify the subsym as a local macro variable see
Section 9.45.9 [.var], page 301.
Substitution may be forced in situations where replacement might be ambiguous by
placing colons on either side of the subsym. The following code:
.eval "10",x
LAB:X: add #x, a
When assembled becomes:
LAB10 add #10, a
Smaller parts of the string assigned to a subsym may be accessed with the following
syntax:
:symbol (char_index ):
Evaluates to a single-character string, the character at char index.
:symbol (start ,length ):
Evaluates to a substring of symbol beginning at start with length length.
$atan2(expr1 ,expr2 )
Returns the floating point arctangent of expr1 / expr2.
$ceil(expr )
Returns the smallest integer not less than expr as floating point.
$cosh(expr )
Returns the floating point hyperbolic cosine of expr.
$cos(expr )
Returns the floating point cosine of expr.
$cvf(expr )
Returns the integer value expr converted to floating-point.
$cvi(expr )
Returns the floating point value expr converted to integer.
$exp(expr )
Returns the floating point value e ^ expr.
$fabs(expr )
Returns the floating point absolute value of expr.
$floor(expr )
Returns the largest integer that is not greater than expr as floating point.
$fmod(expr1 ,expr2 )
Returns the floating point remainder of expr1 / expr2.
$int(expr )
Returns 1 if expr evaluates to an integer, zero otherwise.
$ldexp(expr1 ,expr2 )
Returns the floating point value expr1 * 2 ^ expr2.
$log10(expr )
Returns the base 10 logarithm of expr.
$log(expr )
Returns the natural logarithm of expr.
$max(expr1 ,expr2 )
Returns the floating point maximum of expr1 and expr2.
$min(expr1 ,expr2 )
Returns the floating point minimum of expr1 and expr2.
$pow(expr1 ,expr2 )
Returns the floating point value expr1 ^ expr2.
$round(expr )
Returns the nearest integer to expr as a floating point number.
$sgn(expr )
Returns -1, 0, or 1 based on the sign of expr.
Chapter 9: Machine Dependent Features 301
$sin(expr )
Returns the floating point sine of expr.
$sinh(expr )
Returns the floating point hyperbolic sine of expr.
$sqrt(expr )
Returns the floating point square root of expr.
$tan(expr )
Returns the floating point tangent of expr.
$tanh(expr )
Returns the floating point hyperbolic tangent of expr.
$trunc(expr )
Returns the integer value of expr truncated towards zero as floating point.
9.45.9 Directives
.align [size ]
.even Align the section program counter on the next boundary, based on size. size
may be any power of 2. .even is equivalent to .align with a size of 2.
1 Align SPC to word boundary
2 Align SPC to longword boundary (same as .even)
128 Align SPC to page boundary
.asg string , name
Assign name the string string. String replacement is performed on string before
assignment.
.eval string , name
Evaluate the contents of string string and assign the result as a string to the
subsym name. String replacement is performed on string before assignment.
.bss symbol , size [, [blocking_flag ] [,alignment_flag ]]
Reserve space for symbol in the .bss section. size is in words. If present, block-
ing flag indicates the allocated space should be aligned on a page boundary if
it would otherwise cross a page boundary. If present, alignment flag causes the
assembler to allocate size on a long word boundary.
302 Using as
bits, the value will be truncated. Successive .field directives will pack starting
at the current word, filling the most significant bits first, and aligning to the
start of the next word if the field size does not fit into the space remaining in
the current word. A .align directive with an operand of 1 will force the next
.field directive to begin packing into a new word. If a label is used, it points
to the word that contains the specified field.
.label symbol
Define a special symbol to refer to the load time address of the current section
program counter.
.length
.width Set the page length and width of the output listing file. Ignored.
.list
.nolist Control whether the source listing is printed. Ignored.
.loop [count ]
.break [condition ]
.endloop Repeatedly assemble a block of code. .loop begins the block, and .endloop
marks its termination. count defaults to 1024, and indicates the number of times
the block should be repeated. .break terminates the loop so that assembly
begins after the .endloop directive. The optional condition will cause the loop
to terminate only if it evaluates to zero.
304 Using as
word, filling the most-significant bits first. Unused space is zero-filled. If a label
is used, it points to the first word initialized.
[stag ] .struct [offset ]
[name_1 ] element [count_1 ]
[name_2 ] element [count_2 ]
[tname ] .tag stagx [tcount ]
...
[name_n ] element [count_n ]
[ssize ] .endstruct
label .tag [stag ]
Assign symbolic offsets to the elements of a structure. stag defines a symbol
to use to reference the structure. offset indicates a starting value to use for the
first element encountered; otherwise it defaults to zero. Each element can have
a named offset, name, which is a symbol assigned the value of the element’s
offset into the structure. If stag is missing, these become global symbols. count
adjusts the offset that many times, as if element were an array. element may
be one of .byte, .word, .long, .float, or any equivalent of those, and the
structure offset is adjusted accordingly. .field and .string are also allowed;
the size of .field is one bit, and .string is considered to be one word in
size. Only element descriptors, structure/union tags, .align and conditional
assembly directives are allowed within .struct/.endstruct. .align aligns
member offsets to word boundaries only. ssize, if provided, will always be
assigned the size of the structure.
The .tag directive, in addition to being used to define a structure/union ele-
ment within a structure, may be used to apply a structure to a symbol. Once
applied to label, the individual structure elements may be applied to label to
produce the desired offsets using label as the structure base.
.tab Set the tab size in the output listing. Ignored.
[utag ] .union
[name_1 ] element [count_1 ]
[name_2 ] element [count_2 ]
[tname ] .tag utagx [,tcount ]
...
[name_n ] element [count_n ]
[usize ] .endstruct
label .tag [utag ]
Similar to .struct, but the offset after each element is reset to zero, and the
usize is set to the maximum of all defined elements. Starting offset for the
union is always zero.
[symbol ] .usect "section_name ", size , [,[blocking_flag ] [,alignment_flag ]]
Reserve space for variables in a named, uninitialized section (similar to .bss).
.usect allows definitions sections independent of .bss. symbol points to the
first location reserved by this allocation. The symbol may be used as a variable
name. size is the allocated size in words. blocking flag indicates whether to
block this section on a page boundary (128 words) (see Section 9.45.2 [TIC54X-
306 Using as
Block], page 298). alignment flag indicates whether the section should be
longword-aligned.
.var sym [,..., sym_n ]
Define a subsym to be a local variable within a macro. See See Section 9.45.10
[TIC54X-Macros], page 306.
.version version
Set which processor to build instructions for. Though the following values are
accepted, the op is ignored.
541
542
543
545
545LP
546LP
548
549
9.45.10 Macros
Macros do not require explicit dereferencing of arguments (i.e., \ARG).
During macro expansion, the macro parameters are converted to subsyms. If the number
of arguments passed the macro invocation exceeds the number of parameters defined, the last
parameter is assigned the string equivalent of all remaining arguments. If fewer arguments
are given than parameters, the missing parameters are assigned empty strings. To include
a comma in an argument, you must enclose the argument in quotes.
The following built-in subsym functions allow examination of the string value of subsyms
(or ordinary strings). The arguments are strings unless otherwise indicated (subsyms passed
as args will be replaced by the strings they represent).
$symlen(str )
Returns the length of str.
$symcmp(str1 ,str2 )
Returns 0 if str1 == str2, non-zero otherwise.
$firstch(str ,ch )
Returns index of the first occurrence of character constant ch in str.
$lastch(str ,ch )
Returns index of the last occurrence of character constant ch in str.
$isdefed(symbol )
Returns zero if the symbol symbol is not in the symbol table, non-zero other-
wise.
$ismember(symbol ,list )
Assign the first member of comma-separated string list to symbol; list is re-
assigned the remainder of the list. Returns zero if list is a null string. Both
arguments must be subsyms.
Chapter 9: Machine Dependent Features 307
$iscons(expr )
Returns 1 if string expr is binary, 2 if octal, 3 if hexadecimal, 4 if a character,
5 if decimal, and zero if not an integer.
$isname(name )
Returns 1 if name is a valid symbol name, zero otherwise.
$isreg(reg )
Returns 1 if reg is a valid predefined register name (AR0-AR7 only).
$structsz(stag )
Returns the size of the structure or union represented by stag.
$structacc(stag )
Returns the reference point of the structure or union represented by stag. Al-
ways returns zero.
Instruction, register and functional unit names are case-insensitive. as requires fully-
specified functional unit names, such as ‘.S1’, ‘.L1X’ or ‘.D1T2’, on all instructions using a
functional unit.
For some instructions, there may be syntactic ambiguity between register or functional
unit names and the names of labels or other symbols. To avoid this, enclose the ambiguous
symbol name in parentheses; register and functional unit names may not be enclosed in
parentheses.
9.47.2 Syntax
Block comments are delimited by ‘/*’ and ‘*/’. End of line comments may be introduced
by ‘#’.
Instructions consist of a leading opcode or macro name followed by whitespace and an
optional comma-separated list of operands:
opcode [operand , ...]
Instructions must be separated by a newline or semicolon.
There are two ways to write code: either write naked instructions, which the assembler
is free to combine into VLIW bundles, or specify the VLIW bundles explicitly.
Bundles are specified using curly braces:
{ add r3,r4,r5 ; add r7,r8,r9 ; lw r10,r11 }
A bundle can span multiple lines. If you want to put multiple instructions on a line,
whether in a bundle or not, you need to separate them with semicolons as in this example.
A bundle may contain one or more instructions, up to the limit specified by the ISA
(currently three). If fewer instructions are specified than the hardware supports in a bundle,
the assembler inserts fnop instructions automatically.
The assembler will prefer to preserve the ordering of instructions within the bundle,
putting the first instruction in a lower-numbered pipeline than the next one, etc. This fact,
combined with the optional use of explicit fnop or nop instructions, allows precise control
over which pipeline executes each instruction.
If the instructions cannot be bundled in the listed order, the assembler will automatically
try to find a valid pipeline assignment. If there is no way to bundle the instructions together,
the assembler reports an error.
The assembler does not yet auto-bundle (automatically combine multiple instructions
into one bundle), but it reserves the right to do so in the future. If you want to force an
instruction to run by itself, put it in a bundle explicitly with curly braces and use nop
instructions (not fnop) to fill the remaining pipeline slots in that bundle.
r54 sp
r55 lr
r56 sn
r57 idn0
r58 idn1
r59 udn0
r60 udn1
r61 udn2
r62 udn3
r63 zero
The assembler will emit a warning if a numeric name is used instead of the non-numeric
name. The .no_require_canonical_reg_names assembler pseudo-op turns off this warn-
ing. .require_canonical_reg_names turns it back on.
hw0_got
This modifier is used to load bits 0-15 of the symbol’s offset in the GOT entry
corresponding to the symbol.
hw0_last_got
This modifier yields the same value as hw0_got, but it also checks that the
value does not overflow.
hw1_last_got
This modifier is used to load bits 16-31 of the symbol’s offset in the GOT entry
corresponding to the symbol, and it also checks that the value does not overflow.
plt
This modifier is used for function symbols. It causes a procedure linkage table,
an array of code stubs, to be created at the time the shared object is created
or linked against, together with a global offset table entry. The value is a pc-
relative offset to the corresponding stub code in the procedure linkage table.
This arrangement causes the run-time symbol resolver to be called to look up
and set the value of the symbol the first time the function is called (at latest;
depending environment variables). It is only safe to leave the symbol unresolved
this way if all references are function calls.
hw0_plt
This modifier is used to load bits 0-15 of the pc-relative address of a plt entry.
hw1_plt
This modifier is used to load bits 16-31 of the pc-relative address of a plt entry.
hw1_last_plt
This modifier yields the same value as hw1_plt, but it also checks that the
value does not overflow.
hw2_last_plt
This modifier is used to load bits 32-47 of the pc-relative address of a plt entry,
and it also checks that the value does not overflow.
hw0_tls_gd
This modifier is used to load bits 0-15 of the offset of the GOT entry of the
symbol’s TLS descriptor, to be used for general-dynamic TLS accesses.
hw0_last_tls_gd
This modifier yields the same value as hw0_tls_gd, but it also checks that the
value does not overflow.
hw1_last_tls_gd
This modifier is used to load bits 16-31 of the offset of the GOT entry of the
symbol’s TLS descriptor, to be used for general-dynamic TLS accesses. It also
checks that the value does not overflow.
314 Using as
hw0_tls_ie
This modifier is used to load bits 0-15 of the offset of the GOT entry containing
the offset of the symbol’s address from the TCB, to be used for initial-exec TLS
accesses.
hw0_last_tls_ie
This modifier yields the same value as hw0_tls_ie, but it also checks that the
value does not overflow.
hw1_last_tls_ie
This modifier is used to load bits 16-31 of the offset of the GOT entry containing
the offset of the symbol’s address from the TCB, to be used for initial-exec TLS
accesses. It also checks that the value does not overflow.
hw0_tls_le
This modifier is used to load bits 0-15 of the offset of the symbol’s address from
the TCB, to be used for local-exec TLS accesses.
hw0_last_tls_le
This modifier yields the same value as hw0_tls_le, but it also checks that the
value does not overflow.
hw1_last_tls_le
This modifier is used to load bits 16-31 of the offset of the symbol’s address
from the TCB, to be used for local-exec TLS accesses. It also checks that the
value does not overflow.
tls_gd_call
This modifier is used to tag an instruction as the “call” part of a calling sequence
for a TLS GD reference of its operand.
tls_gd_add
This modifier is used to tag an instruction as the “add” part of a calling sequence
for a TLS GD reference of its operand.
tls_ie_load
This modifier is used to tag an instruction as the “load” part of a calling
sequence for a TLS IE reference of its operand.
.require_canonical_reg_names
Require that canonical register names be used, and emit a warning if the nu-
meric names are used. This is on by default.
.no_require_canonical_reg_names
Permit the use of numeric names for registers that have canonical names.
316 Using as
9.48.2 Syntax
Block comments are delimited by ‘/*’ and ‘*/’. End of line comments may be introduced
by ‘#’.
Instructions consist of a leading opcode or macro name followed by whitespace and an
optional comma-separated list of operands:
opcode [operand , ...]
Instructions must be separated by a newline or semicolon.
There are two ways to write code: either write naked instructions, which the assembler
is free to combine into VLIW bundles, or specify the VLIW bundles explicitly.
Bundles are specified using curly braces:
{ add r3,r4,r5 ; add r7,r8,r9 ; lw r10,r11 }
A bundle can span multiple lines. If you want to put multiple instructions on a line,
whether in a bundle or not, you need to separate them with semicolons as in this example.
A bundle may contain one or more instructions, up to the limit specified by the ISA
(currently three). If fewer instructions are specified than the hardware supports in a bundle,
the assembler inserts fnop instructions automatically.
The assembler will prefer to preserve the ordering of instructions within the bundle,
putting the first instruction in a lower-numbered pipeline than the next one, etc. This fact,
combined with the optional use of explicit fnop or nop instructions, allows precise control
over which pipeline executes each instruction.
If the instructions cannot be bundled in the listed order, the assembler will automatically
try to find a valid pipeline assignment. If there is no way to bundle the instructions together,
the assembler reports an error.
The assembler does not yet auto-bundle (automatically combine multiple instructions
into one bundle), but it reserves the right to do so in the future. If you want to force an
instruction to run by itself, put it in a bundle explicitly with curly braces and use nop
instructions (not fnop) to fill the remaining pipeline slots in that bundle.
r56 sn
r57 idn0
r58 idn1
r59 udn0
r60 udn1
r61 udn2
r62 udn3
r63 zero
The assembler will emit a warning if a numeric name is used instead of the canonical
name. The .no_require_canonical_reg_names assembler pseudo-op turns off this warn-
ing. .require_canonical_reg_names turns it back on.
got
This modifier is used to load the offset of the GOT entry corresponding to the
symbol.
got_lo16
This modifier is used to load the sign-extended low 16 bits of the offset of the
GOT entry corresponding to the symbol.
got_hi16
This modifier is used to load the sign-extended high 16 bits of the offset of the
GOT entry corresponding to the symbol.
318 Using as
got_ha16
This modifier is like got_hi16, but it adds one if got_lo16 of the input value
is negative.
plt
This modifier is used for function symbols. It causes a procedure linkage table,
an array of code stubs, to be created at the time the shared object is created
or linked against, together with a global offset table entry. The value is a pc-
relative offset to the corresponding stub code in the procedure linkage table.
This arrangement causes the run-time symbol resolver to be called to look up
and set the value of the symbol the first time the function is called (at latest;
depending environment variables). It is only safe to leave the symbol unresolved
this way if all references are function calls.
tls_gd
This modifier is used to load the offset of the GOT entry of the symbol’s TLS
descriptor, to be used for general-dynamic TLS accesses.
tls_gd_lo16
This modifier is used to load the sign-extended low 16 bits of the offset of the
GOT entry of the symbol’s TLS descriptor, to be used for general dynamic TLS
accesses.
tls_gd_hi16
This modifier is used to load the sign-extended high 16 bits of the offset of the
GOT entry of the symbol’s TLS descriptor, to be used for general dynamic TLS
accesses.
tls_gd_ha16
This modifier is like tls_gd_hi16, but it adds one to the value if tls_gd_lo16
of the input value is negative.
tls_ie
This modifier is used to load the offset of the GOT entry containing the offset
of the symbol’s address from the TCB, to be used for initial-exec TLS accesses.
tls_ie_lo16
This modifier is used to load the low 16 bits of the offset of the GOT entry
containing the offset of the symbol’s address from the TCB, to be used for
initial-exec TLS accesses.
tls_ie_hi16
This modifier is used to load the high 16 bits of the offset of the GOT entry
containing the offset of the symbol’s address from the TCB, to be used for
initial-exec TLS accesses.
tls_ie_ha16
This modifier is like tls_ie_hi16, but it adds one to the value if tls_ie_lo16
of the input value is negative.
tls_le
Chapter 9: Machine Dependent Features 319
This modifier is used to load the offset of the symbol’s address from the TCB,
to be used for local-exec TLS accesses.
tls_le_lo16
This modifier is used to load the low 16 bits of the offset of the symbol’s address
from the TCB, to be used for local-exec TLS accesses.
tls_le_hi16
This modifier is used to load the high 16 bits of the offset of the symbol’s
address from the TCB, to be used for local-exec TLS accesses.
tls_le_ha16
This modifier is like tls_le_hi16, but it adds one to the value if tls_le_lo16
of the input value is negative.
tls_gd_call
This modifier is used to tag an instruction as the “call” part of a calling sequence
for a TLS GD reference of its operand.
tls_gd_add
This modifier is used to tag an instruction as the “add” part of a calling sequence
for a TLS GD reference of its operand.
tls_ie_load
This modifier is used to tag an instruction as the “load” part of a calling
sequence for a TLS IE reference of its operand.
-wsigned_overflow
Causes warnings to be produced when signed immediate values overflow the
space available for then within their opcodes. By default this option is disabled
as it is possible to receive spurious warnings due to using exact bit patterns as
immediate constants.
-wunsigned_overflow
Causes warnings to be produced when unsigned immediate values overflow the
space available for then within their opcodes. By default this option is disabled
as it is possible to receive spurious warnings due to using exact bit patterns as
immediate constants.
-mv850 Specifies that the assembled code should be marked as being targeted at the
V850 processor. This allows the linker to detect attempts to link such code
with code assembled for other processors.
-mv850e Specifies that the assembled code should be marked as being targeted at the
V850E processor. This allows the linker to detect attempts to link such code
with code assembled for other processors.
-mv850e1 Specifies that the assembled code should be marked as being targeted at the
V850E1 processor. This allows the linker to detect attempts to link such code
with code assembled for other processors.
-mv850any
Specifies that the assembled code should be marked as being targeted at the
V850 processor but support instructions that are specific to the extended vari-
ants of the process. This allows the production of binaries that contain target
specific code, but which are also intended to be used in a generic fashion. For
example libgcc.a contains generic routines used by the code produced by GCC
for all versions of the v850 architecture, together with support routines only
used by the V850E architecture.
-mv850e2 Specifies that the assembled code should be marked as being targeted at the
V850E2 processor. This allows the linker to detect attempts to link such code
with code assembled for other processors.
-mv850e2v3
Specifies that the assembled code should be marked as being targeted at the
V850E2V3 processor. This allows the linker to detect attempts to link such
code with code assembled for other processors.
-mv850e2v4
This is an alias for ‘-mv850e3v5’.
-mv850e3v5
Specifies that the assembled code should be marked as being targeted at the
V850E3V5 processor. This allows the linker to detect attempts to link such
code with code assembled for other processors.
-mrelax Enables relaxation. This allows the .longcall and .longjump pseudo ops to be
used in the assembler source code. These ops label sections of code which are
Chapter 9: Machine Dependent Features 321
either a long function call or a long branch. The assembler will then flag these
sections of code and the linker will attempt to relax them.
-mgcc-abi
Marks the generated object file as supporting the old GCC ABI.
-mrh850-abi
Marks the generated object file as supporting the RH850 ABI. This is the
default.
-m8byte-align
Marks the generated object file as supporting a maximum 64-bits of alignment
for variables defined in the source code.
-m4byte-align
Marks the generated object file as supporting a maximum 32-bits of alignment
for variables defined in the source code. This is the default.
-msoft-float
Marks the generated object file as not using any floating point instructions -
and hence can be linked with other V850 binaries that do or do not use floating
point. This is the default for binaries for architectures earlier than the e2v3.
-mhard-float
Marks the generated object file as one that uses floating point instructions -
and hence can only be linked with other V850 binaries that use the same kind
of floating point instructions, or with binaries that do not use floating point at
all. This is the default for binaries the e2v3 and later architectures.
9.49.2 Syntax
9.49.2.1 Special Characters
‘#’ is the line comment character. If a ‘#’ appears as the first character of a line, the whole
line is treated as a comment, but in this case the line can also be a logical line number
directive (see Section 3.3 [Comments], page 29) or a preprocessor control command (see
Section 3.1 [Preprocessing], page 29).
Two dashes (‘--’) can also be used to start a line comment.
The ‘;’ character can be used to separate statements on the same line.
general register 3
r3, sp
general register 4
r4, gp
general register 5
r5, tp
general register 6
r6
general register 7
r7
general register 8
r8
general register 9
r9
general register 10
r10
general register 11
r11
general register 12
r12
general register 13
r13
general register 14
r14
general register 15
r15
general register 16
r16
general register 17
r17
general register 18
r18
general register 19
r19
general register 20
r20
general register 21
r21
Chapter 9: Machine Dependent Features 323
general register 22
r22
general register 23
r23
general register 24
r24
general register 25
r25
general register 26
r26
general register 27
r27
general register 28
r28
general register 29
r29
general register 30
r30, ep
general register 31
r31, lp
system register 0
eipc
system register 1
eipsw
system register 2
fepc
system register 3
fepsw
system register 4
ecr
system register 5
psw
system register 16
ctpc
system register 17
ctpsw
system register 18
dbpc
324 Using as
system register 19
dbpsw
system register 20
ctbp
9.49.5 Opcodes
as implements all the standard V850 opcodes.
as also implements the following pseudo ops:
Chapter 9: Machine Dependent Features 325
hi0() Computes the higher 16 bits of the given expression and stores it into the
immediate operand field of the given instruction. For example:
‘mulhi hi0(here - there), r5, r6’
computes the difference between the address of labels ’here’ and ’there’, takes
the upper 16 bits of this difference, shifts it down 16 bits and then multiplies
it by the lower 16 bits in register 5, putting the result into register 6.
lo() Computes the lower 16 bits of the given expression and stores it into the im-
mediate operand field of the given instruction. For example:
‘addi lo(here - there), r5, r6’
computes the difference between the address of labels ’here’ and ’there’, takes
the lower 16 bits of this difference and adds it to register 5, putting the result
into register 6.
hi() Computes the higher 16 bits of the given expression and then adds the value
of the most significant bit of the lower 16 bits of the expression and stores the
result into the immediate operand field of the given instruction. For example
the following code can be used to compute the address of the label ’here’ and
store it into register 6:
‘movhi hi(here), r0, r6’ ‘movea lo(here), r6, r6’
The reason for this special behaviour is that movea performs a sign exten-
sion on its immediate operand. So for example if the address of ’here’ was
0xFFFFFFFF then without the special behaviour of the hi() pseudo-op the
movhi instruction would put 0xFFFF0000 into r6, then the movea instruc-
tion would takes its immediate operand, 0xFFFF, sign extend it to 32 bits,
0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF which is wrong
(the fifth nibble is E). With the hi() pseudo op adding in the top bit of the
lo() pseudo op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 =
0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - the right
value.
hilo() Computes the 32 bit value of the given expression and stores it into the imme-
diate operand field of the given instruction (which must be a mov instruction).
For example:
‘mov hilo(here), r6’
computes the absolute address of label ’here’ and puts the result into register
6.
sdaoff() Computes the offset of the named variable from the start of the Small Data
Area (whose address is held in register 4, the GP register) and stores the result
as a 16 bit signed value in the immediate operand field of the given instruction.
For example:
‘ld.w sdaoff(_a_variable)[gp],r6’
loads the contents of the location pointed to by the label ’ a variable’ into
register 6, provided that the label is located somewhere within +/- 32K of the
address held in the GP register. [Note the linker assumes that the GP register
contains a fixed address set to the address of the label called ’ gp’. This can
326 Using as
-D (Debug)
-S (Symbol Table)
-T (Token Trace)
These are obsolete options used to debug old assemblers.
-d (Displacement size for JUMPs)
This option expects a number following the ‘-d’. Like options that expect file-
names, the number may immediately follow the ‘-d’ (old standard) or constitute
the whole of the command line argument that follows ‘-d’ (gnu standard).
-V (Virtualize Interpass Temporary File)
Some other assemblers use a temporary file. This option commanded them to
keep the information in active memory rather than in a disk file. as always
does this, so this option is redundant.
-J (JUMPify Longer Branches)
Many 32-bit computers permit a variety of branch instructions to do the same
job. Some of these instructions are short (and fast) but have a limited range;
others are long (and slow) but can branch anywhere in virtual memory. Often
there are 3 flavors of branch: short, medium and long. Some other assemblers
would emit short and medium branches, unless told by this option to emit short
and long branches.
-t (Temporary File Directory)
Some other assemblers may use a temporary file, and this option takes a filename
being the directory to site the temporary file. Since as does not use a temporary
disk file, this option makes no difference. ‘-t’ needs exactly one filename.
The Vax version of the assembler accepts additional options when compiled for VMS:
‘-h n ’ External symbol or section (used for global variables) names are not case sensi-
tive on VAX/VMS and always mapped to upper case. This is contrary to the C
language definition which explicitly distinguishes upper and lower case. To im-
plement a standard conforming C compiler, names must be changed (mapped)
to preserve the case information. The default mapping is to convert all lower
case characters to uppercase and adding an underscore followed by a 6 digit
hex value, representing a 24 digit binary value. The one digits in the binary
value represent which characters are uppercase in the original symbol name.
The ‘-h n ’ option determines how we map names. This takes several values.
No ‘-h’ switch at all allows case hacking as described above. A value of zero
(‘-h0’) implies names should be upper case, and inhibits the case hack. A value
of 2 (‘-h2’) implies names should be all lower case, with no case hack. A value
of 3 (‘-h3’) implies that case should be preserved. The value 1 is unused. The
-H option directs as to display every mapped symbol during assembly.
328 Using as
Symbols whose names include a dollar sign ‘$’ are exceptions to the general
name mapping. These symbols are normally only used to reference VMS library
names. Such symbols are always mapped to upper case.
‘-+’ The ‘-+’ option causes as to truncate any symbol name larger than 31 char-
acters. The ‘-+’ option also prevents some code following the ‘_main’ symbol
normally added to make the object file compatible with Vax-11 "C".
‘-1’ This option is ignored for backward compatibility with as version 1.x.
‘-H’ The ‘-H’ option causes as to print every symbol which was changed by case
mapping.
brb bar ;
foo: brw destination ;
bar:
(long displacement)
OPCODE ..., foo ;
brb bar ;
foo: jmp destination ;
bar:
aobleq
aoblss
sobgeq
sobgtr
(byte displacement)
OPCODE ...
(word displacement)
OPCODE ..., foo ;
brb bar ;
foo: brw destination ;
bar:
(long displacement)
OPCODE ..., foo ;
brb bar ;
foo: jmp destination ;
bar:
9.51.2 Syntax
9.51.2.1 Special Characters
Line comments are introduced either by the ‘!’ character or by the ‘;’ character appearing
anywhere on a line.
A hash character (‘#’) as the first character on a line also marks the start of a line
comment, but in this case it could also be a logical line number directive (see Section 3.3
[Comments], page 29) or a preprocessor control command (see Section 3.1 [Preprocessing],
page 29).
The Visium assembler does not currently support a line separator character.
9.51.3 Opcodes
All the standard opcodes of the architecture are implemented, along with the following
three pseudo-instructions: cmp, cmpc, move.
In addition, the following two illegal opcodes are implemented and used by the simula-
tion:
stop 5-bit immediate, SourceA
trace 5-bit immediate, SourceA
Chapter 9: Machine Dependent Features 333
9.52.2 Syntax
The assembler syntax directly encodes sequences of opcodes as defined in the WebAssembly
binary encoding specification at https://github.com/webassembly/spec/BinaryEncoding.md.
Structured sexp-style expressions are not supported as input.
9.52.2.2 Relocations
Special relocations are available by using the ‘@plt ’, ‘@got ’, or ‘@got ’ suffixes
after a constant expression, which correspond to the R ASMJS LEB128 PLT,
R ASMJS LEB128 GOT, and R ASMJS LEB128 GOT CODE relocations, respectively.
The ‘@plt ’ suffix is followed by a symbol name in braces; the symbol value is used to
determine the function signature for which a PLT stub is generated. Currently, the symbol
name is parsed from its last ‘F’ character to determine the argument count of the function,
which is also necessary for generating a PLT stub.
9.52.2.3 Signatures
Function signatures are specified with the signature pseudo-opcode, followed by a simple
function signature imitating a C++-mangled function type: F followed by an optional v,
then a sequence of i, l, f, and d characters to mark i32, i64, f32, and f64 parameters,
respectively; followed by a final E to mark the end of the function signature.
but a linker script to do so may be preferrable, as it doesn’t require running the entire
module through the assembler at once.
Chapter 9: Machine Dependent Features 335
9.53.2 Syntax
In XGATE RISC syntax, the instruction name comes first and it may be followed by up
to three operands. Operands are separated by commas (‘,’). as will complain if too many
operands are specified for a given instruction. The same will happen if you specified too
few operands.
nop
ldl #23
CMP R1, R2
The presence of a ‘;’ character or a ‘!’ character anywhere on a line indicates the start
of a comment that extends to the end of that line.
A ‘*’ or a ‘#’ character at the start of a line also introduces a line comment, but these
characters do not work elsewhere on the line. If the first character of the line is a ‘#’
then as well as starting a comment, the line could also be logical line number directive
(see Section 3.3 [Comments], page 29) or a preprocessor control command (see Section 3.1
[Preprocessing], page 29).
The XGATE assembler does not currently support a line separator character.
The following addressing modes are understood for XGATE:
Inherent ‘’
Immediate 3 Bit Wide
‘#number ’
Immediate 4 Bit Wide
‘#number ’
336 Using as
9.53.5 Opcodes
page 342. This option should be used when call targets can potentially be out
of range. It may degrade both code size and performance, but the linker can
generally optimize away the unnecessary overhead when a call ends up within
range. The default is ‘--no-longcalls’.
--transform | --no-transform
Enable or disable all assembler transformations of Xtensa instructions,
including both relaxation and optimization. The default is ‘--transform’;
‘--no-transform’ should only be used in the rare cases when the instructions
must be exactly as specified in the assembly source. Using ‘--no-transform’
causes out of range instruction operands to be errors.
--rename-section oldname =newname
Rename the oldname section to newname. This option can be used multiple
times to rename multiple sections.
--trampolines | --no-trampolines
Enable or disable transformation of jump instructions to allow jumps across a
greater range of addresses. See Section 9.55.4.3 [Jump Trampolines], page 343.
This option should be used when jump targets can potentially be out of range.
In the absence of such jumps this option does not affect code size or perfor-
mance. The default is ‘--trampolines’.
need only be specified in rare cases where there is more than one applicable format and
where it matters which of those formats is used. A FLIX instruction can also be specified
on a single line by separating the opcodes with semicolons:
{ [format ;] opcode0 [operands ]; opcode1 [operands ]; opcode2 [operands ]; ... }
If an opcode can only be encoded in a FLIX instruction but is not specified as part of
a FLIX bundle, the assembler will choose the smallest format where the opcode can be
encoded and will fill unused instruction slots with no-ops.
When possible, the assembler automatically translates instructions from the core Xtensa
instruction set into equivalent instructions from the Xtensa code density option. This trans-
lation can be disabled by using underscore prefixes (see Section 9.55.2.1 [Opcode Names],
page 340), by using the ‘--no-transform’ command-line option (see Section 9.55.1 [Com-
mand Line Options], page 338), or by using the no-transform directive (see Section 9.55.5.3
[transform], page 346).
It is a good idea not to use the density instructions directly. The assembler will au-
tomatically select dense instructions where possible. If you later need to use an Xtensa
processor without the code density option, the same assembly code will then work without
modification.
The Xtensa assembler offers branch relaxation and also extends this concept to function
calls, MOVI instructions and other instructions with immediate fields.
be enabled using the ‘--longcalls’ command-line option or the longcalls directive (see
Section 9.55.5.2 [longcalls], page 345).
or to:
j .L0_TR_1
...
retw
...
mov a10, a2
j .L0_TR_0
.L0_TR_1:
j 1f
.L0_TR_0:
call8 func
...
1:
...
The Xtensa assembler uses trampolines with jump around only when it cannot find
suitable unreachable trampoline. There may be multiple trampolines between the jump
instruction and its target.
344 Using as
This relaxation does not apply to jumps to undefined symbols, assuming they will reach
their targets once resolved.
Jump relaxation is enabled by default because it does not affect code size or perfor-
mance while the code itself is small. This relaxation may be disabled completely with
‘--no-trampolines’ or ‘--no-transform’ command-line options (see Section 9.55.1 [Com-
mand Line Options], page 338).
9.55.5 Directives
The Xtensa assembler supports a region-based directive syntax:
.begin directive [options ]
...
.end directive
All the Xtensa-specific directives that apply to a region of code use this syntax.
The directive applies to code between the .begin and the .end. The state of the option
after the .end reverts to what it was before the .begin. A nested .begin/.end region can
further change the state of the directive without having to be aware of its outer state. For
example, consider:
.begin no-transform
L: add a0, a1, a2
.begin transform
M: add a0, a1, a2
.end transform
N: add a0, a1, a2
.end no-transform
The ADD opcodes at L and N in the outer no-transform region both result in ADD machine
instructions, but the assembler selects an ADD.N instruction for the ADD at M in the inner
transform region.
The advantage of this style is that it works well inside macros which can preserve the
context of their callers.
The following directives are available:
9.55.5.1 schedule
The schedule directive is recognized only for compatibility with Tensilica’s assembler.
.begin [no-]schedule
.end [no-]schedule
9.55.5.2 longcalls
The longcalls directive enables or disables function call relaxation. See Section 9.55.4.2
[Function Call Relaxation], page 342.
.begin [no-]longcalls
.end [no-]longcalls
9.55.5.3 transform
This directive enables or disables all assembler transformation, including relaxation (see
Section 9.55.4 [Xtensa Relaxation], page 341) and optimization (see Section 9.55.3 [Xtensa
Optimizations], page 340).
.begin [no-]transform
.end [no-]transform
Transformations are enabled by default unless the ‘--no-transform’ option is used. The
transform directive overrides the default determined by the command-line options. An
underscore opcode prefix, disabling transformation of that opcode, always takes precedence
over both directives and command-line flags.
9.55.5.4 literal
The .literal directive is used to define literal pool data, i.e., read-only 32-bit data accessed
via L32R instructions.
.literal label , value [, value ...]
This directive is similar to the standard .word directive, except that the actual location
of the literal data is determined by the assembler and linker, not by the position of the
.literal directive. Using this directive gives the assembler freedom to locate the literal
data in the most appropriate place and possibly to combine identical literals. For example,
the code:
entry sp, 40
.literal .L1, sym
l32r a4, .L1
can be used to load a pointer to the symbol sym into register a4. The value of sym will
not be placed between the ENTRY and L32R instructions; instead, the assembler puts the
data in a literal pool.
Literal pools are placed by default in separate literal sections; however, when using
the ‘--text-section-literals’ option (see Section 9.55.1 [Command Line Options],
page 338), the literal pools for PC-relative mode L32R instructions are placed in the
current section.1 These text section literal pools are created automatically before ENTRY
instructions and manually after ‘.literal_position’ directives (see Section 9.55.5.5
[literal position], page 347). If there are no preceding ENTRY instructions, explicit
.literal_position directives must be used to place the text section literal pools;
otherwise, as will report an error.
When literals are placed in separate sections, the literal section names are derived from
the names of the sections where the literals are defined. The base literal section names are
.literal for PC-relative mode L32R instructions and .lit4 for absolute mode L32R in-
structions (see Section 9.55.5.7 [absolute-literals], page 348). These base names are used for
literals defined in the default .text section. For literals defined in other sections or within
the scope of a literal_prefix directive (see Section 9.55.5.6 [literal prefix], page 347), the
following rules determine the literal section name:
1. If the current section is a member of a section group, the literal section name includes
the group name as a suffix to the base .literal or .lit4 name, with a period to
1
Literals for the .init and .fini sections are always placed in separate sections, even when ‘--text-
section-literals’ is enabled.
Chapter 9: Machine Dependent Features 347
separate the base name and group name. The literal section is also made a member of
the group.
2. If the current section name (or literal_prefix value) begins with
“.gnu.linkonce.kind .”, the literal section name is formed by replacing
“.kind ” with the base .literal or .lit4 name. For example, for literals
defined in a section named .gnu.linkonce.t.func, the literal section will be
.gnu.linkonce.literal.func or .gnu.linkonce.lit4.func.
3. If the current section name (or literal_prefix value) ends with .text, the literal
section name is formed by replacing that suffix with the base .literal or .lit4 name.
For example, for literals defined in a section named .iram0.text, the literal section
will be .iram0.literal or .iram0.lit4.
4. If none of the preceding conditions apply, the literal section name is formed by adding
the base .literal or .lit4 name as a suffix to the current section name (or literal_
prefix value).
For literals defined within the delimited region, the literal section names are derived
from the name argument instead of the name of the current section. The rules used to
derive the literal section names do not change. See Section 9.55.5.4 [literal], page 346. If
the name argument is omitted, the literal sections revert to the defaults. This directive has
no effect when using the ‘--text-section-literals’ option (see Section 9.55.1 [Command
Line Options], page 338).
9.55.5.7 absolute-literals
The absolute-literals and no-absolute-literals directives control the absolute vs.
PC-relative mode for L32R instructions. These are relevant only for Xtensa configurations
that include the absolute addressing option for L32R instructions.
.begin [no-]absolute-literals
.end [no-]absolute-literals
These directives do not change the L32R mode—they only cause the assembler to emit
the appropriate kind of relocation for L32R instructions and to place the literal values in
the appropriate section. To change the L32R mode, the program must write the LITBASE
special register. It is the programmer’s responsibility to keep track of the mode and indicate
to the assembler which mode is used in each region of code.
If the Xtensa configuration includes the absolute L32R addressing option, the default is
to assume absolute L32R addressing unless the ‘--no-absolute-literals’ command-line
option is specified. Otherwise, the default is to assume PC-relative L32R addressing. The
absolute-literals directive can then be used to override the default determined by the
command-line options.
Chapter 9: Machine Dependent Features 349
9.56.2 Syntax
The assembler syntax closely follows the ’Z80 family CPU User Manual’ by Zilog. In
expressions a single ‘=’ may be used as “is equal to” comparison operator.
Suffices can be used to indicate the radix of integer constants; ‘H’ or ‘h’ for hexadecimal,
‘D’ or ‘d’ for decimal, ‘Q’, ‘O’, ‘q’ or ‘o’ for octal, and ‘B’ for binary.
The suffix ‘b’ denotes a backreference to local label.
9.56.5 Opcodes
In line with common practice, Z80 mnemonics are used for both the Z80 and the R800.
In many instructions it is possible to use one of the half index registers
(‘ixl’,‘ixh’,‘iyl’,‘iyh’) in stead of an 8-bit general purpose register. This yields
instructions that are documented on the R800 and undocumented on the Z80. Similarly
in f,(c) is documented on the R800 and undocumented on the Z80.
The assembler also supports the following undocumented Z80-instructions, that have not
been adopted in the R800 instruction set:
out (c),0 Sends zero to the port pointed to by register c.
sli m Equivalent to m = (m <<1)+1, the operand m can be any operand that is valid
for ‘sla’. One can use ‘sll’ as a synonym for ‘sli’.
op (ix+d ), r
This is equivalent to
ld r , (ix+d )
opc r
ld (ix+d ), r
The operation ‘opc ’ may be any of ‘res b ,’, ‘set b ,’, ‘rl’, ‘rlc’, ‘rr’, ‘rrc’,
‘sla’, ‘sli’, ‘sra’ and ‘srl’, and the register ‘r ’ may be any of ‘a’, ‘b’, ‘c’, ‘d’,
‘e’, ‘h’ and ‘l’.
opc (iy+d ), r
As above, but with ‘iy’ instead of ‘ix’.
The web site at http://www.z80.info is a good starting place to find more information
on programming the Z80.
352 Using as
9.57.1 Options
‘-z8001’ Generate segmented code by default.
9.57.2 Syntax
9.57.2.1 Special Characters
‘!’ is the line comment character.
If a ‘#’ appears as the first character of a line then the whole line is treated as a comment,
but in this case the line could also be a logical line number directive (see Section 3.3
[Comments], page 29) or a preprocessor control command (see Section 3.1 [Preprocessing],
page 29).
You can use ‘;’ instead of a newline to separate statements.
word registers
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
rln
rhn
rn
rrn
rqn Register direct: 8bit, 16bit, 32bit, and 64bit registers.
@rn
@rrn Indirect register: @rrn in segmented mode, @rn in unsegmented mode.
addr Direct: the 16 bit or 24 bit address (depending on whether the assembler is in
segmented or unsegmented mode) of the operand is in the instruction.
address(rn )
Indexed: the 16 or 24 bit address is added to the 16 bit register to produce the
final address in memory of the operand.
rn (#imm )
rrn (#imm )
Base Address: the 16 or 24 bit register is added to the 16 bit sign extended
immediate displacement to produce the final address in memory of the operand.
rn (rm )
rrn (rm ) Base Index: the 16 or 24 bit register rn or rrn is added to the sign extended 16
bit index register rm to produce the final address in memory of the operand.
#xx Immediate data xx.
9.57.4 Opcodes
For detailed information on the Z8000 machine instruction set, see Z8000 Technical Manual.
Chapter 10: Reporting Bugs 355
10 Reporting Bugs
Your bug reports play an essential role in making as reliable.
Reporting a bug may help you by bringing a solution to your problem, or it may not.
But in any case the principal function of a bug report is to help the entire community
by making the next version of as work better. Bug reports are your contribution to the
maintenance of as.
In order for a bug report to serve its purpose, you must include the information that
enables us to fix the bug.
enable us to investigate. You might as well expedite matters by sending them to begin
with.
To enable us to fix the bug, you should include all these things:
• The version of as. as announces it if you start it with the ‘--version’ argument.
Without this, we will not know whether there is any point in looking for the bug in the
current version of as.
• Any patches you may have applied to the as source.
• The type of machine you are using, and the operating system name and version number.
• What compiler (and its version) was used to compile as—e.g. “gcc-2.7”.
• The command arguments you gave the assembler to assemble your example and observe
the bug. To guarantee you will not omit something important, list them all. A copy
of the Makefile (or the output from make) is sufficient.
If we were to try to guess the arguments, we would probably guess wrong and then we
might not encounter the bug.
• A complete input file that will reproduce the bug. If the bug is observed when the
assembler is invoked via a compiler, send the assembler source, not the high level
language source. Most compilers will produce the assembler source when run with the
‘-S’ option. If you are using gcc, use the options ‘-v --save-temps’; this will save the
assembler source in a file with an extension of ‘.s’, and also show you exactly how as
is being run.
• A description of what behavior you observe that you believe is incorrect. For example,
“It gets a fatal signal.”
Of course, if the bug is that as gets a fatal signal, then we will certainly notice it. But
if the bug is incorrect output, we might not notice unless it is glaringly wrong. You
might as well not give us a chance to make a mistake.
Even if the problem you experience is a fatal signal, you should still say so explicitly.
Suppose something strange is going on, such as, your copy of as is out of sync, or you
have encountered a bug in the C library on your system. (This has happened!) Your
copy might crash and ours would not. If you told us to expect a crash, then when ours
fails to crash, we would know that the bug was not happening for us. If you had not
told us to expect a crash, then we would not be able to draw any conclusion from our
observations.
• If you wish to suggest changes to the as source, send us context diffs, as generated by
diff with the ‘-u’, ‘-c’, or ‘-p’ option. Always send diffs from the old file to the new
file. If you even discuss something in the as source, refer to it by context, not by line
number.
The line numbers in our development sources will not match those in your sources.
Your line numbers would convey no useful information to us.
Here are some things that are not necessary:
• A description of the envelope of the bug.
Often people who encounter a bug spend a lot of time investigating which changes to
the input file will make the bug go away and which changes will not affect it.
Chapter 10: Reporting Bugs 357
This is often time consuming and not very useful, because the way we will find the
bug is by running a single example under the debugger with breakpoints, not by pure
deduction from a series of examples. We recommend that you save your time for
something else.
Of course, if you can find a simpler example to report instead of the original one, that
is a convenience for us. Errors in the output will be easier to spot, running under the
debugger will take less time, and so on.
However, simplification is not vital; if you do not want to do this, report the bug
anyway and send us the entire test case you used.
• A patch for the bug.
A patch for the bug does help us if it is a good one. But do not omit the necessary
information, such as the test case, on the assumption that a patch is all we need. We
might see problems with your patch and decide to fix the problem another way, or we
might not understand it at all.
Sometimes with a program as complicated as as it is very hard to construct an example
that will make the program follow a certain path through the code. If you do not send
us the example, we will not be able to construct one, so we will not be able to verify
that the bug is fixed.
And if we cannot understand what bug you are trying to fix, or why your patch should
be an improvement, we will not install it. A test case will help us to understand.
• A guess about what the bug is or what it depends on.
Such guesses are usually wrong. Even we cannot guess right about such things without
first using the debugger to find the facts.
Chapter 11: Acknowledgements 359
11 Acknowledgements
If you have contributed to GAS and your name isn’t listed here, it is not meant as a slight.
We just don’t know about it. Send mail to the maintainer, and we’ll correct the situation.
Currently the maintainer is Nick Clifton (email address [email protected]).
Dean Elsner wrote the original gnu assembler for the VAX.1
Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug infor-
mation and the 68k series machines, most of the preprocessing pass, and extensive changes
in ‘messages.c’, ‘input-file.c’, ‘write.c’.
K. Richard Pixley maintained GAS for a while, adding various enhancements and many
bug fixes, including merging support for several processors, breaking GAS up to handle
multiple object file format back ends (including heavy rewrite, testing, an integration of
the coff and b.out back ends), adding configuration including heavy testing and verifica-
tion of cross assemblers and file splits and renaming, converted GAS to strictly ANSI C
including full prototypes, added support for m680[34]0 and cpu32, did considerable work
on i960 including a COFF port (including considerable amounts of reverse engineering),
a SPARC opcode file rewrite, DECstation, rs6000, and hp300hpux host ports, updated
“know” assertions and made them work, much other reorganization, cleanup, and lint.
Ken Raeburn wrote the high-level BFD interface code to replace most of the code in
format-specific I/O modules.
The original VMS support was contributed by David L. Kashtan. Eric Youngdale has
done much work with it since.
The Intel 80386 machine description was written by Eliot Dresselhaus.
Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
The Motorola 88k machine description was contributed by Devon Bowen of Buffalo
University and Torbjorn Granlund of the Swedish Institute of Computer Science.
Keith Knowles at the Open Software Foundation wrote the original MIPS back end
(‘tc-mips.c’, ‘tc-mips.h’), and contributed Rose format support (which hasn’t been
merged in yet). Ralph Campbell worked with the MIPS code to support a.out format.
Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, tc-h8300), and IEEE
695 object file format (obj-ieee), was written by Steve Chamberlain of Cygnus Support.
Steve also modified the COFF back end to use BFD for some low-level operations, for use
with the H8/300 and AMD 29k targets.
John Gilmore built the AMD 29000 support, added .include support, and simplified
the configuration of which versions accept which directives. He updated the 68k machine
description so that Motorola’s opcodes always produced fixed-size instructions (e.g., jsr),
while synthetic instructions remained shrinkable (jbsr). John fixed many bugs, including
true tested cross-compilation support, and one bug in relaxation that took a week and
required the proverbial one-bit fix.
Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the 68k,
completed support for some COFF targets (68k, i386 SVR3, and SCO Unix), added support
for MIPS ECOFF and ELF targets, wrote the initial RS/6000 and PowerPC assembler, and
made a few other minor patches.
1
Any more details?
360 Using as
under this License. If a section does not fit the above definition of Secondary then it is
not allowed to be designated as Invariant. The Document may contain zero Invariant
Sections. If the Document does not identify any Invariant Sections then there are none.
The “Cover Texts” are certain short passages of text that are listed, as Front-Cover
Texts or Back-Cover Texts, in the notice that says that the Document is released under
this License. A Front-Cover Text may be at most 5 words, and a Back-Cover Text may
be at most 25 words.
A “Transparent” copy of the Document means a machine-readable copy, represented
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The “Title Page” means, for a printed book, the title page itself, plus such following
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A section “Entitled XYZ” means a named subunit of the Document whose title either
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the Title” of such a section when you modify the Document means that it remains a
section “Entitled XYZ” according to this definition.
The Document may include Warranty Disclaimers next to the notice which states that
this License applies to the Document. These Warranty Disclaimers are considered to
be included by reference in this License, but only as regards disclaiming warranties:
any other implication that these Warranty Disclaimers may have is void and has no
effect on the meaning of this License.
2. VERBATIM COPYING
Appendix A: GNU Free Documentation License 363
You may copy and distribute the Document in any medium, either commercially or
noncommercially, provided that this License, the copyright notices, and the license
notice saying this License applies to the Document are reproduced in all copies, and
that you add no other conditions whatsoever to those of this License. You may not use
technical measures to obstruct or control the reading or further copying of the copies
you make or distribute. However, you may accept compensation in exchange for copies.
If you distribute a large enough number of copies you must also follow the conditions
in section 3.
You may also lend copies, under the same conditions stated above, and you may publicly
display copies.
3. COPYING IN QUANTITY
If you publish printed copies (or copies in media that commonly have printed covers) of
the Document, numbering more than 100, and the Document’s license notice requires
Cover Texts, you must enclose the copies in covers that carry, clearly and legibly, all
these Cover Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on
the back cover. Both covers must also clearly and legibly identify you as the publisher
of these copies. The front cover must present the full title with all words of the title
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Copying with changes limited to the covers, as long as they preserve the title of the
Document and satisfy these conditions, can be treated as verbatim copying in other
respects.
If the required texts for either cover are too voluminous to fit legibly, you should put
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rest onto adjacent pages.
If you publish or distribute Opaque copies of the Document numbering more than 100,
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protocols a complete Transparent copy of the Document, free of added material. If
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remain thus accessible at the stated location until at least one year after the last time
you distribute an Opaque copy (directly or through your agents or retailers) of that
edition to the public.
It is requested, but not required, that you contact the authors of the Document well
before redistributing any large number of copies, to give them a chance to provide you
with an updated version of the Document.
4. MODIFICATIONS
You may copy and distribute a Modified Version of the Document under the conditions
of sections 2 and 3 above, provided that you release the Modified Version under precisely
this License, with the Modified Version filling the role of the Document, thus licensing
distribution and modification of the Modified Version to whoever possesses a copy of
it. In addition, you must do these things in the Modified Version:
A. Use in the Title Page (and on the covers, if any) a title distinct from that of the
Document, and from those of previous versions (which should, if there were any,
364 Using as
be listed in the History section of the Document). You may use the same title as
a previous version if the original publisher of that version gives permission.
B. List on the Title Page, as authors, one or more persons or entities responsible for
authorship of the modifications in the Modified Version, together with at least five
of the principal authors of the Document (all of its principal authors, if it has fewer
than five), unless they release you from this requirement.
C. State on the Title page the name of the publisher of the Modified Version, as the
publisher.
D. Preserve all the copyright notices of the Document.
E. Add an appropriate copyright notice for your modifications adjacent to the other
copyright notices.
F. Include, immediately after the copyright notices, a license notice giving the public
permission to use the Modified Version under the terms of this License, in the form
shown in the Addendum below.
G. Preserve in that license notice the full lists of Invariant Sections and required Cover
Texts given in the Document’s license notice.
H. Include an unaltered copy of this License.
I. Preserve the section Entitled “History”, Preserve its Title, and add to it an item
stating at least the title, year, new authors, and publisher of the Modified Version
as given on the Title Page. If there is no section Entitled “History” in the Docu-
ment, create one stating the title, year, authors, and publisher of the Document
as given on its Title Page, then add an item describing the Modified Version as
stated in the previous sentence.
J. Preserve the network location, if any, given in the Document for public access to
a Transparent copy of the Document, and likewise the network locations given in
the Document for previous versions it was based on. These may be placed in the
“History” section. You may omit a network location for a work that was published
at least four years before the Document itself, or if the original publisher of the
version it refers to gives permission.
K. For any section Entitled “Acknowledgements” or “Dedications”, Preserve the Title
of the section, and preserve in the section all the substance and tone of each of the
contributor acknowledgements and/or dedications given therein.
L. Preserve all the Invariant Sections of the Document, unaltered in their text and
in their titles. Section numbers or the equivalent are not considered part of the
section titles.
M. Delete any section Entitled “Endorsements”. Such a section may not be included
in the Modified Version.
N. Do not retitle any existing section to be Entitled “Endorsements” or to conflict in
title with any Invariant Section.
O. Preserve any Warranty Disclaimers.
If the Modified Version includes new front-matter sections or appendices that qualify
as Secondary Sections and contain no material copied from the Document, you may at
your option designate some or all of these sections as invariant. To do this, add their
Appendix A: GNU Free Documentation License 365
titles to the list of Invariant Sections in the Modified Version’s license notice. These
titles must be distinct from any other section titles.
You may add a section Entitled “Endorsements”, provided it contains nothing but
endorsements of your Modified Version by various parties—for example, statements of
peer review or that the text has been approved by an organization as the authoritative
definition of a standard.
You may add a passage of up to five words as a Front-Cover Text, and a passage of up
to 25 words as a Back-Cover Text, to the end of the list of Cover Texts in the Modified
Version. Only one passage of Front-Cover Text and one of Back-Cover Text may be
added by (or through arrangements made by) any one entity. If the Document already
includes a cover text for the same cover, previously added by you or by arrangement
made by the same entity you are acting on behalf of, you may not add another; but
you may replace the old one, on explicit permission from the previous publisher that
added the old one.
The author(s) and publisher(s) of the Document do not by this License give permission
to use their names for publicity for or to assert or imply endorsement of any Modified
Version.
5. COMBINING DOCUMENTS
You may combine the Document with other documents released under this License,
under the terms defined in section 4 above for modified versions, provided that you
include in the combination all of the Invariant Sections of all of the original documents,
unmodified, and list them all as Invariant Sections of your combined work in its license
notice, and that you preserve all their Warranty Disclaimers.
The combined work need only contain one copy of this License, and multiple identical
Invariant Sections may be replaced with a single copy. If there are multiple Invariant
Sections with the same name but different contents, make the title of each such section
unique by adding at the end of it, in parentheses, the name of the original author or
publisher of that section if known, or else a unique number. Make the same adjustment
to the section titles in the list of Invariant Sections in the license notice of the combined
work.
In the combination, you must combine any sections Entitled “History” in the vari-
ous original documents, forming one section Entitled “History”; likewise combine any
sections Entitled “Acknowledgements”, and any sections Entitled “Dedications”. You
must delete all sections Entitled “Endorsements.”
6. COLLECTIONS OF DOCUMENTS
You may make a collection consisting of the Document and other documents released
under this License, and replace the individual copies of this License in the various
documents with a single copy that is included in the collection, provided that you
follow the rules of this License for verbatim copying of each of the documents in all
other respects.
You may extract a single document from such a collection, and distribute it individu-
ally under this License, provided you insert a copy of this License into the extracted
document, and follow this License in all other respects regarding verbatim copying of
that document.
366 Using as
AS Index
--listing-lhs-width . . . . . . . . . . . . . . . . . . . . . . . . . 25 -a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
--listing-lhs-width2 . . . . . . . . . . . . . . . . . . . . . . . . 25 -A options, i960 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
--listing-rhs-width . . . . . . . . . . . . . . . . . . . . . . . . . 25 -ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
--little . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 -ad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
--longcalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 -ag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
‘--march=architecture ’ command line option, -ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CRIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 -al . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
--MD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 -Aleon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
‘--mul-bug-abort’ command line option, CRIS -an . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 -as . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
--no-absolute-literals . . . . . . . . . . . . . . . . . . . . . 338 -Asparc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
--no-auto-litpools . . . . . . . . . . . . . . . . . . . . . . . . . 338 -Asparcfmaf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
‘--no-expand’ command line option, MMIX. . . 226 -Asparcima . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
--no-longcalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 -Asparclet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
‘--no-merge-gregs’ command line option, MMIX -Asparclite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 -Asparcvis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
‘--no-mul-bug-abort’ command line option, CRIS -Asparcvis2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 -Asparcvis3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
--no-pad-sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 -Asparcvis3r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
‘--no-predefined-syms’ command line option, -Av6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
MMIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 -Av7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
‘--no-pushj-stubs’ command line option, MMIX -Av8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 -Av9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
‘--no-stubs’ command line option, MMIX . . . . 226 -Av9a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
--no-target-align . . . . . . . . . . . . . . . . . . . . . . . . . . 338 -Av9b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
--no-text-section-literals . . . . . . . . . . . . . . . . 338 -Av9c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
--no-trampolines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 -Av9d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
--no-transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 -Av9e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
‘--no-underscore’ command line option, CRIS -Av9m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 -Av9v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
--no-warn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 -b option, i960 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
‘--pcrel’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 -big option, M32R . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
‘--pic’ command line option, CRIS . . . . . . . . . . . 137 -D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
‘--print-insn-syntax’ . . . . . . . . . . . . . . . . . . 204, 335 -D, ignored on VAX . . . . . . . . . . . . . . . . . . . . . . . . . . 327
‘--print-opcodes’ . . . . . . . . . . . . . . . . . . . . . . . 204, 335 -d, VAX option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
‘--register-prefix-optional’ option, M680x0 -eabi= command line option, ARM . . . . . . . . . . . 112
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 ‘-EB’ command line option, AArch64 . . . . . . . . . . . 90
--relax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 -EB command line option, ARC . . . . . . . . . . . . . . . 103
‘--relax’ command line option, MMIX . . . . . . . 226 -EB command line option, ARM . . . . . . . . . . . . . . 112
--rename-section. . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 -EB option (MIPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
--renesas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 -EB option, M32R . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
--sectname-subst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ‘-EB’ option, TILE-Gx . . . . . . . . . . . . . . . . . . . . . . . . 311
‘--short-branches’ . . . . . . . . . . . . . . . . . . . . . . . . . . 203 ‘-EL’ command line option, AArch64 . . . . . . . . . . . 90
--small . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 -EL command line option, ARC . . . . . . . . . . . . . . . 103
--statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 -EL command line option, ARM . . . . . . . . . . . . . . 113
‘--strict-direct-mode’ . . . . . . . . . . . . . . . . . . . . . . 203 -EL option (MIPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
--target-align . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 -EL option, M32R . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
--text-section-literals . . . . . . . . . . . . . . . . . . . 338 ‘-EL’ option, TILE-Gx . . . . . . . . . . . . . . . . . . . . . . . . 311
--traditional-format . . . . . . . . . . . . . . . . . . . . . . . . 28 -f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
--trampolines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 -F command line option, Alpha . . . . . . . . . . . . . . . . 95
--transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 ‘-fno-pic’ option, RISC-V . . . . . . . . . . . . . . . . . . . 259
‘--underscore’ command line option, CRIS . . . 137 ‘-fpic’ option, RISC-V . . . . . . . . . . . . . . . . . . . . . . . 259
--warn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 -g command line option, Alpha . . . . . . . . . . . . . . . . 95
‘--x32’ option, i386. . . . . . . . . . . . . . . . . . . . . . . . . . . 162 -G command line option, Alpha . . . . . . . . . . . . . . . . 95
‘--x32’ option, x86-64 . . . . . . . . . . . . . . . . . . . . . . . . 162 -G option (MIPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
‘--xgate-ramoffset’ . . . . . . . . . . . . . . . . . . . . . . . . . 203 ‘-h’ option, VAX/VMS . . . . . . . . . . . . . . . . . . . . . . . 327
‘-1’ option, VAX/VMS . . . . . . . . . . . . . . . . . . . . . . . 328 ‘-H’ option, VAX/VMS . . . . . . . . . . . . . . . . . . . . . . . 328
-32addr command line option, Alpha . . . . . . . . . . 95 -I path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AS Index 371
att syntax pseudo op, i386 . . . . . . . . . . . . . . . . . . . . 165 Build Configuration Registers Version, ARC . . 104
att syntax pseudo op, x86-64 . . . . . . . . . . . . . . . . . 165 Built-in symbols, CRIS . . . . . . . . . . . . . . . . . . . . . . . 138
attributes, symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 builtin math functions, TIC54X . . . . . . . . . . . . . . 299
auxiliary attributes, COFF symbols . . . . . . . . . . . . 44 builtin subsym functions, TIC54X . . . . . . . . . . . . 306
auxiliary symbol information, COFF . . . . . . . . . . . 56 bundle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
AVR line comment character . . . . . . . . . . . . . . . . . 126 bundle-locked. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
AVR line separator . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 bundle_align_mode directive . . . . . . . . . . . . . . . . . . 51
AVR modifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 bundle_lock directive . . . . . . . . . . . . . . . . . . . . . . . . . 51
AVR opcode summary . . . . . . . . . . . . . . . . . . . . . . . . 127 bundle_unlock directive . . . . . . . . . . . . . . . . . . . . . . . 51
AVR options (none) . . . . . . . . . . . . . . . . . . . . . . . . . . 124 bus lock prefixes, i386 . . . . . . . . . . . . . . . . . . . . . . . . 169
AVR register names . . . . . . . . . . . . . . . . . . . . . . . . . . 126 bval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
AVR support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 byte directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
byte directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . . 301
B
backslash (\\) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 C
backspace (\b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 C preprocessor macro separator, ARC . . . . . . . . 103
balign directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 c_mode directive, TIC54X. . . . . . . . . . . . . . . . . . . . . 302
balignl directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ‘C54XDSP_DIR’ environment variable, TIC54X
balignw directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
bes directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . . . 304 call directive, Nios II . . . . . . . . . . . . . . . . . . . . . . . . 244
big endian output, MIPS . . . . . . . . . . . . . . . . . . . . . . 14 call instructions, i386 . . . . . . . . . . . . . . . . . . . . . . . . . 167
big endian output, PJ . . . . . . . . . . . . . . . . . . . . . . . . . 12 call instructions, relaxation . . . . . . . . . . . . . . . . . . . 342
big-endian output, MIPS . . . . . . . . . . . . . . . . . . . . . 211 call instructions, x86-64 . . . . . . . . . . . . . . . . . . . . . . 167
big-endian output, TIC6X . . . . . . . . . . . . . . . . . . . . 308 call_hiadj directive, Nios II . . . . . . . . . . . . . . . . . 244
bignums . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 call_lo directive, Nios II . . . . . . . . . . . . . . . . . . . . . 244
binary constants, TIC54X . . . . . . . . . . . . . . . . . . . . 298 callj, i960 pseudo-opcode . . . . . . . . . . . . . . . . . . . . 180
binary files, including . . . . . . . . . . . . . . . . . . . . . . . . . . 61 carriage return (backslash-r) . . . . . . . . . . . . . . . . . 31
binary integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 case sensitivity, Z80 . . . . . . . . . . . . . . . . . . . . . . . . . . 350
bit names, IA-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 cfi_endproc directive . . . . . . . . . . . . . . . . . . . . . . . . . 52
bitfields, not supported on VAX . . . . . . . . . . . . . . 330 cfi_fde_data directive . . . . . . . . . . . . . . . . . . . . . . . . 53
Blackfin directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 cfi_personality directive . . . . . . . . . . . . . . . . . . . . . 52
Blackfin options (none) . . . . . . . . . . . . . . . . . . . . . . . 131 cfi_personality_id directive . . . . . . . . . . . . . . . . . 53
Blackfin support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 cfi_sections directive . . . . . . . . . . . . . . . . . . . . . . . . 52
Blackfin syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 cfi_startproc directive . . . . . . . . . . . . . . . . . . . . . . . 52
block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 char directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . . 301
BMI, i386 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 character constant, Z80 . . . . . . . . . . . . . . . . . . . . . . . 350
BMI, x86-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 character constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
branch improvement, M680x0 . . . . . . . . . . . . . . . . . 201 character escape codes . . . . . . . . . . . . . . . . . . . . . . . . . 31
branch improvement, M68HC11 . . . . . . . . . . . . . . 207 character escapes, Z80 . . . . . . . . . . . . . . . . . . . . . . . . 349
branch improvement, VAX. . . . . . . . . . . . . . . . . . . . 328 character, single . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
branch instructions, relaxation . . . . . . . . . . . . . . . . 342 characters used in symbols . . . . . . . . . . . . . . . . . . . . . 30
branch recording, i960 . . . . . . . . . . . . . . . . . . . . . . . . 178 clink directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . 302
branch statistics table, i960 . . . . . . . . . . . . . . . . . . . 178 code16 directive, i386. . . . . . . . . . . . . . . . . . . . . . . . . 172
Branch Target Address, ARC . . . . . . . . . . . . . . . . . 104 code16gcc directive, i386 . . . . . . . . . . . . . . . . . . . . . 172
branch target alignment . . . . . . . . . . . . . . . . . . . . . . 341 code32 directive, i386. . . . . . . . . . . . . . . . . . . . . . . . . 172
break directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . 303 code64 directive, i386. . . . . . . . . . . . . . . . . . . . . . . . . 172
BSD syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 code64 directive, x86-64 . . . . . . . . . . . . . . . . . . . . . . 172
bss directive, i960 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 COFF auxiliary symbol information . . . . . . . . . . . 56
bss directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . . . 301 COFF structure debugging . . . . . . . . . . . . . . . . . . . . 79
bss section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 38 COFF symbol attributes . . . . . . . . . . . . . . . . . . . . . . . 44
BTA saved on exception entry, ARC . . . . . . . . . . 104 COFF symbol descriptor. . . . . . . . . . . . . . . . . . . . . . . 56
bug criteria. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 COFF symbol storage class . . . . . . . . . . . . . . . . . . . . 72
bug reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 COFF symbol type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
bugs in assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 COFF symbols, debugging . . . . . . . . . . . . . . . . . . . . . 56
Build configuration for: BTA Registers, ARC . . 105 COFF value attribute . . . . . . . . . . . . . . . . . . . . . . . . . 81
Build configuration for: Core Registers, ARC . . 105 COMDAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Build configuration for: Interrupts, ARC . . . . . . 105 comm directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
378 Using as
T type of a symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
tab (\t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
tab directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . . . 305
tag directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
U
tag directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . . . 305 ualong directive, SH . . . . . . . . . . . . . . . . . . . . . . . . . . 283
TBM, i386 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 uaquad directive, SH . . . . . . . . . . . . . . . . . . . . . . . . . . 283
TBM, x86-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 uaword directive, SH . . . . . . . . . . . . . . . . . . . . . . . . . . 283
tdaoff pseudo-op, V850 . . . . . . . . . . . . . . . . . . . . . . 326 ubyte directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . 301
temporary symbol names . . . . . . . . . . . . . . . . . . . . . . 42 uchar directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . 301
text and data sections, joining . . . . . . . . . . . . . . . . . 27 uhalf directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . 303
text directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 uint directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . . 303
text section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 uleb128 directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
tfloat directive, i386. . . . . . . . . . . . . . . . . . . . . . . . . 171 ulong directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . 303
tfloat directive, x86-64 . . . . . . . . . . . . . . . . . . . . . . 171 undefined section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Thumb support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 union directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . 305
TIC54X builtin math functions . . . . . . . . . . . . . . . 299 unsegm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
TIC54X line comment character . . . . . . . . . . . . . . 307 usect directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . 305
TIC54X line separator . . . . . . . . . . . . . . . . . . . . . . . . 307 ushort directive, TIC54X. . . . . . . . . . . . . . . . . . . . . 303
TIC54X machine directives . . . . . . . . . . . . . . . . . . . 301 uword directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . 303
TIC54X memory-mapped registers . . . . . . . . . . . . 307
TIC54X options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
TIC54X subsym builtins . . . . . . . . . . . . . . . . . . . . . . 306 V
TIC54X support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 V850 command line options . . . . . . . . . . . . . . . . . . 319
TIC54X-specific macros . . . . . . . . . . . . . . . . . . . . . . 306 V850 floating point (ieee) . . . . . . . . . . . . . . . . . . . . 324
TIC6X big-endian output . . . . . . . . . . . . . . . . . . . . . 308 V850 line comment character . . . . . . . . . . . . . . . . . 321
TIC6X line comment character . . . . . . . . . . . . . . . 308 V850 line separator . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
TIC6X line separator . . . . . . . . . . . . . . . . . . . . . . . . . 308 V850 machine directives . . . . . . . . . . . . . . . . . . . . . . 324
TIC6X little-endian output . . . . . . . . . . . . . . . . . . . 308 V850 opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
TIC6X machine directives . . . . . . . . . . . . . . . . . . . . 309 V850 options (none) . . . . . . . . . . . . . . . . . . . . . . . . . . 319
TIC6X options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 V850 register names . . . . . . . . . . . . . . . . . . . . . . . . . . 321
TIC6X support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 V850 support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
TILE-Gx machine directives . . . . . . . . . . . . . . . . . . 314 val directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
TILE-Gx modifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 value attribute, COFF . . . . . . . . . . . . . . . . . . . . . . . . . 81
TILE-Gx opcode names . . . . . . . . . . . . . . . . . . . . . . 311 value of a symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TILE-Gx register names . . . . . . . . . . . . . . . . . . . . . . 311 var directive, TIC54X . . . . . . . . . . . . . . . . . . . . . . . . 306
TILE-Gx support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 VAX bitfields not supported . . . . . . . . . . . . . . . . . . 330
TILE-Gx syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 VAX branch improvement . . . . . . . . . . . . . . . . . . . . 328
TILEPro machine directives . . . . . . . . . . . . . . . . . . 319 VAX command-line options ignored . . . . . . . . . . . 327
TILEPro modifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 VAX displacement sizing character . . . . . . . . . . . . 330
TILEPro opcode names . . . . . . . . . . . . . . . . . . . . . . 316 VAX floating point . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
TILEPro register names . . . . . . . . . . . . . . . . . . . . . . 316 VAX immediate character . . . . . . . . . . . . . . . . . . . . 330
TILEPro support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 VAX indirect character . . . . . . . . . . . . . . . . . . . . . . . 330
TILEPro syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 VAX line comment character . . . . . . . . . . . . . . . . . 331
time, total for assembly . . . . . . . . . . . . . . . . . . . . . . . . 27 VAX line separator . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
title directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 VAX machine directives . . . . . . . . . . . . . . . . . . . . . . 328
tls_gd directive, Nios II . . . . . . . . . . . . . . . . . . . . . . 244 VAX opcode mnemonics . . . . . . . . . . . . . . . . . . . . . . 328
tls_ie directive, Nios II . . . . . . . . . . . . . . . . . . . . . . 244 VAX operand notation . . . . . . . . . . . . . . . . . . . . . . . 330
tls_ldm directive, Nios II . . . . . . . . . . . . . . . . . . . . . 244 VAX register names . . . . . . . . . . . . . . . . . . . . . . . . . . 330
tls_ldo directive, Nios II . . . . . . . . . . . . . . . . . . . . . 244 VAX support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
tls_le directive, Nios II . . . . . . . . . . . . . . . . . . . . . . 244 Vax-11 C compatibility . . . . . . . . . . . . . . . . . . . . . . . 327
TMS320C6X support . . . . . . . . . . . . . . . . . . . . . . . . . 308 VAX/VMS options . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
tp register, V850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 version directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
transform directive . . . . . . . . . . . . . . . . . . . . . . . . . . 346 version directive, TIC54X . . . . . . . . . . . . . . . . . . . 306
trusted compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 version of assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
turning preprocessing on and off . . . . . . . . . . . . . . . 29 versions of symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
two-byte integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Virtualization instruction generation override
type directive (COFF version) . . . . . . . . . . . . . . . . . 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
type directive (ELF version) . . . . . . . . . . . . . . . . . . . 80 visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60, 62, 70
392 Using as