Introduction to the UVM
SystemVerilog Primer for VHDL Engineers
Ray Salemi
Senior Verification Consultant
[email protected] | www.verificationacademy.com
Ray Salemi — Senior Verification Consultant
Introduction to Introduction to
Advanced Verification the UVM
© 2014 Mentor Graphics Corporation, all rights reserved.
Agenda
1. SystemVerilog for VHDL Engineers
2. Object Oriented Programming
3. SystemVerilog Interfaces
4. Packages, Includes, and Macros
5. UVM Test Objects
6. UVM Environments
7. Connecting Objects
8. Transaction Level Testing
9. The Analysis Layer
10. UVM Reporting
11. Functional Coverage with Covergroups
12. Introduction to Sequences
© 2014 Mentor Graphics Corporation, all rights reserved.
Why SystemVerilog?
RTL
• MultiThreaded Verilog VHDL
• Hardware Data Types
• Netlisting
© 2014 Mentor Graphics Corporation, all rights reserved.
Why SystemVerilog?
Test Benches
• Object Oriented
• Functional Coverage SystemVerilog
• Randomization
• Methodology Libraries
RTL
• MultiThreaded Verilog VHDL
• Hardware Data Types
• Netlisting
© 2014 Mentor Graphics Corporation, all rights reserved.
Difference in Philosophy
VHDL: Contract SystemVerilog: Letter of Intent
• All terms defined • Assumes common language
• Many Sections • Paragraphs Not Sections
• Long, Avoids Ambiguity • Short, Quickly Written
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Adder
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VHDL Adder
Libraries define types
Interface separate from
implementation
All Signal Widths Defined
Width issues explicitly
handled
Widths must match
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Verilog Adder
No Library Definitions. Logic
behavior built into language
Interface and behavior defined
together (no separate entity)
No need for internal signals.
Concatenation implements width
SystemVerilog assumes the engineer
knows how the simulator Width changes handled by
will interpret code simulator.
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SystemVerilog iS CaSe SenSiTive!
Clk != CLK != clk
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Multi-Threaded Behavior
initial
process
= always
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MultiThreaded Behavior
process initial
begin begin
...
wait;
= ...
...
end end
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MultiThreaded Behavior
process always
begin begin
...
...
= ...
...
end end
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Delays
wait until expr;
= wait (expr);
wait for 100ns;
= #100ns;
wait on signal;
= @signal;
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Waiting on an Edge
Unique to SystemVerilog
• @(posedge sig)
• @(negedge sig)
process (clk) begin always @(posedge clk)
if rising_edge(clk) then begin
q <= d;
end if;
end process;
= q <= d;
end
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SystemVerilog Data Values
• 4-state values built into language (no libraries)
• 1
• 0
• X
• Z
Conflict Resolution Table
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Constants are not Strings
<width>’<radix><numerals>
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Four State Types and Two State Types
Four State Types Two State Types
• logic • int (32-bits)
• reg (same as logic) • shortint (16-bits)
• integer (32-bit) • longint(64-bits)
• time (64-bit) • byte (8-bits)
• bit (1 bit)
• Unsigned by default • Signed by Default
SystemVerilog converts between types
automatically
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Declaring Registers and Memories
signal halfbyte std_logic_vector(3 downto 0);
type reversebits_mem_type is array (7 downto 0) of
std_logic_vector(1 to 8);
signal reversebits_mem : reversebits_mem_type;
logic [3:0] halfbyte;
logic [1:8] reversbits_mem[7:0];
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Assigning Different Widths
1 1 0 0 1 0 1 0 <= 1 0 1 0 1 1 0 0 1 0 1 0
Truncation
1 1 1 1 1 1 0 0 1 0 1 0 <= 1 1 0 0 1 0 1 0
Signed Extension
0 0 0 0 1 1 0 0 1 0 1 0 <= 1 1 0 0 1 0 1 0
Unsigned Extension
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Concurrent Assignment
signal <= equation;
VHDL Concurrent Assignment
assign signal = equation;
Verilog Concurrent Assignment
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Concurrent Assignment Example
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Blocking and Non-Blocking
• variable = blocking
• signal = non-blocking
• := operator for variables and blocking
• <= operator for signals and non-blocking
• Types are independent of blocking/non-blocking
• = operator for blocking assignments
• <= operator for non-blocking assignments
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Blocking/Non-Blocking Example
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VHDL Instantiation : Multiple Steps
Example: Instantiating a DUT and Tester
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Verilog Instantiation : One Step
Example: Instantiating a DUT and Tester
SystemVerilog Instantiation
Shortcuts:
Assuming the signals at the top
level have the same names as the
ports in the instantiated module:
• .<portname> matches the top
level signal to the port of the same
name.
• .* matches all top level signals to
ports of the same name.
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Testbench Example
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Next Session
1. SystemVerilog for VHDL Engineers
2. Object Oriented Programming
3. SystemVerilog Interfaces
4. Packages, Includes, and Macros
5. UVM Test Objects
6. UVM Environments
7. Connecting Objects
8. Transaction Level Testing
9. The Analysis Layer
10. UVM Reporting
11. Functional Coverage with Covergroups
12. Introduction to Sequences
© 2014 Mentor Graphics Corporation, all rights reserved.
Introduction to the UVM
SystemVerilog Primer for VHDL Engineers
Ray Salemi
Senior Verification Consultant
[email protected] | www.verificationacademy.com
