JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 19, NO.

9, SEPTEMBER 2001 1307

A Compact 3R-Receiver Module for Short-Haul SDH

STM-16 Systems
Francesco Centurelli, Member, IEEE, Massimo Magliocco, Andrea Pallotta, Pasquale Tommasino, and
Alessandro Trifiletti

Abstract—This paper describes a complete 3R optical re- Gigabit optical transmission systems have to be compact,
ceiver module for synchronous digital hierarchy (SDH) STM-16 cost-effective, and reliable: for short-haul applications (LANs
short-haul systems, housed in a 20-pin dual-in-line (DIL) ceramic and optical access networks), the nonoptical chips and the
package. The module includes an InGaAs p-i-n photodiode, a
commercial GaAs transimpedance amplifier, and a custom-made integration of the optical network unit (ONU) dominate the
silicon bipolar frequency- and phase-locked loop (FPLL)-based costs. An important research topic is then the development of
clock and data recovery (CDR) circuit. The fiber pigtail is actively highly integrated electronic circuits for the receiver and the
aligned to the photodiode by using a proprietary technology that transmitter sides of the link. A key element to achieve this goal
uses a silicon-based optical submount assembly (OSA). The use is low power consumption, which allows the use of low-cost
of a clock recovery circuit based on an FPLL allows avoiding an
external low-frequency reference clock and achieving a root-mean plastic packages for the integrated circuits (ICs) and the design
square (rms) jitter of 0.075 UI. The module requires two supply of dense printed circuit boards (PCBs) or multichip modules
voltages of 5 V and 4.5 V, for a total power dissipation of 930 for the transmitter or receiver system. Moreover, low power
mW, and has a total volume below 0.75 cm3 (24 7 99 3 consumption makes easier the design of compact multichannel
mm3 ). Measurements have shown full compatibility with SDH circuits for WDM systems.
standards.
Even more important to achieve practical ONUs is the devel-
Index Terms—Clock recovery, hybrid module, optical receiver, opment of low-cost and small-sized hybrid modules, integrating
synchronous digital hierarchy (SDH), SONET, synchronous op- the optical and the electrical parts of the receiver in a single
tical network.
package. Moreover, the integrated module concept is widely be-
lieved to be very attractive for a system design engineer. Its most
I. INTRODUCTION important benefit is that modular product speeds up the design
time allowing the usually limited engineering resources to con-
T HE LAST decade has seen an increasing diffusion of high
bit-rate optical communication systems for telecom and
datacom applications, due to the expansion of computer net-
centrate on the complexities of the overall electrical system de-
sign, and it is also generally accepted that a more integrated
works and the development of new multimedia services, that solution simplifies the manufacturing process, reduces instal-
require a large data transmission capacity. Optical fibers have lation and setup times, and leads to a virtually 100% yield for
become the preferred media for long-distance digital communi- the very critical optical and high-speed electrical parts. In recent
cation systems, since they offer very wide bandwidth, low prop- years, a certain number of hybrid modules for transmitters [1],
agation losses, and immunity from crosstalk. Furthermore, local [2] and receivers [3]–[6] for 2.5-Gb/s optical communications
application of optical communications is rapidly increasing, and have been presented in the literature. Takahashi et al. [3] pre-
fiber-based local-area networks (LANs) are expected to play an sented in 1998 a receiver module that meets the specifications
important role in realizing the future multimedia society. of synchronous digital hierarchy (SDH)/SONET standard; the
This situation has spurred the industrial interest toward high module includes a photodiode [p-i-n or avalanche photodiode
bit rates (10 Gb/s and beyond) and wavelength division multi- (APD)], a GaAs transimpedance amplifier, 4 Si ICs and a sur-
plexing (WDM) solutions, to better exploit the large transmis- face acoustic wave (SAW) filter, it uses a 5-V supply voltage for
sion capacity of optical fibers. On the other hand, price-compet- a power dissipation of 1.5 W. Hirose et al. [4] have presented a
itive solutions are required for systems operating at present bit module that use less electrical ICs and a lower supply voltage,
rates (up to 2.5 Gb/s), to comply with commercial demand for for a total power consumption of about 640 mW, and it achieves
low-cost optical systems for short-haul applications. 5 ps of generated jitter. The module presented by Soda et al. [5],
[6] is based on a single 3.3-V silicon IC, and shows about 6 ps
of jitter and a power dissipation of 450 mW.
Manuscript received June 27, 2000; revised May 7, 2001. In this paper, we present a complete 3R SDH STM-16
F. Centurelli, P. Tommasino, and A. Trifiletti are with the Dipartimento di short-haul receiver, including a p-i-n photodiode, a GaAs
Ingegneria Elettronica, Università di Roma “La Sapienza,” 00184 Roma, Italy transimpedance amplifier, and a custom-made Si-bipolar fully
(e-mail: [email protected]; [email protected]; tri-
[email protected]). integrated frequency- and phase-locked loop (FPLL)-based
M. Magliocco and A. Pallotta were with Italtel, Laboratori Ricerca e clock and data recovery circuit. The receiver is housed in a
Sviluppo, Castelletto di Settimo Milanese, Italy. They are now with ST 20-pin dual-in-line (DIL) ceramic package, and presents a fiber
Microelectronics, Cornaredo, Italy (e-mail: [email protected];
[email protected]). pigtail actively aligned to the photodiode. In Section II, we
Publisher Item Identifier S 0733-8724(01)07761-1. describe the receiver module structure and Section III presents
0733–8724/01$10.00 © 2001 IEEE
1308 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 19, NO. 9, SEPTEMBER 2001

Fig. 1. Block scheme of an optical 3R receiver.

Fig. 3. Photograph of the OSA with the photodiode.

Fig. 2. Block diagram of the module.

the custom-made clock and data recovery circuit. The results

of measurements on the receiver module are presented in
Section IV, where the full compatibility with SDH standard is
highlighted. Fig. 4. Structure of the optical interface.

II. RECEIVER MODULE DESCRIPTION

Fig. 1 shows a typical block scheme of an optical 3R (re- whole receiver. Thin-film technology on ceramic substrate
shaping, regenerating, retiming) receiver; a photodiode (p-i-n has been used to lay out the three chips inside the module.
or APD) converts the optical input signal to a current signal, Matched 50- microstrip lines have been used on the alumina
that is then converted to a voltage signal by a transimpedance to ensure the integrity of high-frequency signals, exploiting
preamplifier (TZA). This is followed by a postamplifier [either a fully differential architecture for the whole system. All of
a limiting amplifier or an automatic gain control (AGC)] to yield the off-chip capacitors required by the receiver have been
to the following stages a signal with known amplitude, indepen- mounted inside the module using surface-mount device (SMD)
dent of the input optical power. The amplifier chain is followed components, with the exception of the loop filter of the PLL.
by the clock and data recovery (CDR) circuit, that extracts from To reduce module size and manufacturing costs, the module
the data flow a clock signal at the bit frequency [clock recovery uses silicon as a base to support the fiber and the photodiode,
circuit (CRC)] and uses it to synchronize a decision circuit, so exploiting it as an aid for optical alignment. The optical inter-
regenerating the input data. face is made by a small Si-based optical submount assembly
The hybrid module we present in this paper [7] includes all (OSA) ( mm), shown in Fig. 3, and an active
these functions, so it implements the whole high-frequency alignment technique is used to maximize the coupling with the
part of a receiver for optical communications. Fig. 2 shows photodiode. Fig. 4 presents a sketch of the interface mounting:
the module block diagram, sketched within the ceramic 20-pin the fiber is placed in an etched V-groove and actively aligned to
DIL package. The package includes a p-i-n photodiode, a com- a back-illuminated p-i-n chip [9]. Once coupling efficiency has
mercial GaAs transimpedance amplifier, and a custom-made been maximized, the fiber is fixed in place using thermally cured
silicon bipolar fully integrated FPLL-based CDR circuit [8]; epoxy. The alignment operation takes about 1 min. The coupling
two supply rails of 5 V (for TZA, CDR, and photodiode between the optical fiber and the p-i-n is obtained by means of
biasing) and 4.5 V (for the CDR) are required. The fiber a mirror integrated at the end of the V-groove. Just attaching
pigtail is actively aligned to the p-i-n, mounted on a silicon the bottom-illuminated p-i-n on the predefined gold-plated pads
bench, by a proprietary optical assembly technology, so only leads to a self-alignment of the chip to the mirror. The mirror
one optical and two electrical dice are needed to compose the is realized by means of a special wet etching process able to
CENTURELLI et al.: A COMPACT 3R-RECEIVER MODULE FOR SHORT-HAUL SDH STM-16 SYSTEMS 1309

nonreturn-to-zero (NRZ) input data stream shows a null at

the bit frequency (2.5 GHz), so a nonlinear block is needed
to generate a spectral component at such frequency: a differ-
entiator and full-wave rectifier (DFWR) is used [10], which
obtains a pulse in correspondence to each positive- or nega-
tive-going transition of the input signal. The PLL is then used
as a tunable filter to select the spectral line at the bit fre-
quency. This choice provides a very stable reference signal,
Fig. 5. Block scheme of the clock and data recovery IC.
with a low level of output jitter, when compared with imple-
mentations based on the use of passive filters (SAW), whose
maximum quality factor is limited by detuning specifications.
make a 54 -angled plane surface in the silica layers. This sur- In PLL-based clock recovery systems, the tunability of the
face is then gold-plated to achieve good reflectivity. The mea- PLL allows to keep the filter quality factor independent from
sured coupling efficiency is better than 95%. We have used an tuning, and the stability of the output clock signal is mainly
InGaAs p-i-n photodiode whose effective active area presents a related to the phase noise of the voltage-controlled oscillator
diameter of 75 m. (VCO). A very low noise oscillator is then needed to achieve
The photodiode is directly connected by a 1-mm bonding low jitter values. The PLL bandwidth has to be designed
wire to the GaAs transimpedance amplifier, which presents dif- according to SDH specifications on jitter transfer (2 MHz),
ferential-type output with a gain of about 1 k on a 1.9-GHz so, in order to increase the capture range of the clock re-
bandwidth, when loaded by 50- resistors. The input-referred covery circuit and to compensate for the uncertainty in the
rms noise current of the transimpedance amplifier is about free-running frequency of the VCO, a frequency acquisition
340 nA and dominates the receiver sensitivity: we can assume aid is needed. Therefore, the frequency acquisition process
a p-i-n responsivity 0.9 A/W and an optical transmitter ex- has to be supported by a preliminary frequency setting of
tinction ratio of 10, and so we get from the following equa- the VCO, by adjusting the passive components external to
tion a sensitivity limit of 25 dBm for a bit error rate (BER) of the chip; moreover, the capture range has been increased by
(i.e., SNR ) a frequency acquisition loop (FAL) based on the Richman
quadricorrelator [11], [12]. The quadricorrelator architecture
SNR includes the PLL blocks (phase detector, low-pass filter, and
dBm (1)
VCO) and does not require an external low-frequency clock
signal to lock the VCO frequency to the bit frequency of
Nevertheless, the input electrical sensitivity of the main ampli- the input data stream. For large deviations from the nominal
fier, integrated in the CDR circuit, is about 5 mVpp, so we can bit frequency, the output signal of the PLL presents a zero
expect a total receiver sensitivity of about 20 dBm. average value, and the VCO is driven by the FAL. Once
The CDR chip is a custom-made IC that includes the main frequency lock has been established, and the frequency dif-
amplifier and the clock recovery and data decision functions. A ference detector (FDD) output approaches zero, the phase
clock recovery architecture based on a PLL has been preferred detector (PD) drives the loop filter ensuring phase acquisi-
to the use of a passive filter, to achieve a better jitter performance tion. The Richman architecture has been chosen to achieve
and to allow a higher integration level. Moreover, the use of frequency acquisition since it offers the best tradeoff be-
an FPLL allows to track frequency errors wider than the PLL tween performance and cost-effectiveness, when compared
capture range, so avoiding the use of an external low-frequency with solutions that require an external low frequency (155-
reference clock signal. or 622-MHz) clock signal [13]–[15], often adopted in com-
mercial CDR ICs. Frequency acquisition based on an external
III. CLOCK AND DATA RECOVERY (CDR) IC reference is a fast process, since it is independent from tran-
sition density in the data stream, but the reference frequency
A. Circuit Description is independent from the effective bit frequency to lock. More-
The CDR circuit consists of three main blocks, as shown in over, hundred-of-megahertz-range crystal reference clocks are
Fig. 5: a voltage amplifier with limiting capability, a CRC, and very expensive, and the integration of the FAL with the PLL
a master–slave D-type flip-flop, used as decision circuit. All the requires additional circuitry, such as a lock detector to switch
blocks are dc-coupled to avoid the use of external capacitors. from frequency acquisition to the effective timing recovery.
The gain stage is composed by a linear gain stage (MAIN) fol- Fig. 6 shows a block scheme of the CRC, where the blocks
lowed by a limiting amplifier (DATASQ), to provide to the fol- composing the Richman quadricorrelator can be easily iden-
lowing stages a differential signal with sharp edges and known tified. To reduce the crosstalk between the PLL and the FAL,
amplitude independent of input power. A limiting amplifier has a dead zone for small frequency differences, lower than the
been preferred to an AGC amplifier since it presents a much sim- PLL capture range, has been set in the FDD. VCO reac-
pler circuit topology, and allows to have a lower power dissipa- tive elements and PLL loop filter have been placed off-chip
tion and to pass to the following blocks a reshaped data signal. in order to allow fine trimming of the CDR parameters.
The clock recovery function is based on spectral line re- The overall capture range has been measured to be about
covery, obtained by a nonlinear block, and PLL filtering. The 100 MHz.
1310 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 19, NO. 9, SEPTEMBER 2001

Fig. 6. Block scheme of the clock recovery circuit.

TABLE I
MAIN AMPLIFIER SPECIFICATIONS

Fig. 7. Block scheme of the main amplifier, showing gain stages (GS) and
offset compensation loop.

The circuit has been designed to use two supply voltages of 5

and 4.5 V, and its power dissipation has been kept well below
1 W. The input port is decoupled by external capacitors, and
on-chip matched to 50 to minimize signal reflections, whereas
open collector buffers drive data and clock lines.

Fig. 8. Topology of a gain stage (GS) of the main amplifier.

B. Technological Details
The IC has been designed and fabricated using Maxim
GST-2 semicustom double-poly self-aligned silicon bipolar varying from down to up cases for the process parameters. The
process, which makes available n-p-n and p-n-p transistors, required gain and bandwidth do not allow high loop gains,
diodes, polysilicon, and NiCr resistors, capacitors, and three so that it is not possible to use negative feedback to stabilize
metal layers for interconnections. The small emitter area (0.7 amplifier behavior. Therefore, we have used a compensation
1.6 m ) and the use of isolation trenches in the epitaxial technique based on high-frequency positive feedback, that
layer allow a high integration density and high performance enhances the bandwidth and allows external trimming of the
transistors. The collector-substrate parasitic capacitance results transfer function. The topology chosen for this block, shown
greatly reduced, yielding n-p-n bipolar junction transistors in Fig. 7, consists of two differential gain stages (GS), which
(BJTs) characterized by a maximum transition frequency of ensure the limiting operation, biased by a dc feedback loop
27 GHz and by a breakdown voltage still adequate for 5-V which provides 50- input matching and offset compensation.
applications. Moreover, the availability of lateral p-n-p BJTs Each gain stage uses the topology shown in Fig. 8 [16], where a
has provided high-impedance current sources for high gain capacitively coupled current amplifier (C A) transconductance
phase/frequency comparators (charge pump comparators). stage forms a high-frequency positive feedback loop that ex-
pands the bandwidth without affecting low-frequency behavior.
C. Functional Blocks Description A small-signal model of the circuit topology has been devel-
1) Main Amplifier: The main amplifier (MAIN) has been oped, and its analysis has shown a very low sensitivity of band-
designed to achieve the specifications reported in Table I. The width enhancement to the value of the capacitor in the C A
input ports are decoupled by off-chip capacitors and matched to feedback stage, so the topology is tolerant to process parame-
50 , while the outputs are directly coupled to the next stage. ters variations. The bandwidth can be adjusted by varying the
A differential output test buffer (PROBE) has been included to gain of the positive feedback differential pairs, adjusting their
allow measurements and to optimize the transfer function of the bias currents to tune the best tradeoff between bandwidth en-
amplifier. largement and peaking. The topology in [16] has then been mod-
High-gain simple differential pairs show high sensitivity to ified by making the current externally controlled to compen-
process parameter variations: e.g., the bandwidth of a 40-dB sate process parameter variations. Simulations using nominal
two-stage amplifier can range from 1.35 to over 2.8 GHz, process parameters and an external 50-k resistor have
CENTURELLI et al.: A COMPACT 3R-RECEIVER MODULE FOR SHORT-HAUL SDH STM-16 SYSTEMS 1311

TABLE II
MAIN AMPLIFIER PERFORMANCE UNDER PROCESS PARAMETERS VARIATIONS

by controlling the signal phase shift in the active part of the

loop: this is possible by varying the transconductance of the
secondary cell (Gilbert cell) and so the amount of quadrature
feedback signal [17].
To achieve good phase noise performance, an oscillator
has been preferred to a fully integrated ring oscillator, and a
differential topology has been chosen to minimize the effect of
substrate and supply noise injection. On-chip inductors usually
present a low quality factor , so we have chosen not to inte-
grate the tank, to obtain a higher and achieve a better phase
noise. Moreover, the use of an external tank allows a higher re-
peatability for the circuit, and so a higher yield, and allows to
reduce tunability problems for the VCO. The passive elements
of the tank circuit are placed outside the chip, and this allows to
preset the oscillation frequency of the VCO and to maintain the
Fig. 9. Topology of the VCO. possibility of coarse tunability. In this way, the specifications
for the FAL circuit result relaxed, simplifying its design.
4) Clock and Data Recovery (CDR) Blocks: The CDR
shown a differential gain of 40 dB with 2.3-GHz bandwidth and blocks include the DFWR, the phase detectors, the FDD, and
an input dynamic range of 50 mVpp. Table II reports bandwidth a D-type flip-flop used as decision circuit. Standard high-fre-
and peaking of this amplifier under nominal, up, and down cases quency topologies [10], mostly based on the Gilbert multiplier
for the process parameters, to show the effectiveness of the ex- cell, have been used for such blocks. In the FDD, the bottom
ternal trimming. differential pair of the Gilbert cell has been replaced by a pair
2) Limiting Amplifier: The main amplifier is followed by a of differential stages acting as comparators, one for positive
limiting stage (DATASQ), composed by three cascaded differ- and one for negative input signals, as shown in Fig. 10: the
ential pairs followed by emitter followers used as level shifters. comparators use slightly different reference voltages to obtain a
We have chosen not to use a positive feedback comparator, dead zone of 200 mV centered on zero, so avoiding the effects
which could show a hysteresis loop as a result of process of FDD offsets on the VCO control voltage when the system
parameters variations. The first differential stage amplifies the is in lock.
input signal and drives the second stage far from linear zone, The VCO quadrature output is followed by a squarer stage to
to have a signal with sharp edges and short rise/fall times. The interface with the decision circuit and the output open collector
latter differential stage is designed to work on the edge of the buffer. An exclusive-OR gate has been inserted at the squarer
saturation region and is used to clip the overshoot due to the output, to maintain the possibility of coarse ( 180 ) phase ad-
second stage. Simulations show a differential gain of 38 dB justment between the data and the clock to minimize BER.
with 1.5-GHz bandwidth; the input linear dynamic range is
8 mVpp, that results in rise/fall times of 75 ps.
3) Voltage-Controlled Oscillator (VCO): The VCO exploits D. Circuit Realization
the topology shown in Fig. 9 [10], that yields wide tuning range Fig. 11 shows a microphotograph of the chip, that comprises
and in-phase and quadrature output signals, as required by the about 400 active devices and whose die size is 2 2 mm .
Richman quadricorrelator architecture. The oscillator is com- The integration on the same chip of analog and digital func-
posed of two differential transconductance stages, driven by the tions, the large gain of the linear input section of the circuit,
in-phase and quadrature outputs, loaded by an tank, whose and the presence of a VCO have necessitated the use of separate
values are chosen so as to yield 90 -out-of-phase signals at both ground and supply lines for different parts of the chip, to reduce
ends of the inductors. The oscillation frequency can be changed crosstalk problems. Four sets of supply voltages have then been
1312 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 19, NO. 9, SEPTEMBER 2001

Fig. 12. Photograph of the receiver module.

Fig. 10. Topology of the FDD.

Fig. 13. Waveforms of output clock and data at an optical input of 018 dBm
(200 ps/div and 100 mV/div).

TABLE III
SUMMARY OF THE OPTICAL RECEIVER MODULE PERFORMANCE

Fig. 11. Microphotograph of the CDR IC.

used for the amplifier blocks, the VCO, the FPLL, and the dig-
ital blocks and output buffers. The power consumption of the
circuit is about 780 mW.

IV. MEASUREMENTS
clock signal. The generated jitter has been measured to have an
The hybrid module we have presented in this paper imple- rms value of 0.0075 UI.
ments a full 3R FPLL-based receiver in a 20-pin DIL package, Sending the receiver data and clock outputs to the error de-
with a very limited number of external components. It is very tector, we have obtained the BER curve in Fig. 14, that shows a
compact (24.7 mm 9.9 mm 3 mm, less than 0.75 cm ) and sensitivity of 20 dBm for the whole receiver at room temper-
presents a total power dissipation of 930 mW at room temper- ature for an error probability of 10 .
ature; Fig. 12 is a photograph of the open DIL package, that Adjusting the external loop filter parameters of the CDR,
clearly shows the three dice included in the module. we were able to measure, by an HP 71501 Jitter Analysis
The receiver module has been measured to assess its compat- System, the jitter behavior of the receiver module: Figs. 15 and
ibility with SDH standard for short-haul STM-16 level systems. 16 show, respectively, the measured jitter transfer and jitter
Fig. 13 shows clock and data output signals for a pseudorandom tolerance characteristics, highlighting the compatibility with
binary sequence (PRBS) input with an average optical SDH standard.
power of 18 dBm at 1.55 m, highlighting the good aper- Table III summarizes the measured performance of the
ture of the data eye diagram and the low level of jitter on the module.
CENTURELLI et al.: A COMPACT 3R-RECEIVER MODULE FOR SHORT-HAUL SDH STM-16 SYSTEMS 1313

Fig. 14. BER performance.

Fig. 15. Jitter transfer performance.

V. CONCLUSION viding a direct connection of the optical die to the GaAs TZA
die. An ASIC FPLL-based CDR IC has also been designed and
A space-saving SDH STM-16 optical receiver module for implemented in silicon bipolar technology; the integrated main
short-haul applications, including the clock recovery and data amplifier adjustable bandwidth allows the optimization of the
regenerator functions, has been designed and measured. The 3R-receiver channel filter. The use of clock recovery architec-
module integrates in a 20-pin DIL package the whole high-fre- ture based on FPLL allows a high integration level for the CDR,
quency part of a 3R optical receiver. A silicon bench for the and avoids the need of an external stable reference signal. The
active alignment of the p-i-n to the fiber has been used, pro- module results very compact (totalvolume below 0.75 cm ) and
1314 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 19, NO. 9, SEPTEMBER 2001

Fig. 16. Jitter tolerance performance.

presents a power consumption below 1 W, so it allows to sim- [13] R. Walker, C. Stout, and C.-S. Yen, “A 2.488 Gb/s Si-bipolar clock and
plify the implementation of receiver and repeater nodes in op- data recovery IC with robust loss of signal detection,” in ISSCC Dig.
Tech. Papers, 1997, pp. 246–247.
tical networks. Measurements have shown the full compatibility [14] G. Gutierrez, S. Kong, and B. Coy, “2.488 Gb/s silicon bipolar clock and
of this module with SDH STM-16 standards for short-haul ap- data recovery IC for SONET (OC-48),” in Proc. IEEE CICC, 1998, pp.
plications. 575–578.
[15] J. Hauenschild, D. Friedrich, J. Herrle, and J. Krug, “PIN-preamp
module and CDR-DMUX constituting a receiver for short-haul links
REFERENCES up to 3.5 Gb/s,” IEEE J. Solid-State Circuits, vol. 33, pp. 2247–2251,
Dec. 1998.
[1] F. Ishitsuka, N. Iwasaki, M. Hirose, M. Yanagibashi, H. Ichino, and Y. [16] T. Wakimoto and Y. Akazawa, “A low-power wide-band amplifier using
Ando, “A compact MU interface 2.5 Gb/s optical transmitter module a new parasitic capacitance compensation technique,” IEEE J. Solid-
with an embedded LD-driver IC,” in Proc. ECTC, 1998, pp. 184–191. State Circuits, vol. 25, pp. 200–206, Feb. 1990.
[2] I. Kobayashi, M. Yoshizawa, T. Yoshida, T. Ikeuchi, T. Tajima, and Y. [17] A. Pottbäcker and U. Langmann, “An 8 GHz silicon bipolar clock-re-
Uda, “Compact 2.4 Gbit/s fiber optic transmitter module for 3.3 V+ covery and data-regenerator IC,” IEEE J. Solid-State Circuits, vol. 29,
operation,” in Proc. ECOC, vol. 2, 1999, pp. 238–239. pp. 1572–1576, Dec. 1994.
[3] S. Takahashi, N. Nishiyama, K. Murata, D. Takagi, K. Tanida, and M.
Nishie, “Compact low-power 2.5 Gbit/s SDH/SONET receiver mod-
ules,” in OFC Conf. Dig., 1998, pp. 210–211.
[4] M. Hirose, N. Ishihara, Y. Akazawa, and H. Ichino, “An ultracompact, Francesco Centurelli (S’94–M’95) received the laurea degree (cum laude) and
2-cc-size, 0.64 W 2.5 Gbit/s optical receiver module combined with an the Ph.D. degree in electronic engineering from the University of Roma “La
MU receptacle,” in OFC Conf. Dig., 1998, pp. 160–161. Sapienza,” Roma, Italy, in 1995 and 2000, respectively.
[5] M. Soda, S. Shioiri, T. Morikawa, M. Tachigori, I. Watanabe, He is currently doing postdoctoral work with the Electronic Engineering De-
and M. Shibutani, “A 2.5 Gb/s one-chip receiver module for Gi- parmtne of the University of Roma “La Sapienza.” His research interests in-
gabit-To-The-Home (GTTH) system,” in Proc. IEEE CICC, 1999, pp. clude system-level analysis and design of clock recovery circuits and high-speed
273–276. analog integrated circuits, with particular emphasis on gigabit-rate optical com-
[6] S. Shioiri, M. Soda, A. Goto, N. Kitamura, I. Watanabe, and M. Shibu- munication systems.
tani, “A 2.5 Gb/s high-speed PLC module for Gigabit-To-The-Home
(GTTH) system,” in OFC Conf. Dig., 1999, pp. 188–190.
[7] A. Pallotta, M. Magliocco, A. Trifiletti, F. Centurelli, and P. Tommasino, Massimo Magliocco, photograph and biography not available at the time of
“2.5 Gb/s 20-pin DIL 3R receiver module,” in Proc. ECOC, vol. 1, 1999, publication.
pp. 362–363.
[8] A. Pallotta, F. Centurelli, F. Loriga, and A. Trifiletti, “A monolithic
2.5 Gb/s clock and data recovery circuit based on Silicon bipolar tech-
nology,” in Proc. SyBEN (SPIE no. 3408), 1998, pp. 183–190. Andrea Pallotta received the M.S. degree in electronic engineering from the
[9] M. J. Wale and C. Edge, “Self-aligned flip-chip assembly of photonic University of Ancona, Ancona, Italy.
devices with electrical and optical connections,” IEEE Trans. Comp., From 1991 to 1999, he was with Italtel, Italy, where he joined several Euro-
Hybrids, Manuf. Technol., vol. 13, pp. 780–786, Dec. 1990. pean community research projects in the field of SDH and WDM fiber-optic
[10] R. R. Cordell, J. B. Forney, C. N. Dunn, and W. G. Garrett, “A 50 MHz transmission systems for both transport and access networks. From 1999 to
phase- and frequency-locked loop,” IEEE J. Solid-State Circuits, vol. 2000, he was with Siemens Information and Communication Networks, where
SC-14, pp. 1003–1010, Dec. 1979. he was responsible for the SDH Cross-Connect advanced development group.
[11] D. Richman, “Color-carrier reference phase synchronization accuracy in In September 2000, he joined the STMicroelectronics Company, where he is
NTSC color television,” Proc. IRE, vol. 42, pp. 106–133, Jan. 1954. currently responsible for the electrooptical interface design group. His research
[12] J. A. Bellisio, “A new phase-locked timing recovery method for digital interests include GaAs and silicon high-speed ICs, active optical devices, high-
regenerators,” in IEEE Int. Conf. Communications Rec., vol. 1, 1976, speed TX and RX optical modules, and fiber-optic transmission system engi-
pp. 10.17–10.20. neering.
CENTURELLI et al.: A COMPACT 3R-RECEIVER MODULE FOR SHORT-HAUL SDH STM-16 SYSTEMS 1315

Pasquale Tommasino was born in Formia, Italy, in 1967. He received the Alessandro Trifiletti was born in Roma, Italy, in 1959.
Master’s degree in electronic engineering and the Ph.D. degree from the Uni- In 1991, he joined the Electronic Engineering Department of the University
versity of Roma “La Sapienza,” Roma, Italy, in 1992 and 1999, respectively. of Roma “La Sapienza,” Roma, as a Research Assistant and is currently an As-
Since 1995, he has been with the Electronic Engineering Department of the sistant Professor. His research interests include high-speed circuit design tech-
University of Roma “La Sapienza.” His research interests include the design of niques and III–V device modeling.
integrated circuits for optical communication systems and linear, nonlinear, and
statistical design-oriented modeling of active devices.