FPGA Implementation of Addition Subtraction Module For Double Precision Floating Point Numbers Using Verilog
FPGA Implementation of Addition Subtraction Module For Double Precision Floating Point Numbers Using Verilog
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Authorized licensed use limited to: VIT University. Downloaded on February 23,2022 at 16:01:24 UTC from IEEE Xplore. Restrictions apply.
IEEE International Conference on Advances in Engineering & Technology Research (ICAETR-2014),
August 01-02,2014, Dr. Virendra Swarup Group of Institutions, Unnao, India
speed. This circuit has been implemented in 0.6fl CMOS performance of floating point operators in a library developed
technology. at Sandia National Labs.[8].
The algorithmic approach outperformed LS consistently
with improvement in speed ranging from 12%-56% and
improvements in layout area ranging from 14.5%-35%.The DESIGN DESCRIPTION
resulting LZD circuit has notable performance, which is In this section we will discuss about the hardware that we
essential while it is often a part of the critical path in the have used, block diagram of the proposed system.
floating point unit.[I].Nabeel Shirazi, Walters, and Peter The floating point module performs addition, subtraction.
Athanas (1995) implemented custom 16118 bit three stage Also it implements all four rounding modes-round to nearest
pipelined floating point multiplier that doesn't support even, round to zero, round to positive infinity, round to
rounding modes. By pipelining the each unit the sufficient negative infmity.
number of times in order to maximize speed and to minimize
area. They investigate the ways of implementing the floating
Block Diagram
point operators in the best combination of speed and area in The block diagram and the architectural schematic view of
order to minimize the area requirements small floating point double precision floating point adderlSubtractor is shown in
representation formats are used. Pipeline techniques are figures 2 and 3 respectively. Table 1&2 shows the Rounding
applied to produce a result every clock cycle.[2].Loucas Modes selected for various bit combinations of rmode and
Louca, Cook, and Johnson (1996)explored FPGA Operations selected for various bit combinations of Fp_op.
implementation of addition and multiplication for single Each of the blocks along with its brief description is
precision Floating point numbers that tradeoff the area and explained below:
speed for the accuracy.The design achieved 2.3 MFlops and
doesn't supports rounding modes. And 7 MFlops for addition.
[3].Barry Lee, and Neil Burgess (2002) implemented the
floating point unit using primitives of Xillinx vertex-2 FPGA.
The design achieved the operating frequency of IOOMHz. with
I n p ut
a latency of 4 clock cycles. They focused on using primitives
of a specific FPGA to produce components with low delay and
low area matrices.[4].Pavle Belanovic, and Miriam Leeser
(2002) implemented the reconfigurable floating point unit
using VHDL, which is mapped on to Xillinx
XCVI000FPGA.They developed a library of fully Fig.2: Block Diagram of Double Precision Floating point AdderlSubtractor.
�
implemented in Vertex2p FPGA. The improvement seen in
1lJil(530)
LOP design is the level of logic reduced by 23%with an added
C,a(63
expense of increasing the area by 38%.[6]. Dhiraj Sangwan,
and Mahesh K. Yadav investigated adderlsubtractor and
opb(530) I
IlIb(63:0
multiplication unit for floating point arithmetic using VHDL. eJjJonent)(t�O)
The floating point multiplication operation implemented using
sequential architecture based on booths Radix-4 recording
algorithm. For floating point addition, the sequential addition
aa sub
could have been complex so the combinational architecture
has been implemented.[7]. K. Scott Hemmert, and Keith Fig. 3: Black box view of Double Precision Floatingpoint AdderiSubtractor
multiply achieved the operating frequency of 230 MHz using a 00 Round-nearest -even
10 stage adder pipeline and a 12 stage multiplier pipeline. The 01 Round-to- zero
area requirement is 571 slices for adder. The floating point 10 Round-up
modules are hand-mapped and placed using JHDL as a design 11 Round-down
entry language. This presentation details the size and the
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Authorized licensed use limited to: VIT University. Downloaded on February 23,2022 at 16:01:24 UTC from IEEE Xplore. Restrictions apply.
IEEE International Conference on Advances in Engineering & Technology Research (ICAETR-2014),
August 01-02,2014, Dr. Virendra Swarup Group of Institutions, Unnao, India
Result = X+Y = (Xm x 2Xe) + (Ym x 2Ye)
Table2. Operation selecting mode. involves the following steps:
Bit combination Operation I) Align binary point:
000 Addition • Initial result exponent: the larger of Xe, Ye
Compute exponent difference: Ye - Xe
001 subtraction
•
inexact, and invalid are asserted . 3) If normalization of result is required, then a normalization
step follows:
• Left shift result, decrement result exponent (e.g., if result is
ALGORITHM O.OOl xx . . . ) or
Right shift result, increment result exponent (e.g., if result is
Floating point addition is one of the difficult units in the
•
10.lxx ...)
floating point arithmetic operations. Addition and the related
Continue until MSB of data is 1 (NOTE: Hidden bit in IEEE
operation of subtraction is the most basic arithmetic operation.
Standard)
The hardware implementation of this arithmetic for floating
4) Check result exponent:
point is a complicated operation due to the normalization
If larger than maximum exponent allowed return exponent
requirements.
•
overflow
• If smaller than minimum exponent allowed return exponent
1. Basic floating point Addition algorithm
underflow
5) If result mantissa is 0, may need to set the exponent to zero
Assuming that the operands are already in the IEEE 754
by a special step to return a proper zero.
format, performing floating point addition:
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IEEE International Conference on Advances in Engineering & Technology Research (ICAETR-2014),
August 01-02,2014, Dr. Virendra Swarup Group of Institutions, Unnao, India
respectively. Snapshot is nothing but every moment of the tliJnberof �ce Fip Aops 2274 1536 148%
application while running. It gives the obvious elaborated of
Ibnberof 4 i1JJt l\JTs 2746 1536 178%
application. It will be useful for the new user to comprehend
for the future steps. IlmberofOOlled lOBs 206 124 166%
The double precision floating point adderlSubtractor,
tliJnberof GClKs 1 8 12%
supports the IEEE-754 binary interchange format. The
proposed design is done in Verilog.
Fig. 6: Device utilization summary.
CONCLUSION
The verilog code first simulated with isim and synthesized on
We have presented a Double Precision Floating Point
targeted device XC3s200a-5vq I DO. The adder Subtractor
adderlSubtractor unit Using Verilog. The actual logic design
module occupies an area of 412slices, 834 slices respectively.
of a floating point adder is not too difficult, and most of the
and its operating frequency is 418. I 56Mhz.where as in Xilinx
design time was spent trying to minimize the logic resources
core there are 1266 and operating frequency is 284Mhz. The
used. As a part of our plans, proper rounding will be added in
double precision adderlSubtractor Modules are compliant with
the implementations. The design is in Verilog Hardware
IEEE754 format and handle the various rounding conditions.
description language (HDL), and implemented on FPGA.
The designed arithmetic unit operates on 64-bit operands. It
can be designed for 64-quad double precision. It can be
extended to have more mathematical operations like
trigonometric, exponential and logarithmic functions.
REFERENCES
978-1-4799-6393-5/14/$31.00©2014IEEE
Authorized licensed use limited to: VIT University. Downloaded on February 23,2022 at 16:01:24 UTC from IEEE Xplore. Restrictions apply.
IEEE International Conference on Advances in Engineering & Technology Research (lCAETR-2014),
August 01-02,2014, Dr. Virendra Swarup Group of Institutions, Unnao, India
978-1-4799-6393-5/14/$31.00©2014IEEE
Authorized licensed use limited to: VIT University. Downloaded on February 23,2022 at 16:01:24 UTC from IEEE Xplore. Restrictions apply.