dc_shell> get_nets *my_net*

dc_shell> set enable_keep_signal_dt_net true

dc_shell> set_dont_touch [get_nets *my_net*] true
dc_shell> compile_ultra
Warning: Preserving net 'my_net'. Expect QoR impact. (OPT-154)
dc_shell-topo> get_cells -hier -filter "is_physical_black_box==true"
Warning: Created physical library cell for logical library
%s. (OPT-1413)
dc_shell-topo> create_cell -only_physical MY_U_PO_CELL MY_FILL_CELL
Information: create physical-only cell 'MY_U_PO_CELL'
Warning: The newly created cell does not have location.
Timing will be inaccurate. (DCT-004)
dc_shell-topo> report_cell -only_physical
****************************************
Report : cell
-only_physical
Design : test
Version: D-2010.03-SP3
Date : Mon Jul 12 02:56:25 2010
****************************************
Cell Reference Library Area Orient. Location
-------------------------------------------------------------------------
fill_1 FILL_CELL xyz.mw 26.61 0 (3100.00, 700.00)
fill_2 FILL_CELL xyz.mw 26.61 0 (3000.00, 600.00)
-------------------------------------------------------------------------
Total 2 cells 53.22
1
#*************************************************
# SECTION: Std Cells, with number: 2
#*************************************************
set obj [get_cells {"fill_cell_1"} -all]
set_attribute -quiet $obj orientation N
set_attribute -quiet $obj origin {3100.000 700.000}
set_attribute -quiet $obj is_fixed TRUE
set obj [get_cells {"fill_cell_2"} -all]
set_attribute -quiet $obj orientation N
set_attribute -quiet $obj origin {3000 600.00}
set_attribute -quiet $obj is_fixed TRUE
The read_floorplan command extracts floorplan information
****************************************
Report : The RP groups, which could not be placed.
Version: 2005.12
Date : Tue Dec 27 16:32:02 2005
No. of RP groups:1
****************************************
RP GROUP: compare17::seg7
-------------------------------
Error: Could not get clean area for placing RP group compare17::seg7.
****************************************
Report : The RP groups, not meeting all constraints but placed.
Version: 2005.12
Date : Tue Dec 27 16:32:02 2005
No. of RP groups:1
****************************************
RP GROUP: compare17::rp_group_3
-------------------------------
Warning: Could not set user specified orientation for cell u[8].
dc_shell-topo> create_scenario s1
Warning: Any existing scenario-specific constraints are discarded. (MV-020)
dc_shell-topo> report_timing
Warning: No operating condition was set in scenario s1 (MV-021)
Information: Logic library consistency check FAILED for MCMM. (LIBCHK-360)
create_scenario s1
set_operating_conditions WORST -library Typ.db:Typ
create_scenario s2
set_operating_conditions WORST -library TypHV.db:TypHV
create_scenario s3
set_operating_conditions WORST -library Ftyp.db:Ftyp
create_scenario s4
set_operating_conditions \
-max WORST -max_library Typ.db:Typ \
-min BEST -min_library HoldTyp.db:HoldTyp
Error: Cannot find the specified driving cell in memory.(UID-993)
dc_shell-topo> create_scenario s1
Warning: Any existing scenario-specific constraints are discarded. (MV-020)
Current scenario is: s1
Report : power
Design : Design_1
Scenario(s): s1
Version: C-2009.06
Date : Wed Apr 15 12:52:02 2009
****************************************
Library(s) Used: slow (File: slow.db)
Global Operating Voltage = 1.08
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = Unitless
Warning: Could not find correlated power. (PWR-725)
Power Breakdown
---------------
Cell Driven Net Tot Dynamic Cell
Internal Switching Power (mW) Leakage
Cell Ower (mW) Power (mW) (% Cell/Tot) Power(nW)
------------------------------------------------------------------------
Netlist Power 4.8709 1.2889 6.160e+00 (79%) 1.351e+05
Estimated Clock Tree Power N/A N/A (N/A) N/A
------------------------------------------------------------------------
set_zero_interconnect_delay_mode true
report_qor
set_zero_interconnect_delay_mode false
Warning: Timer is in zero interconnect delay mode. (TIM-177)
Warning: Preserving net 'my_net'. Expect QoR impact. (OPT-154)
Warning: Created physical library cell for logical library
%s. (OPT-1413)
dc_shell-topo> create_cell -only_physical MY_U_PO_CELL MY_FILL_CELL
Information: create physical-only cell 'MY_U_PO_CELL'
Warning: The newly created cell does not have location.
Timing will be inaccurate. (DCT-004)
dc_shell> set PORTS [all_inputs]
{"A0", "A1", "A2", "A3"}
dc_shell> query_objects $PORTS
PORTS = {"A0", "A1", "A2", "A3"}
dc_shell> remove_design
Removing design ‘top’
1
dc_shell> query_objects $PORTS
Error: No such collection ‘_sel2’ (SEL-001)
dc_shell-topo> check_block_abstraction
Error: No scenario data loaded from block reference ’blk1’. (ILM-151)
Error: dont_touch attribute incorrectly set to false on block design ’blk2’. (ILM-
121)
0
get_rp_groups
{mul::grp_mul ripple::grp_ripple example3::top_group}
write_rp_groups -all -output my_groups.tcl
1
remove_rp_groups -all -quiet
1
get_rp_groups
Error: Can’t find objects matching ’*’. (UID-109)
source my_groups.tcl
{example3::top_group}
get_rp_groups
{example3::top_group ripple::grp_ripple mul::grp_mul}
remove_rp_groups ripple::grp_ripple
Removing rp group ’ripple::grp_ripple’
1
get_rp_groups *grp_ripple
Error: Can’t find object ’grp_ripple’. (UID-109)
remove_rp_groups -all
Removing rp group ’mul::grp_mul’
Removing rp group ’example3::top_group’
1
create_scenario s1
set_operating_conditions WORST -library stdcell.setup.typ.db:stdcell_typ
set_tlu_plus_files -max_tluplus design.tlup -tech2itf_map layermap.txt
read_sdc s1.sdc
Error: tlu_plus files are not set in this scenario s1.
RC values will be 0
Error: TLU+ sanity check failed (OPT-1429)
dc_shell-topo> create_scenario s1
Warning: Any existing scenario-specific constraints are discarded. (MV-020)
dc_shell-topo> report_timing
Warning: No operating condition was set in scenario s1 (MV-021)
Error: Cannot find the specified driving cell in memory.(UID-993)
Information: Logic library consistency check FAILED for MCMM. (LIBCHK-360)
Error: tlu_plus files are not set in this scenario <name>.
RC values will be 0.
Error: Scenario S6 is not available in ILM Block1. (ILM-70)
Error: Inconsistent use of ILM BlockInit in the multicorner-multimode
flow. ILM BlockInit has scenarios defined while top design Top does
not have scenarios defined. (ILM-73)
Error: The feature used to generate this DDC file is not supported by
this tool or is not enabled in the current session. (DDC-21)
Information: To pass this netlist from DC to other tools, please use
write_file -pg -f verilog ...
dc_shell> set PORTS [all_inputs]
{"A0", "A1", "A2", "A3"}
dc_shell> query_objects $PORTS
PORTS = {"A0", "A1", "A2", "A3"}
dc_shell> remove_design
Removing design ‘top’
1
dc_shell> query_objects $PORTS
Error: No such collection ‘_sel2’ (SEL-001)
#For each scenario, write out the original interface timing before
#creating the ILM
foreach scenario [all_scenarios] {
current_scenario ${scenario}
write_interface_timing -nosplit ${scenario}.interface_timing.rpt
}
create_ilm
foreach scenario [all_scenarios] {
current_scenario ${scenario}
#For each scenario, write out the interface timing after creating the ILM
write_interface_timing -nosplit ${scenario}.ILM.interface_timing.rpt
#Now verify that the ILM interface timing matches the original design
#using compare_interface_timing
compare_interface_timing \
${scenario}.interface_timing.rpt \
${scenario}.ILM.interface_timing.rpt \
-output ${scenario}.compare_interface_timing.rpt
}
write -format ddc -hierarchy -output ${design}.ILM.ddc
From To Type Worst Slack Difference Status
Ref Model
-----------------------------------------------------------------------------------
---
tdi INPUTS max_rise 1.283 1.345 -0.062 PASS
tdi INPUTS max_fall 1.364 1.389 -0.035 PASS
tdi INPUTS min_rise 0.033 0.032 0.001 PASS
tdi INPUTS min_fall 0.026 0.027 -0.001 PASS
OUTPUTS DataSdram[6] max_rise 2.081 2.037 0.044 PASS
OUTPUTS DataSdram[6] max_fall 2.132 2.031 0.101 FAIL
OUTPUTS DataSdram[6] min_rise 1.329 1.328 0.001 PASS
OUTPUTS DataSdram[6] min_fall 1.347 1.345 0.002 PASS
Error: Pin ’B1/C1’/’INC1’ could not be found. (SDFN-10)
Error: The SDF file contains delays for the design ’SYSTEM’, they cannot be
annotated on design ’BAR’. (SDFN-4)
Warning: Overwriting the rise delay between pin 'M/Z' and pin 'U/A' with (4). (OPT-
835)
prompt> report_net
Information: Updating design information... (UID-85)
. . .
Attributes:
d - dont_touch
c - annotated capacitance
r - annotated resistance
Net Fanout Fanin Load Resistance Pins Attributes
----------------------------------------------------------
. . .
cell57/n16 1 1 1.00 100.00 2 r
cell57/n17 3 1 3.17 100.00 4 c, r
cell57/n18 2 1 5.36 100.00 3 c, r
. . .
----------------------------------------------------------
Total 13 nets 25 13 31.53 1300.00 38
Maximum 4 1 8.53 100.00 5
Average 1.92 1.00 2.43 100.00 3.22
prompt> remove_annotated_delay -from ffd/Q -to m/B
Warning: There is no timing arc between pin ‘ffd/Q’ and pin ‘m/B’. (OPT-834)
Information: Removing delays annotated to pin ‘w/A’. (OPT-831)
Information: Removing annotated delays from pin ‘ffc/QN’ to pin ‘w/A’. (OPT-830)
prompt> remove_annotated_delay -all
Information: Removing all annotated delays from design ‘counter’. (OPT-804)
prompt> check_timing
Information: Checking generated_clocks...
Information: Checking loops...
Information: Checking no_input_delay...
Information: Checking unconstrained_endpoints...
Warning: The following end-points are not constrained for maximum delay.
End point
---------------
sd_CK
sd_CKn
dc_shell-xg-t> read_verilog rtl/MYREG_rtl.v
Loading db file ‘../libraries/syn/gtech.db’
Loading db file ‘../libraries/syn/standard.sldb’
Loading verilog file ‘../risc_design/MYREG_rtl.v’
...
Warning: Can't read link_library file ‘your_library.db’.
...
Current design is ‘MYREG’
dc_shell-xg-t> read_verilog mapped/MYREG_mapped.v
dc_shell-xg-t> report_constraint –all_violators
Warning: Can't read link_library file 'your_library.db’.
...
Warning: Unable to resolve reference 'OR2_4x' in ‘MYREG'.
Warning: Unable to resolve reference 'NAND2_2x' in ‘MYREG'.
Warning: Unable to resolve reference 'MUX21_2x' in ‘MYREG'.
Warning: Unable to resolve reference 'DFF_4x' in ‘MYREG'.
...
****************************************
Report : constraint
-all_violators
Design: MYREG
Warning: In design ‘design_name’, there are sequential cells not connected to any
load. (OPT-109)
Information: Use the ‘check_design’ command for more information about warnings.
(LINT-99)
dc_shell> get_attribute [get_lib_pin MYTECHLIB/DFFSRST/D] nextstate_type
Warning: Attribute 'nextstate_type' does not exist on port 'D'. (UID-101)

Error information

Information: Error 1 Error: Cannot find the specified driving cell in memory.(UID-
993) (MSG-3032)
Information: Error 1 Error: No such collection ‘_sel2’ (SEL-001) (MSG-3032)
Information: Error 1 Error: No scenario data loaded from block reference ’blk1’.
(ILM-151) (MSG-3032)
Information: Error 1 Error: dont_touch attribute incorrectly set to false on block
design ’blk2’. (ILM-121) (MSG-3032)
Information: Error 2 Error: Can’t find objects matching ’*’. (UID-109) (MSG-3032)
Information: Error 1 Error: TLU+ sanity check failed (OPT-1429) (MSG-3032)
Information: Error 1 Error: Cannot find the specified driving cell in memory.(UID-
993) (MSG-3032)
Information: Error 1 Error: Scenario S6 is not available in ILM Block1. (ILM-70)
(MSG-3032)
Information: Error 1 Error: No such collection ‘_sel2’ (SEL-001) (MSG-3032)
Information: Error 1 Error: Pin ’B1/C1’/’INC1’ could not be found. (SDFN-10) (MSG-
3032)
Information: Error 1 Error: The SDF file contains delays for the design ’SYSTEM’,
they cannot be annotated on design ’BAR’. (SDFN-4) (MSG-3032)
Information: Error 1 Error: The feature used to generate this DDC file is not
supported by this tool or is not enabled in the current session. (DDC-21) (MSG-
3032)
Information: Error 1 Error: Inconsistent use of ILM BlockInit in the multicorner-
multimode flow. ILM BlockInit has scenarios defined while top design Top does not
have scenarios defined. (ILM-73) (MSG-3032)

summary

UID-993 Error 1
SEL-001 Error 1
ILM-151 Error 1
ILM-121 Error 1
UID-109 Error 2
OPT-1429 Error 1
UID-993 Error 1
ILM-70 Error 1
SEL-001 Error 1
SDFN-10 Error 1
SDFN-4 Error 1
DDC-21 Error 1
ILM-73 Error 1
LIBCHK-360 Information 2
UID-85 Information 1
OPT-831 Information 1
OPT-830 Information 1
OPT-804 Information 1
LINT-99 Information 1
MSG-3032 Information 13
OPT-154 Warning 1
MV-021 Warning 1
PWR-725 Warning 1
TIM-177 Warning 1
OPT-154 Warning 1
MV-021 Warning 1
OPT-834 Warning 1
UID-101 Warning 1
DCT-004 Warning 2
OPT-1413 Warning 2
MV-020 Warning 3
OPT-109 Warning 1

Check.error.list UID-993 SEL-001 ILM-151 ILM-121 UID-109 OPT-1429 UID-993 ILM-70

SEL-001 SDFN-10 SDFN-4 DDC-21 ILM-73