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16 views3 pages

New Thesis

Uploaded by

ssubramaniam1990
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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Abstract

With the increasing complexity of IP designs, verification has become quite popular yet is still
a significant challenge for a verification engineer. A proper verification environment can bring
out bugs that one may never expect in the design. On the contrary, a poorly designed verification
environment could give false information about the functioning of the design and bugs may
appear on the consumer’s end. Hence, the verification industry is continually looking for more
efficient verification methodologies. This paper describes one such efficient methodology
implemented on an Inter-Integrated Circuit (I2C) system. I2C packs in itself the powerful
features
of the Serial Peripheral Interface (SPI) and the universal asynchronous receiver-transmitter
(UART), but is comparatively more efficient and uses less hardware for implementation. Also,
it can establish secure communication between multiple masters and multiple slaves with
minimal wiring. In this project, from a design perspective, the master is a hardware block, and
the slave is a verification IP. The methodology used for verification is based on the Universal
Verification Methodology (UVM), a class library written in the SystemVerilog language. The
paper describes how the verification of an I2C system uses the powerful tools of UVM. The
master core has been successfully verified and the coverage goals are met. The effort has been
documented in this paper in detail.
Chapter 1
Introduction
Back when fabrication of devices with dimensions in microns was a wonder, designs were not
as intricate, and the prime focus was on design more than verification. However, now, with
rapid advancement in technology scaling, verification has become more of a challenge. As the
designs became smaller, more space became available on the chip, and it gave the designer a
chance to add new features and capabilities to the design. As a result, many sensors were built
right onto the chip instead of connecting it with external sensors.
With these new possibilities in technology and more complex designs, a straightforward
verification plan of toggling a few pins and observing the output no longer works. Each design
has so many pins connected to it that the connections alone take up multiple lines of code
and it is a misuse of time and intelligence to keep all the verification related code in one file
and navigate through it. A layered test-bench helps to maintain modular code such that all
the wiring is in one file, the input stimulus in one and so forth. This way, when a verification
engineer needs to add new features to the verification environment, navigation through all the
files is not needed, and change in the code of one file causes little/no change in other files.
1.1 Research Goals 2
Thus it helps in maintainability of the code.
This paper discusses one such efficient and re-usable verification environment applied to
an Inter-Integrated Circuit (I2C) system with a Master as hardware and slave as a verification
IP. The environment uses the useful features of Universal Verification Methodology (UVM)
such as sequences, transaction level modeling, object-oriented programming, advanced data
types, and functional coverage to verify the system thoroughly. The sections below describe
the motivation, research goals and the organization of this paper.
1.1 Research Goals
The primary intent of setting up this verification environment is to research and implement
a self-checking, constrained random, layered test-bench using the UVM framework and to
observe its effectiveness. Shown below is a summary of the leading research goals:
• To understand the I2C protocol and integrate the master core with multiple slave VIPs
to validate it.
• To observe the effectiveness of a self-checking test-bench and a random sequence generator
through functional coverage and assertions.
• To come up with an effective verification methodology that is applicable not only to
I2C, but could also easily be applied to other communication protocols. More on this is
discussed in the following chapters.

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