CSIT212

Lab 3
1 . Suppose a computer using direct mapped cache has 2 bytes of byte-addressable main
20

memory, and a cache of 32 blocks, where each cache block contains 16 bytes.
a) How many blocks of main memory are there?
220 / 24 = 216
b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of
the tag, block, and offset fields?
20 bit addreses with 11 bit in the tag field , 5 in the block field, and 4 in the offset field
c) To which cache block will the memory address 0x0DB63 map?
0DB63 =  0000 1101  1011  0110 0011
To block 22
2. Suppose a computer using direct mapped cache has 2 bytes of byte-addressable main memory
32

and a cache size of 512 bytes, and each cache block contains 64 bytes.
a) How many blocks of main memory are there?
232 / 26 = 226
b) What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag,
block, and offset fields?
23 bits in the tag field, 3 in the block field, and 6 in the offset field.

c) To which cache block will the memory address 0x13A4498A map?

To block 6

3. Suppose a computer using fully associative cache has 2 bytes of byte-addressable main
24

memory and a cache of 128 blocks, where each cache block contains 64 bytes.
a) How many blocks of main memory are there?
224 / 26 = 218
b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag
and offset fields?

24 bit addresses with 18 bits in the tag field and 6 in the offset field
d) To which cache block will the memory address 0x01D872 map?
Its an associative cache , it maps anywhere
4. Suppose we have a computer that uses a memory address word size of 8 bits. This computer
has a 16-byte cache with 4 bytes per block. The computer accesses a number of memory
locations throughout the course of running a program.
Suppose this computer uses direct-mapped cache. The format of a memory address as seen by
the cache is shown below:
The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E,
0x4F, 0x50, 0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. The memory addresses of the
first four accesses have been loaded into the cache blocks as shown below. (The contents of the
tag are shown in binary and the cache “contents” are simply the address stored at that cache
location.)

a) What is the hit ratio for the entire memory reference sequence given above, assuming we
count the first four accesses as misses?
Out of 14 memory accesses , there are 10 misses , the hit ratio is 28.57%
H =( access – misses) / accesses
= (14 – 10 )/ 14
= 28.57%

b) What memory blocks will be in the cache after the last address has been accessed?
Block 0 , tag 1001 , contains 90 91 92 93
Block 1 , tag 1001 , contains 94 95 96 97
Block 2 , tag 1010 , contains A8 A9 AA AB
Block 3 , tag 1010 , contains AC AD AE AF

5. Assume a direct-mapped cache that holds 4096 bytes, where each block is 16 bytes.
Assuming an address is 32 bits and that cache is initially empty, complete the table below. (You
should use hexadecimal numbers for all answers.) Which, if any of the addresses will cause a
collision (forcing the block that was just brought in to be overwritten) if they are accessed one
right after the other?
 Address Tag Cache location Offset within block
0x0FF0FABA 0FF0F AB A
0X00000011 00000 01 1
0X0FFFFFFE 0FFFF FF E
0X23456719 23456 71 9
0XCAFEBABE CAFEB AB E

0XCAFEBABE colliding