Ee6602 Embedded Systems LT P C 3 0 0 3

EE8691-Embedded Systems Department of EIE 2021-2022
EE6602 EMBEDDED SYSTEMS LT P C 3 0 0 3

UNIT I INTRODUCTION TO EMBEDDED SYSTEMS 9
Introduction to Embedded Systems – The build process for embedded systems- Structural
units in Embedded processor , selection of processor & memory devices- DMA – Memory
management methods- Timer and Counting devices, Watchdog Timer, Real Time Clock, In
circuit emulator, Target Hardware Debugging.
UNIT II EMBEDDED NETWORKING 9
Embedded Networking: Introduction, I/O Device Ports & Buses– Serial Bus communication
protocols - RS232 standard – RS422 – RS485 - CAN Bus -Serial Peripheral Interface (SPI) –
Inter Integrated Circuits (I2C) –need for device drivers.
UNIT III EMBEDDED FIRMWARE DEVELOPMENT ENVIRONMENT 9
Embedded Product Development Life Cycle- objectives, different phases of EDLC,
Modelling of EDLC; issues in Hardware-software Co-design, Data Flow Graph, state
machine model, Sequential Program Model, concurrent Model, object oriented Model.
UNIT IV RTOS BASED EMBEDDED SYSTEM DESIGN 9
Introduction to basic concepts of RTOS- Task, process & threads, interrupt routines in RTOS,
Multiprocessing and Multitasking, Preemptive and non-preemptive scheduling, Task
communication shared memory, message passing-, Inter process Communication –
synchronization between processes-semaphores, Mailbox, pipes, priority inversion, priority
inheritance, comparison of Real time Operating systems: Vx Works, чC/OS-II, RT Linux.
UNIT V EMBEDDED SYSTEM APPLICATION DEVELOPMENT 9
Case Study of Washing Machine- Automotive Application- Smart card System Application,.
TOTAL: 45 PERIODS
TEXT BOOKS:
1. Rajkamal, ‘Embedded System-Architecture, Programming, Design’, Mc Graw Hill, 2013.
2. Peckol, “Embedded system Design”, John Wiley & Sons,2010
3. Lyla B Das,” Embedded Systems-An Integrated Approach”, Pearson, 2013
REFERENCES:
1. Shibu. K.V, “Introduction to Embedded Systems”, Tata Mcgraw Hill,2009.
2. Elicia White,” Making Embedded Systems”, O’ Reilly Series,SPD,2011.
3. Tammy Noergaard, “Embedded Systems Architecture”, Elsevier, 2006.
4. Han-Way Huang, ”Embedded system Design Using C8051”, Cengage Learning,2009.
Able to understand the basics of Embedded Systems with the analysis of linear and
C402.1 digital electronic circuits.
Able to develop inter communicating Embedded System with its building blocks like
C402.2 embedded processor, memory and I/O devices using different communication
protocols.
Able to understand entire life cycle of embedded product development, also Partition
C402.3
Hardware and Software using various embedded development strategies.
Able to understand the differences between the general computing system and the em-
C402.4 bedded system, also design real time embedded systems using the concepts of RTOS.
Able to demarcate hardware and software fault of washing

C402.5 machine, automotive application and Smart card System.
5. Rajib Mall “Real-Time systems Theory and Practice” Pearson Education, 2007.
COURSE OUTCOME
On completion of this course, the students will be,
MAPPING OF CO AND PO WITH CORRELATION LEVEL1/2/3

CO PO PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO PSO
1 St. 2Joseph’s3College4of Engineering
5 6 7 8 91 0 1 2 1 2 3
C402. 3 3 3 1 1 1 - - - - 1 2 3 2 1
1
C402. 3 3 3 2 2 1 - 1 - - 1 3 3 2 1
2
C402. 3 3 3 2 2 1 - 1 1 1 2 3 3 3 1
3
C402. 3 3 3 3 2 1 - 1 1 1 2 3 2 2 2
4
C402. 3 3 3 2 3 2 2 2 2 1 3 3 3 2 3
5 Unit I
INTRODUCTION TO EMBEDDED SYSTEMS
Sl.No.Knowledge level Course Content CO State-
1. U Introduction to Embedded Systems ment
2. U/R The build process for embedded systems and its vari-
ous Structural units.
3. U/R/An The process of selection of processor & memory de-
4. U/R vices in embedded system
DMA C402.1
5. U The various Memory management
6. U/R Methods
Timer and Counting devices
7. U/R Watchdog Timer
8. U/R Real Time Clock
9. U/An In circuit emulator and Target
Hardware Debugging.
Unit II
EMBEDDED NETWORKING
1. U Embedded Networking ment
2. U/R I/O Device Ports & Buses
3. U/R Serial Bus communication protocols
4. U/R RS232 standard
C402.2
5. U RS422 and RS485
6. U CAN Bus
7. U Serial Peripheral Interface (SPI)
8. U Inter Integrated Circuits
9. U Need for device drivers
Unit III
EMBEDDED FIRMWARE DEVELOPMENT ENVIRONMENT
1. U Objectives of Embedded Product Development Life ment
2. U Cycle. phases of EDLC
Different
3. U/E Modeling of EDLC
4. U/An Issues in Hardware-software Co-design
C402.3
5. U/An Data Flow Graph
6. U State machine model
7. U Sequential Program Model
8. U Concurrent Model
9. U Object oriented Model
Unit IV
RTOS BASED EMBEDDED SYSTEM DESIGN
St. Joseph’s College of Engineering 2
1. U Introduction to basic concepts of RTOS
2. U Task, process & threads
3. U/R Interrupt routines in RTOS,
4. U Multiprocessing and Multitasking
5. U Preemptive and non-preemptive scheduling
6. U Task communication shared C402.4
7. U Message passing-, Inter process Communication
8. Synchronization between
U/An
processes-semaphores, Mailbox, pipes, priority inver-
9. sion.
Comparison of Real
U/An
time Operating systems: VxWorks, чC/OS-II, RT
Unit V
EMBEDDED SYSTEM APPLICATION DEVELOPMENT
1. U/Ap Washing Machine Application ment
2. U/Ap Washing Machine hardware
3. U/Ap Washing Machine software
4. U/Ap Automotive Application
C402.5
5. U/Ap Automotive hardware software
6. U/Ap Automotive software
7. U/Ap Smart card System Application
8. U/Ap Smart card System-hardware
9. U/Ap Smart card System software
Ap – Appling; An – Analyzing; U – Understanding, E- Evaluating,C-Creating,R-
Remembering
UNIT – I
INTRODUCTION TO EMBEDDED SYSTEMS
Part – B (C402.1)
1. Explain the process of converting high level language application software in to a ROM
image for an embedded system.
To do all the coding in assembly language may be very time consuming in most cases.
Software istherefore developed in a high-level language, ‘C’ or ‘C++’ or ‘Java’. Most of
the times, ‘C’ is thepreferred language. For coding, there is little needto understand
assembly language instructions and the programmer does not have to know the
machinecode for any instruction at all. The programmer needs to understand only the
hardware organization.
As an example, consider the following problem:
Add 127, 29 and 40 and print the square root.

An exemplary C language program for all the processors is as follows: (i) # include
<stdio.h>(ii) #
include <math.h>(iii) void main (void) { (iv) int i1, i2, i3, a; float result; (v) i1 = 127; i2
= 29; i3 = 40;
a = i1 + i2 + i3; result = sqrt (a); (vi) printf (result);}
It is evident, then, that coding for square-root will need many lines of code and can be
done only byan expert assembly language programmer. To write the program in a high
level language is very simplecompared to writing it in the assembly language. ‘C’
programs have a feature that adds the assemblyinstructions when using certain processor-
specific features and coding for the specific section, forexample, port device driver. the
different programming layers in a typical embedded‘C’ software. These layers are as
follows. (i)Processor Commands. (ii) Main Function. (iii) Interrupt Service Routine. (iv)
Multiple tasks, say, 1 toN. (v) Kernel and Scheduler. (vi) Standard library functions,
protocol functions and stack allocationfunctions.Figure 1.8 shows the process of
converting a C program into the ROM image file. A compilergenerates the object codes.
The compiler assembles the codes according to the processor instructionset and other
specifications.
The ‘C’ compiler for embedded systems must, as a final step of compilation,use a code-
optimizer. It optimizes the codes before linking. After compilation, the linker linksthe
object codes with other needed codes. For example, the linker includes the codes for the
functions,printfandsqrt codes. Codes for device management and driver (device control
codes) also link at thisstage: for example, printer device management and driver codes.
2. Explain in detail the design process involved in embedded system /Explain in detail
about the different embedded processors in a system.(DEC 2014) (MAY 2015).
PROCESSOR EMBEDDED INTO A SYSTEM
A processor is the heart of the embedded system. For an embedded system designer,
knowledge of microprocessors and microcontrollers is a prerequisite. In the following
explanations, too, it has been presumed that the reader has a thorough understanding of
microprocessors or microcontrollers. [The reader may refer to a standard text or the texts
listed in the ‘References’ at the end of this book for an in-depth understanding of
microprocessors, microprocessors and DSPs that are incorporated in embedded system
design.]
EMBEDDED PROCESSOR IN A SYSTEM

A processor has two essential units: Program Flow Control Unit (CU) and Execution Unit
(EU). The CU includes a fetch unit for fetching instructions from the memory. The EU
has circuits that implement the instructions pertaining to data transfer operations and data
conversion from one form to another. The EU includes the Arithmetic and Logical Unit
(ALU) and also the circuits that execute instructions for a program control task, say, halt,
interrupt, or jump to another set of instructions. It can also execute instructions for a call
or branch to another program and for a call to a function. A processor runs the cycles of
fetch and execute. The instructions, defined in the processor instruction set, are executed
in the sequence that they are fetched from the memory. A processor is mostly in the form
of an IC chip; alternatively, it could be in core form in an ASIC or at a SoC. Core means a
part of the functional circuit on the VLSI chip.
An embedded system processor chip or core can be one of the following.

1. General Purpose Processor (GPP):
a. Microprocessor.
b. Microcontroller.
c. Embedded Processor.
d. Digital Signal Processor (DSP).
e. Media Processor.
2. Application Specific System Processor (ASSP) as additional processor [Refer to
Section 1.2.6.]
3. Multiprocessor system using General Purpose processors (GPPs) and Application
Specific Instruction Processors (ASIPs)
4. GPP core (s) or ASIP core (s) integrated into either an Application Specific Integrated
Circuit (ASIC), or a Very Large Scale Integrated Circuit (VLSI) circuit or an FPGA core
integrated with processor unit(s) in a VLSI (ASIC) chip.
For a system designer, the following are important considerations when selecting a
processor:
1. Instruction set.
2. Maximum bits in an operand (8 or 16 or 32) in a single arithmetic or logical operation.
3. Clock frequency in MHz and processing speed in Million Instructions Per Second
(MIPS).
[Refer to Appendix B for an alternate metric Dhyrystonefor processing performance.]
4. Processor ability to solve the complex algorithms used in meeting the deadlines for
theirprocessing.

Microprocessor
The CPU is a unit that centrally fetches and processes a set of general-purpose
instructions. The CPU instruction set (Section 2.4) includes instructions for data transfer
operations, ALU operations, stack operations, input and output (I/O) operations and
program control, sequencing and supervising operations. The general purpose instruction
set (refer to Appendix A, Section A.1) is always specific to a specific CPU. Any CPU
must possess the following basic functional units.
1. A control unit to fetch and control the sequential processing of a given command or
instruction and for communicating with the rest of the system.
2. An ALU for the arithmetic and logical operations on the bytes or words. It may be
capable of processing 8, 16, 32 or 64 bit words at an instant.
A microprocessor is a single VLSI chip that has a CPU and may also have some other
units (for examples, caches, floating point processing arithmetic unit, pipelining and
super-scaling units) that are additionally present and that result in faster processing of
instructions. [Refer to Section 2.1.] The earlier generation microprocessor’s fetch-and-
execute cycle was guided by clock frequency of the order of ~1 MHz. Processors now
operate at clock frequency of 2 GHz. [Intel released a 2 GHz processor on August 25,
2001. This also marked the twentieth anniversary of the introduction of the IBM PC. Intel
released 3 GHz Pentium 4 on April 14, 2003.] Since early 2002, a few highly
sophisticated embedded systems (for examples, Gbps transceiver and encryption engine)
have incorporated the GHZ processor. [Gbps means Giga bit per second. Transceiver
means a transmitting cum receiving circuit with appropriate processing and controls, for
example, for bus-collisions.]
One example of an older generation microprocessor is Intel 8085. It is an 8-bit processor.
Another is Intel 8086 or 8088, which is a 16-bit processor. Intel 80x86 (also referred as
x86) processors are the 32-bit successors of 8086. [The x here means extended 8086 for
32 bits.] Examples of 32-bit processors in 80x86 series are Intel 80386 and 80486.
Mostly, the IBM PCs use 80x86 series of processors and the embedded systems
incorporated inside the PC for specific tasks (like graphic accelerator, disk controllers,
network interface card) use these microprocessors. An example of the new generation 32-
and 64-bit microprocessor is the classic Pentium series of processors from Intel. These
have superscalar architecture [Section 2.1]. They also possess powerful ALUs and
Floating Point Processing Units (FLPUs) [Table 2.1]. An example of the use of Pentium
III operating at 1 GHz clock frequency in an embedded system is the ‘Encryption
Engine’. This gives encrypted data at the rate of 0.464 Gbps.
Table 1.1lists the important microprocessors used in the embedded

systems.Themicroprocessorsare among the following streams of families:
The microprocessors from Streams 1 and 2 have Complicated Instruction Set Computer
(CISC)
architecture [Section A.1]. Microprocessors form Streams 3 and 4 have Reduced
Instruction SetComputer (RISC) architecture [Section A.1.4]. An RISC processor
provides speedy processing of the instructions, each in a single clock-cycle. Further,
besides the greatly enhanced capabilities mentioned above, there is great enhancement of
the speed by which an instruction from a set is processed. Thumb‚ Instruction set is a new
industry standard that also gives a reduced code density in a RISC processor. [The
concepts of architecture features of the processor in an embedded system, CISC and RISC
processors and processor instruction-set will be explained later in Appendices A and B.]
RISCs are used when the system needs to perform intensive computation, for example, in
a speech processing system.
How does a system designer select a microprocessor? This will be explained in Section
2.2.
MICROCONTROLLER
Just as a microprocessor is the most essential part of a computing system, a
microcontroller is the most essential component of a control or communication circuit. A
microcontroller is a single-chip VLSI unit (also called ‘microcomputer’) which, though
having limited computational capabilities, possesses enhanced input-output capabilities
and a number of on-chip functional units. [Refer to Section 1.3 for various functional
units.] Microcontrollers are particularly suited for use in embedded systems for real-time
control applications with on-chip program memory and devices. Figure 1.2 shows the
functional circuits present (in solid boundary boxes) in a microcontroller. It also shows
the application-specific units (in dashed boundary boxes) in a specific version of a given
microcontroller family. A few of the latest microcontrollers also have high computational
and superscalar processing capabilities. [For the meaning of superscalar architecture, refer
to Section 2.1.] Appendix C gives the comparative functionalities of select
microcontroller representatives from these families. Important microcontroller chips for
embedded systems are usually among the following five streams of families given in
Table 1.2.

Figure 1.3 shows commonly used microcontrollers in the small-, medium- and large-
scale embedded systems. In Section C.1 (refer to Tables C.1.1 to C.1.3 therein) those
features will be described that have to be considered by a system designer before
choosing a microcontroller as a processing unit.
Embedded System Design Process

An Overview of the embedded system design process aimed at two objectives.
1) Steps in Embedded System Design
The major steps in the embedded system design process are given in the diagram below.
Inthis top-down view, we start with the system requirements. In the next step,
specification,we create a more detailed description of what we want. But the specification
statesonly how the system behaves, not how it is built. The details of the system’s
internalsbegin to take shape when we develop the architecture, which gives the system
structurein terms of large components. Once we know the components we need, we can
designthose components, including both software modules and any specialized hardware
weneed. Based on those components, we can finally build a complete system.The
alternativeis a bottom-up view in which we start with components to build a system.
Bottom-updesign steps are shown in the figure as dashed-line arrows. We need bottom-
up designbecause we do not have perfect insight into how later stages of the design
process willturn out. Decisions at one stage of design are based upon estimates of what
will happenlater: How fast can we make a particular function run? How much memory
will we need?How much system bus capacity do we need?
2) Design Methodology

2) Design Methodology
An embedded system is a system that has three main components embedded into it
I. It embeds hardware similar to a computer. Figure 1.1 shows the units in the hardware or an em-
bedded system. As its software usually embeds in the ROM or flash memory, it usually do not
need a secondary hard disk and CD memory as in a computer
2. It embeds main application software. The application software may concurrently perform a
series of tasks or processes or threads
3, It embeds a real-time operating system (RTOS) that supervises the application software running
on hardware and organizes access to a resource according to the priorities of tasks in the system.
It provides a mechanism to let the processor run a process as scheduled and context-switch
between the various processes. (The concept of process. thread and task explained later in Sec-
tions 7.1 to 7.3.) It sets the rules during the execution of the application software. (A small-scale
embedded system may no embed the RTOS)
Built-in process:
Assembly language coding is extremely useful for configuring physical devices like ports. A line-
display interface, ADC and DAC and reading into or transmitting from a buffer. These codes are
also called low-level codes for the device driver functions
Lack of knowledge of writing device driver codes or codes that utilize the processor-specific fea-
tures- invoicing codes in an embedded system design team can cost a lot a vendor may charge for
the APIs and also charge intellectual property fees for each system shipped out of the company.
To make all the codes in assembly language may, however, be very time consuming. Full coding
assembly may be done only for a few simple, small-scale systems, such as toys, automatic chocol-
ate vending machines, robots or data acquisition systems.
1. An assembler translates the assembly software into the machine codes using a step called as-
sembling.
2. In the next step, called linking, a linker links these codes with the other codes required. Linking
is necessary because of the number of codes to be linked for the final binary file. For example,
there are the standard codes to program a delay task for which there is a reference in the assembly
language program. The codes for the delay must link with the assembled codes. The delay code is
sequential from a certain beginning address. The assembly software code is also sequential from a
certain beginning address. Both the codes have to be linked at the distinct addresses as well as at
the available addresses in the system, the linked file in binary for run on a computer is commonly
known as an executable file or simply an ‘.exe’ file. After linking, there has to be reallocation of
the sequences of placing the codes before actually placing the codes in memory.
3. In the next step, the louder program performs the task of reallocating the codes after finding the
physical memory addresses available at a given instant. The loader is a pail of the operating sys-
tem and places codes into the memory after reading the ‘exe’ rile. This step is necessary because
the available memory addresses may not start from Ox0000, and binary codes have to be loaded
at different addresses during the run. The loader finds the appropriate start address. In a computer,
after the loader loads into a section of RAM, the program is ready to run.
4. The final step of the system design process is locating these codes as a ROM image. The codes
are permanently placed at the addresses actually available in the ROM. In embedded systems,
there is no program to keep track of the available addresses at different times during the run, as in
a computer. In embedded systems, therefore, the next step instead of loader after linking is the use
of a locater, which locates the I0 tasks and hardware device driver codes at fixed addresses. P0(1
and device addresses are fixed for a given system as per the interfacing circuit between the system
buses and ports or devices. the locator program reallocates the linked file and creates a file for a
permanent location of the codes in a standard format. The file format may be in the Intel Hex file
format or Motorola s-record format .The designer has to define die available addresses to locate
and create files to permanently locate the codes.
5. Lastly, either (i) a laboratory system. called device programmer, takes as input the ROM image
file and finally burns the image into the PROM or flash or (ii) at foundry, a mask is created for
the ROM of the embedded system from the ROM image file. (The process of placing the codes in
PROM or flash is also called burning.]The mask created from the image gives the ROM in IC
chip form.
3. List the various hardware units that must in be present the Embedded system. (Dec
2017)
EMBEDDED SYSTEM
A computer is a system that has the following or more components.
1. A microprocessor
2. A large memory comprising the following two kinds:
(a) Primary memory (semiconductor memories - RAM, ROM and fast accessible caches)
(b) Secondary memory (magnetic memory located in hard disks, diskettes and cartridge tapes
and optical memory in CD-ROM)
3. Input units like keyboard, mouse, digitizer, scanner, etc.
4. Output units like video monitor, printer, etc.
5. Networking units like Ethernet card, front-end processor-based drivers, etc.
6. I/O units like a modem, fax cum modem, etc.
An embedded system is one that has computer-hardware with software embedded in it as one
of its most important component. It is a dedicated computer-based system for an
application(s) or product. It may be either an independent system or a part of a larger system.
As its software usually embeds in ROM (Read Only Memory) it does not need secondary
memories as in a computer.
An embedded system has three main components:
1. It has hardware. Figure 1.1 shows the units in the hardware of an embedded system.
2. It has main application software. The application software may perform concurrently the
series of tasks or multiple tasks.
3. It has a real time operating system (RTOS) that supervises the application software and
provides a mechanism to let the processor run a process as per scheduling and do the context-
switch between the various processes (tasks). RTOS defines the way the system works. It
organizes access to a resource in sequence of the series of tasks of the system. It schedules
their working and execution by following a plan to control the latencies and to meet the
deadlines. [Latency refers to the waiting period between running the codes of a task and the
instance at which the need for the task arises.] It sets the rules during the execution of the
application software. A small-scale embedded system may not need an RTOS. An embedded
system has software designed to keep in view three constraints: (i) available systemmemory,
(ii) available processor speed and (iii) the need to limit power dissipation when running the
system continuously in cycles of wait for events, run, stop and wake-up. There are several
definitions of embedded systems given in books published recently. Given below is a series
of definitions from others in the field:
(1) “An embedded system is a system whose principal function is not computational, but
which is controlled by a computer embedded within it. The computer is likely to be a
microprocessor or microcontroller. The word embedded implies that it lies inside the overall
system, hidden from view, forming an integral part of greater whole”.
(2) “An embedded system is a microcontroller-based, software-driven, reliable, real time

control system, autonomous, or human- or network-interactive, operating on diverse physical
variables and in diverse environments, and sold into a competitive and cost-conscious
market”.
the major components of an embedded system hardware
4. How the Real time systems differ from conventional system? (MAY 2015) (DEC2014
A Real-Time Operating System (RTOS) is a computing environment that reacts to input
within a specific time period. A real-time deadline can be so small that system reaction
appears instantaneous. The term real-time computing has also been used, however, to
describe "slow real-time" output that has a longer, but fixed, time limit.
Learning the difference between real-time and standard operating systems is as easy as
imagining yourself in a computer game. Each of the actions you take in the game is like a
program running in that environment. A game that has a real-time operating system for its
environment can feel like an extension of your body because you can count on a specific "lag
time:" the time between your request for action and the computer's noticeable execution of
your request. A standard operating system, however, may feel disjointed because the lag time
is unreliable. To achieve time reliability, real-time programs and their operating
system environment must prioritize deadline actualization before anything else. In the gaming
example, this might result in dropped frames or lower visual quality when reaction time and
visual effects conflict.
5.Explain the components of embedded system hardware and the functional circuits in
the core of microcontroller.
EMBEDDED SYSTEM
A computer is a system that has the following or more components.
1. A microprocessor
2. A large memory comprising the following two kinds:
(a) Primary memory (semiconductor memories - RAM, ROM and fast accessible caches)
(b) Secondary memory (magnetic memory located in hard disks, diskettes and cartridge tapes
and optical memory in CD-ROM)
3. Input units like keyboard, mouse, digitizer, scanner, etc.
4. Output units like video monitor, printer, etc.
5. Networking units like Ethernet card, front-end processor-based drivers, etc.
6. I/O units like a modem, fax cum modem, etc.
An embedded system is one that has computer-hardware with software embedded in it as one
of its most important component. It is a dedicated computer-based system for an
application(s) or product. It may be either an independent system or a part of a larger system.
As its software usually embeds in ROM (Read Only Memory) it does not need secondary
memories as in a computer.
An embedded system has three main components:
1. It has hardware. Figure shows the units in the hardware of an embedded system.
2. It has main application software. The application software may perform concurrently the
series of tasks or multiple tasks.
3. It has a real time operating system (RTOS) that supervises the application software and
provides a mechanism to let the processor run a process as per scheduling and do the context-
switch between the various processes (tasks). RTOS defines the way the system works. It
organizes access to a resource in sequence of the series of tasks of the system. It schedules
their working and execution by following a plan to control the latencies and to meet the
deadlines. [Latency refers to the waiting period between running the codes of a task and the
instance at which the need for the task arises.] It sets the rules during the execution of the
application software. A small-scale embedded system may not need an RTOS. An embedded
system has software designed to keep in view three constraints: (i) available systemmemory,
(ii) available processor speed and (iii) the need to limit power dissipation when running the
system continuously in cycles of wait for events, run, stop and wake-up. There are several
definitions of embedded systems given in books published recently. Given below is a series
of definitions from others in the field:
(1) “An embedded system is a system whose principal function is not computational, but
which is controlled by a computer embedded within it. The computer is likely to be a
microprocessor or microcontroller. The word embedded implies that it lies inside the overall
system, hidden from view, forming an integral part of greater whole”.
(2) “An embedded system is a microcontroller-based, software-driven, reliable, real time

control system, autonomous, or human- or network-interactive, operating on diverse physical
variables and in diverse environments, and sold into a competitive and cost-conscious
market”.
the major components of an embedded system hardware
MICROCONTROLLER
Just as a microprocessor is the most essential part of a computing system, a microcontroller is
the most essential component of a control or communication circuit. A microcontroller is a
single-chip VLSI unit (also called ‘microcomputer’) which, though having limited
computational capabilities, possesses enhanced input-output capabilities and a number of
on-chip functional units. [Refer to Section 1.3 for various functional units.] Microcontrollers
are particularly suited for use in embedded systems for real-time control applications with on-
chip program memory and devices. Figure 1.2 shows the functional circuits present (in solid
boundary boxes) in a microcontroller. It also shows the application-specific units (in dashed
boundary boxes) in a specific version of a given microcontroller family. A few of the latest
microcontrollers also have high computational and superscalar processing capabilities. [For
the meaning of superscalar architecture, refer to Section 2.1.] Appendix C gives the
comparative functionalities of select microcontroller representatives from these families.
Important microcontroller chips for embedded systems are usually among the following five
streams of families given in Table 1.2.
Figure 1.3 shows commonly used microcontrollers in the small-, medium- and large-scale
embedded systems. In Section C.1 (refer to Tables C.1.1 to C.1.3 therein) those features will
be described that have to be considered by a system designer before choosing a
microcontroller as a processing unit.

6.(i)Explain an Embedded System on chip and in VLSI circuit.
Lately, embedded systems are being designed on a single silicon chip, called System on
chip (SoC).SoC is a new design innovation for embedded systems. An embedded processor is
a part of the SoCVLSI circuit. A SoC may be embedded with the following components:
multiple processors, memories,multiple standard source solutions, called IP (Intellectual
Property) cores and other logic andanalog units. A SoC may also have anetwork protocol
embedded into it. It may also embed anencryption function unit. It can embed discrete cosine
transforms for signal processing applications. Itmay embed FPGA (Field Programmable Gate
Array) cores [Section 1.6.5].
For a number of applications, the GPP (microcontrollers, microprocessors or DSPs) cores
may notsuffice. For security applications, killer applications, smart card, video game, palm
top computer, cellphone,mobile-Internet, hand-held embedded systems, Gbps transceivers,
Gigabits per second LANsystems and satellite or missile systems, we need special processing
units in a VLSI designed circuit tofunction as a processor. These special units are called
Application Specific Instruction Processors(ASIP). For an application, both the configurable
processors (called FPGA cum ASIP processors) andnon-configurable processors (DSP or
Microprocessor or Microcontrollers) might be needed on achip. One example of a killer
application using multiple ASIPs is high-definition television signalsprocessing. [High
definition means that the signals are processed for a noise-free, echo-canceledtransmission,
and for obtaining a flat high-resolution image (1920 x 1020 pixels) on the televisionscreen.]
A cell-phone is another killer application. [A killer application is one that is useful to millions
ofusers.]
Recently, embedded SoCs have been designed for functioning as DNA chips. Consider an
FPGAwith a large number of gate arrays. Now, using VLSI design techniques, we can
configure thesearrays to process the specific tasks on anSoC. This gives anSoC as a DNA
chip. Each set of arrayshas a specific and distinct DNA complex structure. These structures as
well as the processor embedson the DNA chip.
6. (ii)Explain the details about exemplary Embedded System

(i) Automatic chocolate vending machine
Hardware required:
Processor- Micro controller, internal bus- 8 bit, processor architecture CISC , PROM- 4KB,
RAM- 256 bytes on chip, I/O ports-input for coin sorter port, delivery port, display port.
(ii) ROBOT
Hardware required:
Processor- Micro controller, internal bus- 8 bit, processor architecture CISC , PROM- 8KB,
RAM- 256 bytes on chip, I/O ports-multiple ports for motors and for angle encoders, PWM
for DAC,ADC
(iii) Mobile phone:
Hardware required:
Processor- Multi processor system on chip, internal bus- 32 bit, processor architecture RISC,
caches and MMU, PROM- 1MB,EEPROM-32kb, RAM- 1MB on SoC, I/O ports-keypad and
display ports, transceiver, real time detection of an event or signal, PWM for DAC, ADC,
modulation demodulation, DSP instruction.
(iv)Voice processor
Hardware required:
Processor- Microprocessor +DSP, internal bus- 32 bit, processor architecture RISC, caches
and MMU, PROM- 1MB,EEPROM & Flash-4MB, RAM- 1MB off-chip, I/O ports-input port
for speech and output port for replay, real time detection of an event or signal, PWM for
DAC, ADC, DSP instruction. Or any four exemplary systems.
7.ii) Explain the various types of Embedded Systems. (May 2018)
Types of embedded system

Real-time embedded system:
Real-time systems are those which give a quick response to critical situations. They are used
in military, medical and industrial applications. Engineers working in these systems have
high demand is current days. To develop the real-time embedded system we require timing
analysis, multitasking design, debugging, cross-platform testing and architecture design. In
these systems, quick response is very important. Better hardware is also used in these systems
to avoid failure in performance. Real-time systems control the external environment by input
& output interfaces and sensors. The external environment includes human and other animals.
Some examples of real-time embedded systems include:-
 Controlling heat, elevators, lights, and doors in buildings
 Robots
 Traffic control system including railway tracks, airspace, shipping lines, highways
 Radio, satellite and telephone communication
 Patient monitoring system
 Radiation therapy system in the hospital
 Computer games
 Multimedia systems which consist of video, audio, text and graphics interfaces
 Military usage that includes tracking, weapons, and command & control
Standalone embedded system:
This type of embedded system works for itself as a device without needing any interconnec-
ted computer. It can take data in the form of analog or digital signals. This system first pro-
cess data and then outputs data by displaying on the screen. It can also output data to any at-
tached device. Examples of standalone embedded systems include:-
 Microwave ovens
 Digital cameras
 Mp3 players
 Video game consoles
 Temperature measurement systems
Networked embedded system:
Networked embedded systems are those systems which are connected to the network to give
output to the attached resources. The devices in the networked embedded system are connec-
ted to the network with network interfaces. The network can be either a local area network
(LAN) or a wide area network (WAN). The connection in networked embedded systems can
be wireless or wired. This embedded system is fast and emerging its popularity over days.
The embedded web server is that which is connected to network devices and is controlled by
the web browser also. Example of this is the office security system. In office security system,

different sensors (light sensors, smoke sensors or motion detectors) are networked together
through LAN and controlled over the WAN (internet).
Mobile embedded system:

Mobile embedded systems are limited in resources including memory. Examples of mobile
embedded systems include:-
 Personal digital assistants (PDA)

 Cellular phones
 Mp3 players
 Digital cameras,
Small-scale embedded system:
Small-scale embedded systems consist of 8-16 bit microcontroller. This system can perform
tasks at a small level. They have on-chip ROM and RAM. Small-scale systems can be even
activated by the battery. The tools used to develop small-scale embedded systems are an ed-
itor, cross assembler, assembler and integrated development environment (IDE). The purpose
of this system is not computation but to control as a computer embedded inside it. It behaves
as a component of a computer and its function is not to compute. The small-scale system is
dedicated to some specific task. To apply for the job as a small-scale embedded designer you
need skills including data communication, digital electronic design, control engineering, soft-
ware engineering, computer architecture, motors & actuators, analog electronic design,
sensors & measurement and IC design & measurement.
Medium scale embedded system:
This embedded system has 16-32 bit microprocessor or microcontroller with external RAM
and ROM They can perform medium to complex level works. The integration between hard-
ware and software is complex in these embedded systems. Programming languages used to
develop medium scale embedded systems include Java, C, Visual C++, debugger, C++,
RTOS, simulator, source code engineering tool and IDE. The designer of the medium scale
embedded system should also know how to use semaphores, queues, mailboxes, pipes, and
sockets. Knowing the application programming interface (API) in the RTOS tool for con-
trolling microcontroller is also necessary.
Sophisticated embedded system:
The embedded system which can do large-scale works with multiple 32-64 bit chips is
known as sophisticated embedded systems. They can perform distributed work on a large
scale. The complexity of hardware and software is very high in these systems. In sophistic-
ated embedded systems, hardware and software are assembled together on large scale and
designing of hardware products is also included in these systems.
7. (i)Explain the concepts of DMA and structural units of an embedded
Processor?(May 2018)
DMA
Direct memory access (DMA) is a means of having a peripheral device control a processor's
memory bus directly. DMA permits the peripheral, such as a UART, to transfer data directly
to or from memory without having each byte (or word) handled by the processor. Thus DMA
enables more efficient use of interrupts, increases data throughput, and potentially reduces
hardware costs by eliminating the need for peripheral-specific FIFO buffers.
Dealing direct
In a typical DMA transfer, some event (such as an incoming data-available signal from a
UART) notifies a separate device called the DMA controller that data needs to be transferred
to memory. The DMA controller then asserts a DMA request signal to the CPU, asking its
permission to use the bus. The CPU completes its current bus activity, stops driving the bus,
and returns a DMA acknowledge signal to the DMA controller. The DMA controller then
reads and writes one or more memory bytes, driving the address, data, and control signals as
if it were itself the CPU. (The CPU's address, data, and control outputs are tristated while the
DMA controller has control of the bus.) When the transfer is complete, the DMA controller
stops driving the bus and deasserts the DMA request signal. The CPU can then remove its
DMA acknowledge signal and resume control of the bus.Each DMA cycle will typically
result in at least two bus cycles: either a peripheral read followed by a memory write or a
memory read followed by a peripheral write, depending on the transfer base addresses. The
DMA controller itself does no processing on this data. It just transfers the bytes as instructed
in its configuration registers. When designing with DMA, address buffers must be disabled
during DMA so the bus requester can drive them without bus contention. To avoid bus
contention, the bus buffer used by the DMA device must not drive the address bus until after
HLDA goes active to indicate that the CPU has stopped driving the bus signals, and it must
stop driving the bus before the CPU drives HLDA inactive. The system design may also need
pullup resistors or terminators on control signals (such as read and write strobes) so the
control signals don't float to the active state during the brief period when neither the
processor nor the DMA controller is driving them.DMA controllers require initialization by
software. Typical setup parameters include the base address of the source area, the base
address of the destination area, the length of the block, and whether the DMA controller
should generate a processor interrupt once the block transfer is complete.
DMA or burst
DMA operations can be performed in either burst or single-cycle mode. Some DMA
controllers support both. In burst mode, the DMA controller keeps control of the bus until all
the data buffered by the requesting device has been transferred to memory (or when the
output device buffer is full, if writing to a peripheral).
In single-cycle mode, the DMA controller gives up the bus after each transfer. This
minimizes the amount of time that the DMA controller keeps the processor off of the memory
bus, but it requires that the bus request/acknowledge sequence be performed for every
transfer. This overhead can result in a drop in overall system throughput if a lot of data needs
to be transferred.
STRUCTURAL UNITS
Characteristics:
An embedded system is characterized by the following: (I) Real-time and mukirateoperaticns-

define the ways in whieh the System works, reacts o events, interrupts and schedules the System’s
functioning in real time. It does so by nollowing a plan to control latencies and to meet deadlines.
(latency refers to the waiting period between running the codes of a task or interrupt service routine
and the instance at which (he need for the task or interrupt fron an event arises). The different opera-
tions may take place at distinct rates. For example, audio, video, data, network stream and events have
different rates and time constraints. (2) Complex algorithms. (3) Complex graphic user interfaces
(GUIs) and other user interfaces(4)Dedicated functions.
Constraints An embedded system is designed keeping in view three constraints: (1) available system-
memory. (2) Available processor speed. (3) The need to limit power dissipation when running the sys -
tem continuously in cycles of ‘wait for events: 'run’, 'stop’, ‘wakeup and 'sleep’. The system design or
an embedded system has Constraints with regard to performance. Power, size and design and manu-
facturing costs.

8.Compare the features of various types of memory (MAY 2015) (Dec 2017)
In a system, there are various types of memories. Figure 1.4 shows a chart for the various
forms ofmemories that are present in systems.
These are as follows:
(i) Internal RAM of 256 or 512 bytes in amicrocontroller for registers,temporary data and
stack.
(ii) Internal ROM/PROM/EPROM for about4 kB to 16 kB of program (in the case of
microcontrollers).
(iii) External RAM for the temporary dataand stack (in most systems).
(iv) Internal caches (in the case of certain microprocessors).
(v)EEPROM or flash (in many systems saving the results of processing in nonvolatile
memory: forexample, system status periodically and digital-camera images, songs, or
speeches after a suitableformat compression). (vi) External ROM or PROM for embedding
software (in almost all nonmicrocontroller-based systems).
(vii) RAM Memory buffers at the ports. (viii) Caches (in superscalar microprocessors).
Table 1.4 gives the functions assigned in the embedded systems to the memories. ROM or
PROM or EPROM embeds the embedded software specific to the system.
9.(i) Explain possible steps involved in build process of embedded control systems. (May
2017) (DEC 2016)
ASSEMBLY AND LINKING

Assembly and linking are the last steps in the compilation process they turn a list of
instructions into an image of the program’s bits in memory. Loading actually puts the
program in memory so that it can be executed. In this section, we survey the basic

techniques required for assembly linking to help us understand the complete compilation and
loading process.
The assembler’s job is to translate symbolic assembly language statements into bit-level
representations of instructions known as object code. The assembler takes care of instruction
formats and does part of the job of translating labels into addresses. However, since the
program may be built from many files, the final steps in determining the addresses of
instructions and data are performed by the linker, which produces an executable binary file.
That file may not necessarily be located in the CPU’s memory, however, unless the linker
happens to create the executable directly in RAM. The program that brings the program into
memory for execution is called a loader.The simplest form of the assembler assumes that
the starting address of the assembly language program has been specified by the
programmer. The addresses in such a program are known as absolute addresses.
Assemblers
When translating assembly code into object code, the assembler must translate opcodes and
format the bits in each instruction, and translate labels into addresses. In this section, we
review the translation of assembly language into binary. Labels make the assembly process
more complex, but they are the most important abstraction provided by the assembler. Labels
let the programmer (a human programmer or a compiler generating assembly code) avoid
worrying about the locations of instructions and data. Label processing requires making
two passes through the assembly source code as follows:
1. The first pass scans the code to determine the address of each label.
2. The second pass assembles the instructions using the label values computed in the first
pass.
The name of each symbol and its address is stored in a symbol tablethat is built during the
first pass. The symbol table is built by scanning from the first instruction to thelast.
During scanning, the current location in memory is kept in a program location counter (PLC).
Despite the similarity in name to a program counter, the PLC is not used to execute the
program, only to assign memory locations to labels.
The simplest case is absolute addressing. In this case, one of the first statements in the
assembly language program is a pseudo-op that specifies the origin of the program, that is,
the location of the first address in the program. A common name for this pseudo-op (e.g., the
one used for the ARM) is the ORG statement.
ORG 2000
Which puts the start of the program at location 2000. This pseudo-op accomplishes this by
setting the PLC’s value to its argument’s value, 2000 in this case. Assemblers generally allow
a program to have many ORG statements in case instructions or data must be spread around
various spots in memory.
Linking
• Many assembly language programs are written as several smaller pieces rather than as a
single large file. Breaking a large program into smaller files helps delineate program
modularity. If the program uses library routines, those will already be preassembled, and
assembly language source code for the libraries may not be available for purchase.

• A linker allows a program to be stitched together out of several smaller pieces. The linker
operates on the object files created by the assembler and modifies the assembled code to
make the necessary links between files.
• Some labels will be both defined and used in the same file. Other labels will be defined in a
single file but used elsewhere as illustrated in Figure 2.18. The place in the file where a label
is defined is known as an entry point. The place in the file where the label is used is called an
external reference.
• The main job of the loader is to resolve external references based on available entry points.
As a result of the need to know how definitions and references connect, the assembler passes
to the linker not only the object file but also the symbol table.
• Even if the entire symbol table is not kept for later debugging purposes, it must at least pass
the entry points. External references are identified in the object code by their relative
symbol identifiers.
• The linker proceeds in two phases.
oFirst, it determines the address of the start of each object file. The order in which object files
are to be loaded is given by the user, either by specifying parameters when the loader is run
or by creating a load map file that gives the order in which files are to be placed in memory.
Given the order in which files are to be placed in memory and the length of each object file, it
is easy to compute the starting address of each file.
oAt the start of the second phase, the loader merges all symbol tables from the object files
into a single, large table. It then edits the object files to change relative addresses into
addresses. This is typically performed by having the assembler write extra bits into the object
file to identify the instructions and fields that refer to labels. If a label cannot be found in the
merged symbol table, it is undefined and an error message is sent to the user.
9.(ii) Discuss about the structural units in embedded processor and how a processor is
selected for an embedded application. (MAY 2016) (DEC 2016)
Structural units in Embedded Processor:
Processors is an important unit of an Embedded System
Processors in an Embedded System:
Processors has two essential units:
1. Program Flow Control Unit (CU) – Fetch Unit for fetching instruction.
2. Execution unit (EU) – data transfer operation and data conversion.
EU includes the ALU and also the circuit that executes instruction for program
control task, halt, interrupt,jump instruction.
Processor selection for an embedded system

With numerous kinds of processors with various design philosophies available at our disposal
for using in our design, following considerations need to be factored during processor selec-
tion for an embedded system.
 Performance Considerations
 Power considerations
 Peripheral Set
 Operating Voltage
 Specialized Processing Units
Now let us discuss each of them in detail.
Performance considerations
The first and foremost consideration in selecting the processor is its performance. The per-
formance speed of a processor is dependent primarily on its architecture and its silicon
design. Evolution of fabrication techniques helped packing more transistors in same area
there by reducing the propagation delay. Also presence of cache reduces instruction/data
fetch timing. Pipelining and super-scalar architectures further improves the performance of
the processor. Branch prediction, speculative execution etc are some other techniques used
for improving the execution rate. Multi-cores are the new direction in improving the perform-
ance.
Rather than simply stating the clock frequency of the processor which has limited signific-
ance to its processing power, it makes more sense to describe the capability in a standard
notation. MIPS (Million Instructions Per Second) or MIPS/MHz was an earlier notation fol-
lowed by Dhrystones and latest EEMBC’s CoreMark. CoreMark is one of the best ways to
compare the performance of various processors.
Processor architectures with support for extra instruction can help improving performance for
specific applications. For example, SIMD (Single Instruction/Multiple Data) set and Jazelle –
Java acceleration can help in improving multimedia and JVM execution speeds.
So size of cache, processor architecture, instruction set etc has to be taken in to account when
comparing the performance.
Power Considerations
Increasing the logic density and clock speed has adverse impact on power requirement of the
processor. A higher clock implies faster charge and discharge cycles leading to more power
consumption. More logic leads to higher power density there by making the heat dissipation
difficult. Further with more emphasis on greener technologies and many systems becoming
battery operated, it is important the design is for optimal power usage.
Techniques like frequency scaling – reducing the clock frequency of the processor depending
on the load, voltage scaling – varying the voltage based on load can help in achieving lower
power usage. Further asymmetric multiprocessors, under near idle conditions, can effectively
power off the more powerful core and load the less powerful core for performing the tasks.
SoC comes with advanced power gating techniques that can shut down clocks and power to
unused modules.
Peripheral Set
Every system design needs, apart from the processor, many other peripherals for input and
output operations. Since in an embedded system, almost all the processors used are SoCs, it
is better if the necessary peripherals are available in the chip itself. This offers various bene-
fits compared to peripherals in external IC’s such as optimal power architecture, effective
data communication using DMA, lower BoM etc. So it is important to have peripheral set in
consideration when selecting the processor.

Operating Voltages
Each and every processor will have its own operating voltage condition. The operating
voltage maximum and minimum ratings will be provided in the respective data sheet or user
manual.
While higher end processors typically operate with 2 to 5 voltages including 1.8V for
Cores/Analogue domains, 3.3V for IO lines, needs specialized PMIC devices, it is a deciding
factor in low end micro-controllers based on the input voltage. For example it is cheaper to
work with a 5V micro-controller when the input supply is 5V and a 3.3 micro-controllers
when operated with Li-on batteries.
Specialized Processing
Apart from the core, presence of various co-processors and specialized processing units can
help achieving necessary processing performance. Co-processors execute the instructions
fetched by the primary processor thereby reducing the load on the primary. Some of the pop-
ular co-processors include
 Floating Point Co-processor:
RISC cores supports primarily integer only instruction set. Hence presence of a FP co-pro-
cessor can be very helpful in application involving complex mathematical operations includ-
ing multimedia, imaging, codecs, signal processing etc.
 Graphic Processing Unit:
GPU(Graphic Processing Unit) also called as Visual processing unit is responsible for draw-
ing images on the frame buffer memory to be displayed. Since human visual perception
needed at-least 16 Frames per second for a smooth viewing, drawing for HD displays in-
volves a lot of data bandwidth. Also with increasing graphic requirements such as textures,
lighting shaders etc, GPU’s have become a mandatory requirements for mobile phones, gam-
ing consoles etc.
Various GPU’s like ARM’s MALI, PowerVX, OpenGL etc are increasing available in higher
end processors. Choosing the right co-processor can enable smooth design of the embedded
application.
Digital Signal Processors

DSP is a processor designed specifically for signal processing applications. Its architecture
supports processing of multiple data in parallel. It can manipulate real time signal and convert
to other domains for processing. DSP’s are either available as the part of the SoC or separate
in an external package. DSP’s are very helpful in multimedia applications. It is possible to
use a DSP along with a processor or use the DSP as the main processor itself.
Price
Various considerations discussed above can be taken in to account when a processor is being
selected for an embedded design. It is better to have some extra buffer in processing capacit-
ies to enable enhancements in functionality without going for a major change in the design.
While engineers (especially software/firmware engineers) will want to have all the function-
alities, price will be the determining factor when designing the system and choosing the right
processor.
10. With a neat diagram, explain the working of Direct Access(DMA) and mention the
memory management methods.(MAY 2016) (MAY 2015) (DEC 2014) (DEC 2016)
A DMA controller is a device, usually peripheral to a CPU that is programmed to
perform a sequence of data transfers on behalf of the CPU. A DMA controller can directly
access memory and is used to transfer data from one memory location to another, or from an
I/O device to memory and vice versa. A DMA controller manages several DMA channels,
each of which can be programmed to perform a sequence of these DMA transfers. Devices,
usually I/O peripherals, that acquire data that must be read (or devices that must output data
and be written to) signal the DMA controller to perform a DMA transfer by asserting a
hardware DMA request (DRQ) signal. A DMA request signal for each channel is routed to
the DMA controller. This signal is monitored and responded to in much the same way that a
processor handles interrupts. When the DMA controller sees a DMA request, it responds by
performing one or many data transfers from that I/O device into system memory or vice
versa. Channels must be enabled by the processor for the DMA controller to respond to DMA
requests. The number of transfers performed, transfer modes used, and memory locations
accessed depends on how the DMA channel is programmed. A DMA controller typically
shares the system memory and I/O bus with the CPU and has both bus master and slave
capability. Fig.16.1 shows the DMA controller architecture and how the DMA controller
interacts with the CPU. In bus master mode, the DMA controller acquires the system bus
(address, data, and control lines) from the CPU to perform the DMA transfers. Because the
CPU releases the system bus for the duration of the transfer, the process is sometimes
referred to as cycle stealing.
In bus slave mode, the DMA controller is accessed by the CPU, which programs the
DMA controller's internal registers to set up DMA transfers. The internal registers consist of
source and destination address registers and transfer count registers for each DMA channel,
as well as control and status registers for initiating, monitoring, and sustaining the operation
of the DMA controller.
Memory allocation
 When a process is created, the memory manager allocates the memory addresses
(blocks) to it by mapping the processaddress space.
 Threads of a process share the memory space of the process
 Memory Management after Initial Allocation
 Memory manager of the OS─ secure, robust and well protected.
 No memory leaks and stack overflows
 Memory leaks means attempts to write in the memory block not allocated to a process
or data structure.
 Stack overflow means that the stack exceeding the allocated memory block(s)
Memory Managing Strategy for a system
 Fixed-blocks allocation
 Dynamic -blocks Allocation
 Dynamic Page-Allocation
 Dynamic Data memory Allocation
Memory Managing Strategy for a system
 Dynamic address-relocation
 Multiprocessor Memory Allocation
 Memory Protection to OS functions
Memory allocation in RTOSes
RTOS may disable the support to the dynamic block allocation, MMU support to dynamic
page allocation and dynamic binding as this increases the latency of servicing the tasks and
ISRs.
RTOS may not support to memory protection of the OS functions, as this increases the
latency of servicing the tasks and ISRs. User functions are then can run in kernel space and
run like kernel functions
RTOS may provide for disabling of the support to memory protection among the tasks as this
increases the memory requirement for each task
11.Discuss about
i) in-circuit emulator & Watch dog Timer (May 2017) (May 2018)
ii) Target Debugging.
IN CIRCUIT EMULATOR
Embedded systems tend to lack a display, keyboard, and mouse with which to manipulate the
microcontroller that you’re trying to program. So a host computer is used for this function,
and typically communicates over a serial cable or more recently, Wi-Fi.
Once you create, edit, and compile code for your embedded system on a host computer, you
will have executable (object) code that needs to be uploaded to the microcontroller in your
embedded system. There, you can see the code in action, test it, and debug the code by
making changes to the code on the host, recompiling, and running it again on the target
MCU. But what if you want to alter the contents of a register, memory, or the state of your
I/O to see what happens? An In-circuit emulator (ICE) is a debugging tool that allows you to
access a target MCU for in-depth debugging. A genuine ICE requires you to remove the
microcontroller and to insert the ICE in its place, most commonly using an adapter. In-circuit
emulation is rather rare in these days of high-performance, relatively low-cost processors
because ICE needs to be invisible to the system, which is difficult to do with extremely fast,
memory-intensive chips. Nevertheless, not every system requires a high-performance MCU,
and it’s still possible to use ICE. ICE is the best tool for finding difficult bugs and can
provide invaluable insight.
ICE consists of a hardware board with accompanying software for the host computer.
The ICE is physically connected between the host computer and the target MCU. The
debugger on the host establishes a connection to the MCU via the ICE. ICE allows a
developer to see data and signals that are internal to the MCU, and to step through the source
code (e.g., C/C++ on the host) or set breakpoints; the immediate ramifications of executed
software are observed during run time. Since the debugging is done via hardware, not
software, the MCU’s performance is left intact for the most part, and ICE does not
compromise MCU resources. This type of debugging is also referred to as source-level or
run-time debugging, except ICE is as close to the real scenario as possible, as it’s not a
simulation but a substitution of the target MCU with an emulation, or accurate mirror, of the
target MCU in the ICE itself. The behavior of the MCU will be more accurately reflected in
ICE, and in real-time.
The disadvantage of ICE debugging is that the ICE hardware must be physically connected to
the MCU. As chips get smaller, adapters can help in connecting tiny surface mounted chips to
the ICE. Another disadvantage is that ICE devices come with a learning curve, especially if
there will be complex debugging functions, for example, flagging when a register holds a
specific value after a conditional branch is taken, etc. And last, disadvantage is that as high-
performance chips have come down in price, the accessibility for debugging with ICE has
faded to the point where ICE hardware has become rare for anyone who is not still using an
8051-era MCU. In-circuit emulators require fast connectivity and loads of memory, so lower
level MCUs (8-, -16-bit and MHz, not GHz) are more likely to have an ICE option available.
Furthermore, highly integrated chips may create fewer bugs versus off-chip, board-mounted
EEPROMS and interfaces.
WATCH DOG TIMER

Watch dog timer is a device that can be set for a present interval, and an event error must
occur during that interval else the device will generate the time out signal .For example, we
anticipate that a set of tasks must finish within 100ms.The watch dog timer disables and stops
in case the tasks finish within 100ms. The watch dog timer generates the interrupts after
100ms and executes a routine that runs because the tasks failed to finish in the anticipated
interval. A software task can also be programmed as a watchdog timer.

The watchdog timer has a number of applications. One application in a mobile phone is that
the display is turned off in case no GUI interaction takes place with specified time. The
interval is usually set at 15, 20 , 25 , or 30 s in a mobile phone. This saves power.
Another application in a mobile phone is that if a given menu is not selected by a click within
a pre-set time interval, another menu can be presented or a beep can be generated to invite
user’s attention.
An application in a temperature controller is that if a controller takes no action to switch off
the current within the pre-set time, the current is switched off and a warning signal raised,
indicating controller failure. Failure to switch off current may cause a boiler in which water is
heated to burst.
• Example: checking the stack depth, number of buffers allocated and the state of me-
chanical components in the system before resetting the watchdog timer.
• A flag should be set at various points in the code indicating the successful completion
of that block of code.
• Before the timer is reset, all flags are checked, if all the flags have been set, the timer
can be retriggered for another interval.
• If not, the failure mode is recorded and the timer is allowed to time out.

TARGET HARDWARE DEBUGGING:

Even though the firmware is bug free and everything is intact in the board, your embedded
product need not function as per the expected behaviour in the first attempt for various
hardware related reasons like dry soldering of components, missing connections in the PCB
due to any un-noticed errors in the PCB layout design, misplaced components, signal
corruption due to noise, etc. The only way to sort out these issues and figure out the real
problem creator is debugging the target board. Hardware debugging is not similar to firmware
debugging. Hardware debugging involves the monitoring of various signals of the target
board (address/data lines, port pins, etc.), checking the inter connection among various
components, circuit continuity checking, tec. The various hardware debugging tools used in
Embedded Product Development are explained below.
MAGNIFYING GLASS (Lens):
You might have noticed watch repairer wearing a small magnifying glass while engaged in
repairing a watch. They use the magnifying glass to view the minute components inside the
watch in an enlarged manner so that they can easily work with them. Similar to a watch
repairer, magnifying glasses are the primary hardware debugging tool for an embedded
hardware debugging professional. A magnifying glass is a powerful visual inspection tool.
With a magnifying glass(lens), the surface of the target board can be examined thoroughly for
dry soldering of components, missing components, improper placement of components,
improper soldering, track(PCB connection)damage, short of tracks, etc. Nowadays high
quality magnifying stations are available for visual inspection. The magnifying station
incorporates magnifying glasses attached to a stand with CFL tubes for providing proper
illumination for inspection tool for the entire hardware board whereas the other small lens
within the station is used for magnifying a relatively small area of the board which requires
thorough inspection.
MULTIMETER:
I believe the name of the instrument itself is sufficient to give an outline of its usage. A
multimeter is used for measuring various electrical quantities like voltage(both AC and DC),
current(DC as well as AC), resistance, capacitance, continuity checking, transistor checking,
cathode and anode identification of diode, etc. Any multimeter will work over a specific
range for each measurement. A multimeter is the most valuable tool in the toolkit of an
embedded hardware developer. It is the primary debugging tool for physical contact based
hardware debugging and almost all the developers start debugging the hardware with it. In
embedded hardware debugging it is mainly used for checking the circuit continuity between
different points on the board, measuring the supply voltage, checking the signal value,
polarity, etc. Both analog and digital versions of a multimeter are available. The digital
version is preferred over the analog one for various reasons like readability, accuracy, etc.
Fluke, Rishab, Philips, etc. are the manufacturers of commonly available high quality digital
multimeters.
DIGITAL CRO:
Cathode Ray Oscilloscope (CRO) is a little more sophisticated tool compared to a
multimeter. You might have studied the operation and use of a CRO in your basic electronics
lab. CRO is used for waveform capturing and analysis, measurement of signal strength, etc.
By connecting the point under observation on the target board to the channels of the
oscilloscope, the waveforms can be captured and analysed for expected behaviour. CRO is a
very good tool in analysing interference noise in the power supply line and other signal lines.
Monitoring the crystal oscillator signal from the target board is a typical example of the usage
of the CRO for the waveform capturing and analysis in target board debugging. CROs are
available in both analog and digital versions. Though digital CROs are costly, featurewise
they are best suited for target board debugging applications. Digital CROs are available for
high frequency support and they also incorporate modern techniques for recording waveform
over a period of time, capturing waves on the basis of a configurable event(trigger) from the
target board(e.g. High to low transition of a port pin of the target processor). Most of the
modern digital CROs contain more than one channel and is easy to capture and analyse
various signals from the target board using multiple channels simultaneously. Various
measurements like phase, amplitude, etc. is also possible with CROs. Tektronix, Agilent,
Philips, tec. Are the manufacturers of high precision good quality digital CROs.
LOGIC ANALYSER:
A logic analyser is the big brother of digital CRO. Logic analyser is used for capturing digital
data(logic 1 or 0) from a digital circuitry whereas CRO is employed in capturing all kinds of
waves including logic signals. Another major limitation of CRO is that the total number of
logic signals/waveforms that can be captured with a CRO is limited by the number of
channels. A logic analyser contains special connectors and clips which can be attached to the
target board for capturing digital data. In target board debugging applications, a logic
analyser captures the states of various port pins, address bus and data bus of the target
processor/controller, etc. Logic analysers give an exact reflection of what happens when a
particular line of firmware is running. This is achieved by capturing the address line logic and
data line logic of the target hardware. Most modern logic analysers contain provisions for
storing captured data, selecting a desired region of the captured waveform, zooming selected
region of the captured waveform, etc. Tektronix, Agilent, etc. in the logic analyser market.
FUNCTION GENERATOR:
Function generator is not debugging tool. It is an input signal simulator tool. A function
generator is capable of producing various periodic waveforms like sine wave, square wave,
saw-tooth wave, etc. with different frequencies and amplitude. Sometimes the target board
may require some kind of periodic waveform with a particular frequency as input to some
part of the board. Thus, in debugging environment, the function generator serves the purpose
of generating and supplying required signals.
12. Discuss in detail about selection of processor and memory devices for an embedded
system application.
Refer question no. 9.(ii) for answer
13. Explain in detail the working principle of incircuit Emulator. (MAY2018)
Refer question no. 11.(i) for answer
Part B (C402.2)
1. i)Explain the features of RS232C and RS485 and give some differences between
them. (MAY2018)
RS-232 SERIAL INTERFACE
RS232 was first introduced in 1962, This is the most common type of serial interface, it was
the standard communication before the PS2 and USB become popular in the computer
industry, you connect a mouse, modem, and printer to RS-232 serial interface. RS232 only
allows for one transmitter and one receiver on each line. RS232 also use a Full-Duplex
transmission method. RS232 can transmit up to 1Mbps with maximum distance up to 50 ft.

RS-422 SERIAL INTERFACE
RS422 is an improved version of RS232, it uses twisted pair cable to reduce the noise, and it
uses signaling balancing to transmit data, so what is signal balanced – It uses a voltage-
difference between the two lines as an indication of the signal value, with this method the
data is able to transmit for longer distance with faster data rates, with RS422 the data can
transmit up to 10 Mpbs at 50 feet or 100 Kbps at 4000 feet. RS422 is capable of multi-drop
capability, it limits up to 10 slaves in the data line.
RS485 SERIAL INTERFACE

RS485 is an improved version of RS422, it expands on the capabilities, the major change is to
have multi-drop Limitation of RS422, it allows up to 32 devices to communicate through the
same data line. Any of the slave devices on an RS-485 bus can communicate with all the
slave within the data line without going through the master device.
RS-422
RS-232
RS-485
Cabling Single ended Single ended multi-drop Multi-drop
No. of Devices 1 transmitter 1 transmitter 32

1 receiver 10 receivers transmitters
32 receivers
Communication Full duplex Full duplex, Full duplex,

Mode Half duplex Half duplex
Max Distance 50 feet at 19.2 4000 feet at 100 kbps 4000 feet at
kbps 100 kbps

RS-422
RS-232
RS-485
Max Data Rate 1 mbps for 50 10 mbps for 50 feet 10 mbps for
feet 50 feet
ii)How to transfer a byte of data using I2C protocol?

The I2C (Inter Integrated Circuit) bus, developed by Philips Semiconductors, provides a
three-wire bi-directional interface between multiple devices. I2C uses two lines, one for
synchronization clock (SCL) and one for data and acknowledgement (SDA). The BUS
MASTER is the chip issuing the commands on the BUS. The IC that initiates a data transfer
on the bus is considered the BUS MASTER and all the others are regarded as the bus slaves.
The IC bus is a Multi-MASTER BUS. More than one IC capable of initiating data transfer
can be connected to it. I2C bus transfers consist of a number of bytes framed by a start
condition and a stop condition. When bus transfers are not taking place, both SDA and SCL
float high. The transmitter indicates the start condition by generating a falling edge of SDA
followed by the falling edge of SCL within the same clock cycle. The end of a data transfer
generates a rising edge of SCL followed by the rising edge of SDA within the same clock
cycle. The receivers keep monitoring these two lines. Once the transfer starts, eight data bits
are sent according to the clock cycles. In the ninth clock cycle, the receiver indicates the
success of data transfer by raising SDA high; otherwise, SDA is low. Multiple bytes can be
sent by repeating this 9-clock cycle. The transmitter indicates the end of transmission by
generating the rising edge of SCL followed by the rising edge of SDA within the same clock
cycle. The first byte on SDA after the start is the control byte. The left seven bits of a control
byte indicate the destination address (devices). The rightmost bits of the control byte
indicates the data transfer is write (sent) or read (receive).
2. Explain in detail the function of any one serial communication protocol using I 2C bus.
(Dec 2017) (DEC 2014)
2
The I C Bus:
2
• TheI Cbus[Phi92]isawell-knownbuscommonlyusedtolinkmicrocontrollersinto
systems. IthasevenbeenusedforthecommandinterfaceinanMPEG-2 videochip[van97];whilea
separatebuswasusedforhigh-speedvideo data,setupinformation wastransmittedtotheon-
2
chipcontrollerthroughanI Cbusinterface.
2
•I Cisdesignedtobelowcost,easytoimplement,andofmoderatespeed(upto100KB/sfor
thestandardbusandupto400KB/sfortheextendedbus).Asaresult,itusesonlytwolines
theserialdataline(SDL)fordataandtheserialclockline(SCL), whichindicateswhenvalid data
2
areonthedataline.Figure4.6showsthestructureofatypicalI Cbussystem.
•
Every nodeinthenetworkisconnectedtobothSCLandSDL.Somenodesmaybeabletoact
asbusmastersandthebusmay havemorethanonemaster.Othernodesmay actasslavesthat
onlyrespondtorequests frommasters.
• The basic electrical interface to the bus is shown in Figure 4.7.Thebus does not define
particular voltagestobeusedforhighorlowsothateitherbipolarorMOScircuitscanbe
connectedtothebus.
•Bothbussignalsuseopencollector/opendraincircuits.1Apull-upresistorkeepsthedefault
stateofthesignalhigh,andtransistorsareusedineachbusdevicetopulldownthesignalwhen a0is
tobetransmitted.
• The
Opencollector/opendrainsignalingallowsseveraldevicestosimultaneouslywritethebus
withoutcausingelectricaldamage.The opencollector/opendraincircuitryallowsaslavedevice
tostretchaclocksignalduring areadfromaslave.Themasterisresponsibleforgeneratingthe SCL
clock,buttheslavecanstretchthelowperiodoftheclock(butnotthehighperiod)if necessary.
• TheI2Cinterfaceonamicrocontrollercanbeimplementedwithvaryingpercentagesofthe
functionalityinsoftware andhardware[Phi89]. AsillustratedinFigure4.8,atypicalsystem has
a1-bithardwareinterfacewithroutinesforbyte level functions.
2
• TheI Cdevicetakescareofgeneratingtheclockanddata.Theapplicationcodecallsroutines
tosendanaddress,sendadatabyte,andsoon,whichthengeneratestheSCL andSDL,
acknowledges,andsoforth.
 I2C signaling
o Sender pulls down bus for 0.
o Sender listens to bus---if it tried to send a 1 and heard a 0, someone else is si-
multaneously transmitting.
o Transmissions occur in 8-bit bytes.
 I C data link layer
2

o Every device has an address (7 bits in standard, 10 bits in extension).
o Bit 8 of address signals read or write.
o General call address allows broadcast.
 I C bus arbitration
2
o Sender listens while sending address.

o When sender hears a conflict, if its address is higher, it stops signaling.
o Low-priority senders relinquish control early enough in clock cycle to allow
bit to be transmitted reliably.
•
Oneofthemicrocontroller’stimersistypicallyusedtocontrolthelengthofbitsonthebus.
Interruptsmaybeusedtorecognizebits.However,whenusedinmastermode,polledI/Omay
beacceptableifnootherpending taskscanbeperformed,sincemastersinitiatetheirown transfers.
3 i)Draw the CAN data frame format and explain the bus arbitration process in CAN
protocol.
The CAN data link layer comprises two protocols: Classical CAN introduced in 1986 and
implemented for the first time in 1988 and CAN FD launched in 2012 and internationally
standardized in 2015 in ISO 11898-1. For a transitional period there are also non-ISO
compliant implementations on the market. They are application-transparent, meaning they
can be used for software development and designing prototype networks. However, CiA
doesn’t recommend using them for serial production.
The two CAN data link layer protocols have some common features. Any node has the right
to request transmission rights at any time. The necessary bus arbitration method to avoid
transmission conflicts is the same: Frames with the highest assigned identifier get bus access
without delay. All frame types (data, remote, error, and overload frame) are transmitted in
broadcast. The data frame structure comprising several fields is the same.
One of the unique features of the CAN data link layers is that all single-bit errors are detec-
ted. Multi-bit errors are detected with a high probability. In order to provide data consistency
in all nodes, local errors are globalized. Additionally, the fault confinement implemented in
the CAN data link layers precludes a single node from corrupting the communication of the
others permanently.

The Classical CAN protocol uses just one bit-rate in the arbitration and the data phase. The
transmission speed is limited to 1 Mbit/s for short networks (theoretically up to 40 m). How-
ever the achievable bit-rate depends on the network length and the used physical layer ele-
ments such as cable, connector, and transceiver. The payload, the data field, is limited to 8
byte.
The CAN FD protocol allows payloads up to 64 byte. Additionally, it supports an optional

second bit-rate for the data-phase. The limitation of the speed in the arbitration phase is the
same as for Classical CAN. In the data phase, the speed is limited by transceiver character-
istic, the oscillator tolerance, and the topology (ringing). Data phase bit rates up to 8 Mbit/s
are realistic when using a bus-line topology with very short, not terminated stubs.
(ii) Explain in detail about the I/O devices used in embedded systems. (MAY2018)
Input and Output Devices
Input and output devices allow the computer system to interact with the outside world by
moving data into and out of the system. An input device is used to bring data into the system.
Some input devices are:
 Keyboard
 Mouse
 Microphone
 Bar code reader
 Graphics tablet
An output device is used to send data out of the system. Some output devices are:
 Monitor
 Printer
 Speaker
Input/output devices are usually called I/O devices. They are directly connected to an
electronic module inside the systems unit called a device controller. For example, the
speakers of a multimedia computer system are directly connected to a device controller called
an audio card (such as a Soundblaster), which in turn is connected to the rest of the system.
Sometimes secondary memory devices like the hard disk are called I/O devices (because they
move data in and out of main memory.) What counts as an I/O device depends on context. To
a user, an I/O device is something outside of the system box. To a programmer, everything
outside of the processor and main memory looks like an I/O devices. To an engineer working
on the design of a processor, everything outside of the processor is an I/O device.
A computer that is dedicated to running a program that controls another device is
an embedded system. An embedded system is usually embedded inside the device it controls.
Usually they run just one program that is permanently kept in a special kind of main memory
called ROM (for Read Only Memory). More processor chips are sold per year for embedded
systems than for all other purposes.
4 Explain the CAN architecture with neat diagram. (Dec 2017) (Dec 2014)
TheControllerAreaNetwork(CAN)buswasdevelopedforautomotiveelectronics.Itprovides
megabitratesandcanhandlelargenumbersofdevices.
Ethernetandvariations ofstandardEthernetareusedforavarietyofcontrolapplications
CAN bus
 First used in 1991. Serial bus, 1 Mb/sec up to 40 m. Synchronous bus.
Logic 0 dominates logic 1 on bus. Arbitrated with CSMA/AMP:
Arbitration on message priority.

CAN Data Frame

 11 bit destination address.
 RTR bit determines read/write from/to destination.
 Any node can detect bus error, interrupt packet for retransmission.
CAN Controller
 Controller implements physical and data link layers.
 No network layer needed---bus provides end-to-end connections.
5. Give the advantages and disadvantages of using serial communication devices and
parallel communication devices. (MAY2018)
There are two ways to transfer data between computers: Serial Transmission and Parallel
Transmission.
Serial Transmission

Data is sent bit by bit from one computer to another in two directions. Each bit has a clock
pulse rate. Eight bits are transmitted at a time with a start and stop bit known as a parity bit,
which is 0 and 1 respectively. Data cables are used when transmitting data to a longer
distance. The data cable has D-shaped 9 pin cable that connects the data in series.
Categories of Serial Transmission
Asynchronous transmission – an extra bit is added to each byte to alert the receiver on the
arrival of new data. 0 is used as a start bit while 1 used as a stop bit.Synchronous
transmission – no extra bit is added to each byte. Data is transferred in batches which
contains multiple bytes.
Parallel Transmission
Several bits are transmitted together simultaneously with one clock pulse rate. It transmits
quickly as it utilizes several input and output lines for sending the data.It uses a 25-pin port
with 17 signal lines and 8 ground lines. The 17 signal lines are divided as
 4 lines – initiates handshaking
 5 lines – communicates and notifies errors
 8 lines – transfers data
Applications
Serial transmission occurs between two computers or from a computer to an external device
located some distance away. Parallel transmission can take place within a computer system,
through a computer bus or to an external device located a close distance away.
Examples
An example of serial mode transmission include connection between a computer and a
modem using the RS-232 protocol. An RS-232 cable can accommodate 25 wires, but only
two of these wires are for data transmission, the rest are for overhead control signaling. The
two data wires run on simple serial transmission in either direction.In this example, a
computer may be far from the modem, making parallel transmission very expensive. With
this, speed of transmission is considered less important compared to the economic advantage
of serial transmission.
An example of parallel mode transmission include connection between a computer and a
printer. Most printers are within 6 meters or 20 feet from the transmitting computer and the
slight cost for extra wires is offset by the added speed gained through parallel transmission of
data.
Comparison between Serial and Parallel Transmission

Basis for Comparison Serial Transmission Parallel Transmission
Data flows in 2 directions, Data flows in multiple directions, 8
Definition
bit by bit bits (1 byte) at a time
Cost Economical Expensive
Number of bits transferred
1 bit 8 bits or 1 byte
per clock pulse
Speed Slow Fast
Used for long distance Used for short distance
Applications
communication communication
Example Computer to computer Computer to printer
Differences between Serial and Parallel Transmission
 Serial transmission requires a single line to send data. Parallel transmission requires
multiple lines to send data.

 There are less errors and noise in serial transmission since transmission is done one
bit at a time. There are more errors and noise in parallel transmission since
transmission is done multiple bits at a time.
 Serial transmission is slower since data flows through a single line. Parallel
transmission is faster since data flows through multiple lines.
 Serial transmission is full duplex since the sender can send and receive data. Parallel
transmission is half duplex since the data can be sent or received at a time.
 The cables used in serial transmission are thinner, longer and economical as compared
to the cables used in parallel transmission.
 Serial transmission is reliable and straightforward. Parallel transmission is unreliable
and complicated.
Both serial and parallel transmissions have advantages and disadvantages. Parallel
transmission is used for shorter distance and provides greater speed. While, serial
transmission is reliable for transferring data to longer distance. Both serial and parallel
transmissions are individually essential for transferring data.
6. Explain about the Input/ Output Devices and uses of UART and HDLC and explain how
data is transferred using PCI/X. List the major features. (DEC 2014
7.i)Describe the various components of synchronous serial input and output ports.
(Nov/Dec-2013)


7. (ii) Explain the function of embedded processor architecture and I/O devices
CPU BUSES
A computer system encompasses much more than the CPU it also includes memory and I/O
devices. The bus is the mechanism by which the CPU communicates with memory and
devices. A bus is, at a minimum, a collection of wires, but the bus also defines a protocol by
which the CPU, memory, and devices communicate. One of the major roles of the bus is to
provide an interface to memory. (Of course, I/O devices also connect to the bus.)
Clock provides synchronization to the bus components,

R/W is true when the bus is reading and false when the bus is writing,
Address is an a-bit bundle of signals that transmits the address for an access,
Data is an n-bit bundle of signals that can carry data to or from the CPU, and Data ready
signals when the values on the data bundle are valid.
Bus Protocols:
The basic building block of most bus protocols is the four-cycle handshake,
illustrated in Figure. The handshake ensures that when two devices want to communicate,
one is ready to transmit and the other is ready to receive.The handshake uses a pair of wires
dedicated to the handshake: enq (meaning enquiry) and ack (meaning acknowledge). Extra
wires are used for the data transmitted during the handshake. The four cycles are described
below.

1. Device 1 raises its output to signal an enquiry, which tells device 2 that it should get ready
to listen for data.
2. When device 2 is ready to receive, it raises its output to signal an acknowledgment. At this
point,devices 1 and 2 can transmit or receive.
3. Once the data transfer is complete, device 2 lowers its output, signaling that it has
received the data.
4. After seeing that ack has been released, device 1 lowers its output.
At the end of the handshake, both handshaking signals are low, just as they were at the start
of the handshake. The system has thus returned to its original state in readiness for another
handshake- enabled data transfer.Microprocessor buses build on the handshake for
communication between the CPU and other system components. The term bus is used in two
ways.The most basic use is as a set of related wires, such as address wires. However, the
term may also mean a protocol for communicating between components.To avoid confusion,
we will use the term bundle to refer to a set of related signals. The fundamental bus
operations are reading and writing.
8. Explain in detail about SPI communication protocol and its interfacing techniques.
(MAY 2016).
SPI is a common communication protocol used by many different modules. For example, SD
card modules, RFID card reader modules, and 2.4 GHz wireless transmitter/receivers all use
SPI to communicate with the microcontroller.One unique benefit of SPI is the fact that data
can be transferred without interruption. Any number of bits can be sent or received in
a continuous stream. With I2C and UART, data is sent in packets, limited to a specific
number of bits. Start and stop conditions define the beginning and end of each packet, so the
data is interrupted during transmission.
Devices communicating via SPI are in a master-slave relationship. The master is the
controlling device (usually a microcontroller), while the slave (usually a sensor, display, or
memory chip) takes instruction from the master. The simplest configuration of SPI is a single
master, single slave system, but one master can control more than one slave (more on this
below).

Advantages and Disadvantages of SPI
There are some advantages and disadvantages to using SPI, and if given the choice between
different communication protocols, you should know when to use SPI according to the
requirements of your project :
Advantages
o No start and stop bits, so the data can be streamed continuously without interruption
o No complicated slave addressing system like I2C
o Higher data transfer rate than I2C (almost twice as fast)
o Separate MISO and MOSI lines, so data can be sent and received at the same time
Disadvantages
o Uses four wires (I2C and UARTs use two)
o No acknowledgement that the data has been successfully received (I2C has this)
o No form of error checking like the parity bit in UART
o Only allows for a single master
9. Write short notes on:

i) RS 232 standard(May 2017)
The processing element at the port (peripheral) send the byte through a shift register at the
port to which the microprocessor writes the byte. RS-232 (ANSI/EIA-232 Standard) is the
serial connection historically found on IBM-compatible PCs. It is used for many purposes,
such as connecting a mouse, printer, or modem, as well as industrial instrumentation.
Because of improvements in line drivers and cables, applications often increase the
performance of RS-232 beyond the distance and speed listed in the standard. RS-232 is
limited to point-to-point connections between PC serial ports and devices. RS-232 hardware
can be used for serial communication up to distances of 50 feet.
Data
TXD (pin 3) Serial Data Output
RXD (pin 2) Serial Data Input
Handshake
RTS (pin 7) Request to Send
CTS (pin 8) Clear to Send
DSR (pin 6) Data Set Ready
DCD (pin 1) Data Carrier Detect
DTR (pin 4) Data Terminal Ready
Ground

GND (pin 5) Ground
Other
RI (pin 9) Ring Indicator
Table 1: Pin Functions for RS-232

RS-422
RS-422 (EIA RS-422-A Standard) is the serial connection historically used on Apple Macintosh com -
puters. RS-422 uses a differential electrical signal, as opposed to unbalanced signals referenced to
ground with the RS-232. Differential transmission uses two lines each for transmit and receive signals
which results in greater noise immunity and longer distances as compared to the RS-232. These ad-
vantages make RS-422 a better fit for industrial applications.
RS-485
RS-485 (EIA-485 Standard) is an improvement over RS-422, because it increases the number of
devices from 10 to 32 and defines the electrical characteristics necessary to ensure adequate signal
voltages under maximum load. With this enhanced multi-drop capability, you can create networks of
devices connected to a single RS-485 serial port. The noise immunity and multi-drop capability make
RS-485 the serial connection of choice in industrial applications requiring many distributed devices
networked to a PC or other controller for data collection, HMI, or other operations. RS-485 is a super -
set of RS-422; thus, all RS-422 devices may be controlled by RS-485. RS-485 hardware may be used
for serial communication with up to 4000 feet of cable.
Data
TXD+ (pin 8) Serial Data Output (differential)
TXD- (pin 9) Serial Data Output(differential)
RXD+ (pin 4) Serial Data Input(differential)
RXD- (pin 5) Serial Data Input(differential)
Handshake
RTS+ (pin 3) Request to Send (differential)
RTS- (pin 7) Request to Send (differential)
CTS+ (pin 2) Clear to Send (differential)
CTS- (pin 6) Clear to Send (differential)
DSR (pin 6) Data Set Ready

Ground
GND (pin 1) Ground
Table 2: Pin Functions for RS-485 and RS-422

RS-232, RS-422, and RS-485 Comparison
RS-232 is the most common serial interface and used to ship as a standard component on most Win -
dows-compatible desktop computers. Now it is more common to use RS-232 over USB using a con-
verter. RS-232 only allows for one transmitter and one receiver on each line. RS-232 also uses a Full-
Duplex transmission method. Some RS-232 boards sold by National Instruments support baud rates
up to 1 Mbit/s, but most devices are limited to 115.2 kbits/s.
RS-422 (EIA RS-422-A Standard) is the serial connection used on legacy Apple computers. It
provides a mechanism for transmitting data up to 10 Mbits/s. RS-422 sends each signal using two
wires to increase the maximum baud rate and cable length. RS-422 is also specified for multi-drop ap -
plications where only one transmitter is connected to, and transmits on, a bus of up to 10 receivers.
RS-485 is a superset of RS-422 and expands on the capabilities. RS-485 was made to address the
multi-drop limitation of RS-422, allowing up to 32 devices to communicate through the same data
line. Any of the slave devices on a RS-485 bus can communicate with any other 32 slave devices
without going through a master device. Since RS-422 is a subset of RS-485, all RS-422 devices may
be controlled by RS-485.
Both RS-485 and RS-422 have multi-drop capability, but RS-485 allows up to 32 devices and RS-422
has a limit of 10. For both communication protocols, you should provide your own termination. All
National Instruments RS-485 boards will work with RS-422 standards.
The following table compares mode of operation, total number of drivers and receivers, maximum
cable length, and maximum data rate.
Specifications RS-232 RS-422 RS-485
Mode of Operation Single-Ended Differential Differential
Number of Drivers / 1 Driver 1 Driver 32 Drivers*

Receivers on One Line 1 Receiver 10 Receivers 32 Receivers
Maximum Cable Length 50 ft (2500 pF) 4000 ft 4000 ft
Maximum Data Rate (at 160 kbits/s (can 10 Mbit/s 10 Mbit/s

max cable length) be up to 1Mbit/s)
Table 3: Specifications of RS-232, RS-422, and RS-485

ii) CAN bus
A Controller Area Network (CAN bus) is a robust vehicle bus standard designed to
allow microcontrollers and devices to communicate with each other in applications without
a host computer. It is a message-based protocol, designed originally for multiplex electrical
wiring within automobiles to save on copper, but is also used in many other contexts.
Application
 Passenger vehicles, trucks, buses (gasoline vehicles and electric vehicles)
 Electronic equipment for aviation and navigation
 Industrial automation and mechanical control
 Elevators, escalators
 Building automation
 Medical instruments and equipment.
 The CAN bus protocol has been used on the Shimano DI2 electronic gear shift system
for road bicycles since 2009, and is also used by the Ansmann and BionX systems in
their direct drive motor.
 The CAN bus is also used as a fieldbus in general automation environments, primarily
due to the low cost of some CAN controllers and processors.
 Manufacturers including NISMO aim to use CAN bus data to recreate real-life racing
laps in the videogame Gran Turismo 6using the game's GPS Data Logger function, which
would then allow players to race against real laps.
 Johns Hopkins University's Applied Physics Laboratory's Modular Prosthetic Limb
(MPL) uses a local CAN bus to facilitate communication between servos and microcon-
trollers in the prosthetic arm.
 Teams in the FIRST Robotics Competition widely use CAN bus to communicate be-
tween the roboRIO and other robot control modules.
 The CueScript teleprompter range uses CAN bus protocol over coaxial cable, to con-
nect its CSSC – Desktop Scroll Control to the main unit
10. Explain with all necessary sketches to enable intra communications among
peripherals using I2C bus.(May 2017) (DEC 2016)
TheI2CBus:
• TheI2Cbus[Phi92]isawell-knownbuscommonlyusedtolinkmicrocontrollersinto
systems. IthasevenbeenusedforthecommandinterfaceinanMPEG-2 videochip[van97];whilea
separatebuswasusedforhigh-speedvideo data,setupinformation wastransmittedtotheon-
chipcontrollerthroughanI2Cbusinterface.
•I2Cisdesignedtobelowcost,easytoimplement,andofmoderatespeed(upto100KB/sfor
thestandardbusandupto400KB/sfortheextendedbus).Asaresult,itusesonlytwolines
theserialdataline(SDL)fordataandtheserialclockline(SCL), whichindicateswhenvalid data
areonthedataline.Figure4.6showsthestructureofatypicalI2Cbussystem.
•
Every nodeinthenetworkisconnectedtobothSCLandSDL.Somenodesmaybeabletoact
asbusmastersandthebusmay havemorethanonemaster.Othernodesmay actasslavesthat
onlyrespondtorequests frommasters.

• The basic electrical interface to the bus is shown in Figure 4.7.Thebus does not define
particular voltagestobeusedforhighorlowsothateitherbipolarorMOScircuitscanbe
connectedtothebus.
•Bothbussignalsuseopencollector/opendraincircuits.1Apull-upresistorkeepsthedefault
stateofthesignalhigh,andtransistorsareusedineachbusdevicetopulldownthesignalwhen a0is
tobetransmitted.
•
TheOpencollector/opendrainsignalingallowsseveraldevicestosimultaneouslywritethebus
withoutcausingelectricaldamage.Theopencollector/opendraincircuitryallowsaslavedevice
tostretchaclocksignalduring areadfromaslave.Themasterisresponsibleforgeneratingthe SCL
clock,buttheslavecanstretchthelowperiodoftheclock(butnotthehighperiod)if necessary.
• TheI2Cinterfaceonamicrocontrollercanbeimplementedwithvaryingpercentagesofthe
functionalityinsoftware andhardware[Phi89]. AsillustratedinFigure4.8,atypicalsystem
has a1-bithardwareinterfacewithroutinesforbyte level functions.
• TheI2Cdevicetakescareofgeneratingtheclockanddata.Theapplicationcodecallsroutines
tosendanaddress,sendadatabyte,andsoon,whichthengeneratestheSCL andSDL,
acknowledges,andsoforth.
 I2C signaling
o Sender pulls down bus for 0.
o Sender listens to bus---if it tried to send a 1 and heard a 0, someone else is
simultaneously transmitting.
o Transmissions occur in 8-bit bytes.
 I2C data link layer
o Every device has an address (7 bits in standard, 10 bits in extension).
o Bit 8 of address signals read or write.
o General call address allows broadcast.
 I C bus arbitration
2
o Sender listens while sending address.

o When sender hears a conflict, if its address is higher, it stops signaling.
o Low-priority senders relinquish control early enough in clock cycle to
allow bit to be transmitted reliably.

•Oneofthemicrocontroller’stimersistypicallyusedtocontrolthelengthofbitsonthebus.Interrupts
maybeusedtorecognizebits.However,whenusedinmastermode,polledI/Omay
beacceptableifnootherpending taskscanbeperformed,sincemastersinitiatetheirown transfers.
11. Explain the functionalities of RS232 and RS485 standard serial interface with neat
diagram. (May 2017)
Refer Question No. 1(i) for answer
UNIT – III
EMBEDDED FIRMWARE DEVELOPMENT ENVIRONMENT
PART B(C402.3)
1. Illustrate with functional description about the different phases of Embedded
Design Life Cycle model. (MAY 2016) (May 2017) (DEC 2016) (Dec 2017)
(i)EDLC is an Analysis-Design-Implementation based problem solving approach for the
product development. Analysis – What product need to be developed Design – Good
approach for building it Implementation – To develop it EDLC is an Analysis-Design-
Implementation based problem solving approach for the product development. Analysis
– What product need to be developed Design – Good approach for building it
Implementation – To develop it
(ii) Essential in understanding the scope and complexities involved in anyEmbedded
product development. Defines interaction and activities among Various groups of
product development sector. Project management , System design and development ,
System testing , Release management and quality assurance
(iii) Aim of any product development is the Marginal benefit Marginal benefit =
Return on investment Product needs to be acceptable by the end user i.e. it has to meet
the requirements of the end user in terms of quality, reliability & functionality. EDLC
helps in ensuring all these requirements by following three objective Ensuring that high
quality products are delivered to user Risk minimization and defect prevention in product
development through project management Maximize productivity
6. The primary definition of quality in any embedded product development is return on
investment achieved by the product. In order to survive in market, quality is very
important factor to be taken care of while developing the product. Qualitative attributes
depends on the budget of the product so budget allocation is very important. Budget
allocation might have done after studying the market, trends & requirements of product,
competition .etc.
7. Project management (PM) Adds an extra cost on budget But essential for ensuring the
development process is going in right direction Projects in EDLC requires Loose project
management or tight project management. PM is required for Predictability Analyze the
time to finish the product (PDS = no of person days ) Co-ordination Resources
(developers) needed to do the job Risk management. Backup of resources to overcome
critical situation . Ensuring defective product is not developed
8. Measure of efficiency as well as ROI Different ways to improve the productivity are
Saving the manpower X members – X period X/2 members – X period Use of automated
tools where ever is required Re-usable effort – work which has been done for the
previous product can be used if similarities present b/w previous and present product. Use
of resources with specific set of skills which exactly matches the requirements of the
product, which reduces the time in training the resource
9. A life cycle of product development is commonly referred as the “model” A simple
model contains fivephases Requirement analysis Design Development and test
Deployment and maintenance The no of phases involved in EDLC model depends on the
complexity of the product Classic Embedded product development life cycle model
10. NEED: Any embedded product may evolves as an output of a need. Need may come
from an individual/from public/from company(generally speaking from an end
user/client) ,New/custom product development , Product re-engineering , Product
maintenance CONCEPTUALIZATION:

11. ANALYSIS: Analyze and document functional and non-functional requirements
Interface definition and documentation Define test plan and procedure Requirement
specification document Document review Rework on requirements and documents
12. DESIGN:Deals with the entire design of the product taking the requirements into
consideration and focuses on how the functionalities can be delivered. •Only i/p & o/p are
defined here •Product will look like a black box •Sent for approval from client •Generates
detailed architecture •Detailed architecture also needs approval
13. DEVELOPMENT AND TESTING: Development phase transforms the design into
realizable product , Design is transformed into hardware and firmware , Look and feel of
the device is very important Testing phase can be divided into , Unit testing –
independent testing of hardware and firmware ,Integration testing – testing after
integrating hardware and firmware , System testing – testing of whole system on
functionality and non-functionality basis ,User acceptance testing – testing of the product
against the criteria mentioned by the end-user/client , Test reports
14. DEPLOYMENT: A process of launching fully functional model into the market
SUPPORT: Deals with the operation and maintenance of the product , Support should be
provide to the end user/client to fix the bugs of the product UPGRADES: , Releasing of
new version for the product which is already exists in the market , Releasing of major bug
fixes. RETIREMENT/DISPOSAL: ,Everything changes, the technology you feel as the
most advanced and best today may not be the same tomorrow , Due to this the product
cannot sustain in the market for long It has to be disposed on right time before it causes
the loss.
15. EDLC APPROACHES: Linear/Waterfall Model: Conceptualization Need Analysis
Design Development & testing Deployment Support Upgrades Retirement ,Each phase of
EDLC is executed in sequence ,Flow is unidirectional ,Output of one phase serving as
input of other
16. Iterative/Incremental/Fountain EDLC Model: ,Cascaded series of linear models ,Do
some analysis, follow some design, then some implementation in cycles ,Repeat the
cycles until the requirements are met
17. Prototyping/evolutionary model:  Similar to iterative model, product is developed in
multiple cycles  The only difference is the model produces more refined prototype of
the product at each cycle instead of just adding the functionality at each cycle like in
iterative model.
18. Spiral model: Spiral model is best suited for the development of complex embedded
products and situations where the requirements are changing from customer side. Risk
evaluation in each stage helps in reducing risk
2. Discuss about
i) Linear or Waterfall Model
Design methodologies
Process is important because without it, we can’t reliably deliver the products we want to
create. Thinking about the sequence of steps necessary to build something may seem
superfluous. But the fact is that everyone has their own design process, even if they don’t
articulate it. If you are designing embedded systems in your basement by yourself, having
your own work habits is fine. But when several people work together on a project, they
need to agree on who will do things and how they will get done. Being explicit about
process is important when people work together. Therefore, because many embedded
computing systems are too complex to be designed and built by one person, we have to
think about design processes.
• Time-to-market. Customers always want new features. The product that comes out first
can win the market, even setting customer preferences for future generations of the
product. The profitable market life for some products is three to six months—if you are
three months late, you will never make money. In some categories, the competition is
against the calendar, not just competitors. Calculators, for example, are disproportionately
sold just before school starts in the fall. If you miss your market window, you have to
wait a year for another sales season.
• Design cost. Many consumer products are very cost sensitive. Industrial buyers are also
increasingly concerned about cost. The costs of designing the system are distinct from
manufacturing cost—the cost of engineers’ salaries, computers used in design, and so on
must be spread across the units sold. In some cases, only one or a few copies of an
embedded system may be built, so design costs can dominate manufacturing costs.
Design costs can also be important for high volume consumer devices when time-to-
market pressures cause teams to swell in size.
• Quality. Customers not only want their products fast and cheap, they also want them to
be right. A design methodology that cranks out shoddy products will soon be forced out
of the marketplace. Correctness, reliability, and usability must be explicitly addressed
from the beginning of the design job to obtain a high quality product at the end.
Design flows
A design flow is a sequence of steps to be followed during a design
Design flow: sequence of steps in a design methodology.
May be partially or fully automated.
Use tools to transform, verify design.
Design flow is one component of methodology. Methodology also includes management
organization, etc.
Waterfall Model
The waterfall development model consists of five major phases: requirements analysis
determines the basic characteristics of the system; architecture design decomposes the
functionality into major components; coding implements the pieces and integrates them;
testing uncovers bugs; and maintenance entails deployment in the field, bug fixes, and
upgrades. The waterfall model gets its name from the largely one-way flow of work and
information from higher levels of abstraction to more detailed design steps. Although top-
down design is ideal because it implies good foreknowledge of the implementation during
early design phases, most designs are clearly not quite so top down. Most design projects
entail experimentation and changes that require bottom-up feedback. As a result, the
waterfall model is today cited as an unrealistic design process.
Spiral model
As design progresses, more complex systems will be constructed. At each level of design,
the designers go through requirements, construction, and testing phases. At later stages
when more complete versions of the system are constructed, each phase requires more
work, widening the design spiral. This successive refinement approach helps the
designers understand the system they are working on through a series of design cycles.
The first cycles at the top of the spiral are very small and short, while the final cycles at
the spiral’s bottom add detail learned from the earlier cycles of the spiral. The spiral
model is more realistic than the waterfall model because multiple iterations are often
necessary to add enough detail to complete a design. However, a spiral methodology with
too many spirals may take too long when design time is a major requirement.

Successive refinement model

In this approach, the system is built several times. A first system is used as a rough
prototype, and successive models of the system are further refined. This methodology
makes sense when you are relatively unfamiliar with the application domain for which
you are building the system. Refining the system by building several increasingly
complex systems allows you to test out architecture and design techniques. The various
iterations may also be only partially completed; for example, continuing an initial system
only through the detailed design phase may teach you enough to help you avoid many
mistakes in a second design iteration that is carried through to completion.
Embedded computing systems often involve the design of hardware as well as software.
Even if you aren’t designing a board, you may be selecting boards and plugging together
multiple hardware components as well as writing code. Front-end activities such as
specification and architecture simultaneously consider hardware and software aspects.
Similarly, back-end integration and testing consider the entire system. In the middle,
however, development of hardware and software components can go on relatively
independently— while testing of one will require stubs of the other, most of the hardware
and software work can proceed relatively independently.
ii) Iterative or Fountain Model.
 It follows analysis, design and implementation. Evaluate the product and cycle back
trough and conduct analysis, design and repeat the cycle.
 It is a cascade of series of linear models. Here, requirements are known at the begin-
ning and are derived into groups.
Advantages
 Provides good development cycle feedback at each function/ feature implementation
and data can be used as reference for similar product development in future.
More responsive to changing user needs.
Provides a working model with minimum features at first cycle itself.
Less manufacturing risk.
Product development can be stopped at any stage.
Drawbacks
 Extensive review requirement impact on operations due to new releases.
 Training for each new deployment.
iii) EDLC (MAY 2018)

The life cycle is referred as models. A typical simple product contains 5 phases-
 Requirement analysis
 Design
 Development and test
 Deployment
 Maintenance
The embedded product life cycle model contains phases as follows-
i) Need:
The embedded product is an output of ‘Need” from an individual/ public/ company.
Based on the need a proposal is prepared, reviewed by seniors, approved and then the
product goes to product development team.
The types of need could be as follows
 New or custom product development: Need for product which does not exist or as a
competitor for an existing product.
 Product re-engineering: The market is dynamic and competitive. Therefore there is
always a need of making changes in an existing product design and launching its new
version. Product re-engineering includes Product maintenance (technical support to
end user), Corrective maintenance (corrective action following a failure) and
Preventive maintenance (scheduled maintenance to avoid failure)
ii) Conceptualization:
It is a product development phase which begins after approval. In this stage the following
tasks are performed:
 Feasibility study: It is the careful examination of need and it suggests solutions to
build product.
 Cost Benefit analysis: This analysis involves identifying total development cost and
profits expected.
 Product scope: This means knowing what is in the scope and not in the scope for the
product.
 Planning activities: This covers various plans required for product development.
iii) Analysis:
This stage starts after the conceptualization phase is approved by the client. It
concentrates on developing functional model of product. The product is defined in detail
with respect to input, process and output. This stage determines the function performed
by product.
 Analysis and documentation: This phase analyzes business needs and purpose of
product. It also addresses various functional aspects and quality attributes.
 Interface definition and documentation: This defines interface between product and
other parts of systems.
 Defining Test plan and procedure: This defines the tests to be performed and what
should be included in the test. Some tests that are carried out are- Unit testing (unit/
module level), Integration testing (Integrating each module), System testing
(functional aspects) and User acceptance testing (meeting all requirements).
iv) Design:
The entire design of product as per requirements is done in this phase.
v) Development and testing:
This phase transforms design into realizable product.
vi) Deployment:
Deployment is nothing but launching first fully functional model of product. It includes
some important tasks as follows-
 Notification of product deployment: Launching ceremony details to stake holders and
public.
 Execution of training plan: Train the end user.
 Product installation: Install product to ensure it is fully functional.
 Product – Post implementation review: To determine success of product.
vii) Support:
Support means operation and maintenance of product in product environment. The
activities are-
 To set up a dedicated support wing
 To identify bugs and areas of improvement.
viii) Upgrade:
It is necessary to upgrade the product already present in market. Upgrades deals with
feature enhancement, bug fixes, etc.
ix) Retirement/ Disposal:
The product is declared as obsolete and is discontinued from market due to revolutionary
technology changes.
3. Discuss about
i) Prototyping or Evolutionary Model


(ii) Spiral Model.

The spiral model is a risk-driven software development process model. Based on the

unique risk patterns of a given project, the spiral model guides a team to adopt elements
of one or more process models, such as incremental, waterfall, or evolutionary
prototyping.
4. What are the fundamental issues in Hardware and software co-design in

Embedded
system?
The Hardware/Software Codesign Overview module is intended to introduce the

hardware/software codesign to the practicing design, software, and systems engineers, .
The module provides key codesign concepts and attempts to show the benefits of the
codesign approach over the current design process.The module consists of five sections.
The topic is introduced by defining codesign, illustrating its usefulness, and introducing
example systems that require this new methodology. the components that make up an
ideal codesign environment. The second describes the unified representation for hardware
and software that is one of the components for an ideal codesign environment. The third
section describes techniques used to partition a system into hardware and software
components. An automated partitioning algorithm is the ideal way to go, but this is a
difficult enough problem that many codesign environments still leave this problem up to
the expertise of the user.
The fourth section describes the integrated modeling substrate that forms a component of
an ideal codesign environment. This modeling substrate allows the complete
hardware/software system model to be simulated at any point in the design process, which
allows some degree of validation to be performed.
5. Enumurate state machine model for seat belt alarm system. (Dec 2017).
When inputs appear intermittently rather than as periodic samples, it is often convenient
to thinkof the system as reacting to those inputs.
• The reaction of most systems can be characterized in terms of the input received and the
current state of the system. This leads naturally to a finite-state machine style of
describing the reactive system’s behavior.
• Moreover, if the behavior is specified in that way, it is natural to write the
program implementing that behavior in a state machine style.
• The state machine style of programming is also an efficient implementation of
such computations. Finite-state machines are usually first encountered in the context of
hardware design. The State Machine example can be seen below.

6. Explain in detail the various testing performed in product development.

Unit testing: testing each unit or module of the product independently for required
functionality and quality aspects.
Integration testing: integrating each modules and testing the integrated unit for required
funstionality.
System testing: Testing the functional product developments after integration
- Usability testing
- Load testing
- Security testing
- Scalability testing
- Sanity testing
- Smoke testing
- Performance testing
- Endurance testing
7. Explain Sequential program model and concurrent process model.

Concurrent engineering
When designing a large system along with many people, it is easy to lose track of the
complete design flow and have each designer take a narrow view of his or her role in the
design flow. Concurrent engineering attempts to take a broader approach and optimize the
total flow.
Concurrent engineering efforts are comprised of the elements described below.
• Cross-functional teams include members from various disciplines involved in the process,
including manufacturing, hardware and software design, marketing, and so forth.
• Concurrent product realization process activities are at the heart of concurrent engineering.
Doing several things at once, such as designing various subsystems simultaneously, is critical
to reducing design time.
• Incremental information sharing and use helps minimize the chance that concurrent product
realization will lead to surprises. As soon as new information becomes available, it is shared
and integrated into the design. Cross-functional teams are important to the effective sharing
of information in a timely fashion.
• Integrated project management ensures that someone is responsible for the entire project,
and that responsibility is not abdicated once one aspect of the work is done.
• Early and continual supplier involvement helps make the best use of suppliers’ capabilities.
• Early and continual customer focus helps ensure that the product best meets customers’
needs.

8. What are the issues in hardware software and co-design?(MAY 2018)

Two approaches for the embedded system design device programmer system design
device programmer
(1) When the software development cycle ends then the cycle begins for the process of
integrating the software into the hardware at the time when a system is designed .
(2) Both cycles concurrently proceed when co-designing a time critical sophisticated
system.
Software Hardware Tradeoff Software Hardware Tradeoff
It is possible that certain subsystems in hardware (microcontroller), IO memory accesses,
real-time clock, system clock, pulse width modulation, timer and serial communication
are also implemented by the software. A serial communication real-time clock and timers
featuring microcontroller may cost more than the microprocessor with external memory
and a software implementation.
Hardware implementations provide advantage of processing speed Reduced memory for
the program. (ii) Reduced number of chips but at an increased cost.
(iii) Simple coding for the device drivers.
(iv) Internally embedded codes, which are more secure than at the external ROM
(v) Energy dissipation can be controlled by controlling the clock rate and voltage
Software implementation advantages Software implementation advantages
( i) Easier to change when new hardware versions become available.
(ii) Programmability for complex operations.
(iii) Faster development time.
(iv) Modularity and portability.
( v) Use of standard software engineering, modeling and RTOS tools.
(vi) Faster speed of operation of complex functions with high-speed microprocessors.
(vii) Less cost for simple systems.
Units to be Units to be choosen choosen Processor ASIP or ASSP Multiple processors
System-on Chip Memory Other Hardware Units of System Buses. Software Language
RTOS (real-time programming OS) Code generation tools . Tools for finally embedding
the software into binary image.
Embedded System Processors Choice Embedded System Processors Choice. Processor
Less System System with Microprocessor or Microcontroller or DSP System with
Single purpose processor or ASSP in VLSI or FPGA
9. Explain the Common computational model with neat diagrams. (MAY 2018)
It is useful to understand how a high-level language program is translated into
instructions. Since implementing an embedded computing system often requires
controlling the instruction sequences used to handle interrupts, placement of data and
instructions in memory, and so forth, understanding how the compiler works can help you
know when you cannot rely on the compiler.
Next, because many applications are also performance sensitive, understanding how code
is generated can help you meet your performance goals, either by writing high-level
code that gets compiled into the instructions you want or by recognizing when you must
write your own assembly code.
Compilation begins with high-level language code such as C and generally produces
assembly code. (Directly producing object code simply duplicates the functions of an
assembler which is a very desirable stand-alone program to have.)
The high-level language program is parsed to break it into statements and expressions. In
addition, a symbol table is generated, which includes all the named objects in the
program. Some compilers may then perform higher-level optimizations that can be
viewed as modifying the high-level language program input without reference to
instructions.
Simplifying arithmetic expressions is one example of a machine-independent
optimization. Not all compilers do such optimizations, and compilers can vary widely
regarding which combinations of machine-independent optimizations they do perform.
Instruction-level optimizations are aimed at generating code. They may work directly on
real instructions or on a pseudo-instruction format that is later mapped onto the
instructions of the target CPU. This level of optimization also helps modularize the
compiler by allowing code generation to create simpler code that is later optimized. For
example, consider the following array access code:
x[i] = c*x[i];
A simple code generator would generate the address for x[i] twice, once for each
appearance in the statement. The later optimization phases can recognize this as an
example of common expressions that need not be duplicated. While in this simple case
it would be
possible to create a code generator that never generated the redundant expression, taking
into account every such optimization at code generation time is very difficult. We get
better code
and more reliable compilers by generating simple code first and then optimizing it.

10.With a suitable example, explain about the state machine model of an Automatic
Chocolate Vending Machine (ACVM).(MAY 2016) (DEC 2016)
1.Requirements: The requirements of the machine can be shown below:
1.purpose: To sell chocolate through an ACVM from which children can automatically
purchase the chocolate. The payment is by inserting the coins of appropriate amount into
a coin slot.
2.Inputs: Coins.User commands.
3.Signals,events and notification: Each port generates an interrupt on receiving a coin at
input. Each port interrupt starts an ISR, which increases value of amount . Each
selected menu choice sends a notification to the system.
4. Outputs Chocolate. Refund. Display of the menu for GUIS, time and date, welcome
messages.
5.Functions of the system: A child sends commands to the system using GUIS.The GUIS
consists of the LCD, keypad and touch screen.The child insert the coins for the cost of
chocolate and the machine delivers the chocolate. If the coins are of more amount than
cost of chocolate, the excess amount is refunded along with chocolate. USB wireless
modem enables communication to ACVM owner.
6.Design metrics: Power dissipation: As required by mechanical units and
display.Process deadline: Machine waits for a maximum of 30sec for the coin and the
machine should deliver the chocolate within 60sec.
11(i) Write detailed notes on software and hardware interface techniques. (May 2017)
The Hardware/Software Codesign Overview module is intended to introduce
the hardware/software codesign to the practicing design, software, and systems
engineers, . The module provides key codesign concepts and attempts to show the
benefits of the codesign approach over the current design process.
The module consists of five sections. The topic is introduced by defining codesign,
illustrating its usefulness, and introducing example systems that require this new
methodology. the components that make up an ideal codesign environment.
The second describes the unified representation for hardware and software that is one of
the components for an ideal codesign environment.
The third section describes techniques used to partition a system into hardware and
software components. An automated partitioning algorithm is the ideal way to go, but this

is a difficult enough problem that many codesign environments still leave this problem up
to the expertise of the user.
The fourth section describes the integrated modeling substrate that forms a component of
an ideal codesign environment. This modeling substrate allows the complete
hardware/software system model to be simulated at any point in the design process, which
allows some degree of validation to be performed.
(ii) Explain about sequential program model for the development of embedded
platform.(May2017)
*Despite benefits of state machine model, most popular development tools use
sequential programming language C, C++, Java, Ada, VHDL, Verilog, etc.
*Development tools are complex and expensive, therefore not easy to adapt or replace
Must protect investment
*Two approaches to capturing state machine model with sequential programming
language
*Front-end tool approach, Additional tool installed to support state machine language
Graphical and/or textual state machine languages
*May support graphical simulation
*Automatically generate code in sequential programming language that is input to main
development tool
*Drawback: must support additional tool (licensing costs, upgrades, training,
etc.),Language subset approach
*Most common approach...
Follow rules (template) for capturing state machine constructs in equivalent sequential
language constructs
Used with software (e.g.,C) and hardware languages (e.g.,VHDL) ,Capturing UnitControl
state machine in C,Enumerate all states (#define)
*Declare state variable initialized to initial state (IDLE) Single switch statement branches
to current state’s case.Each case has actions up, down, open, timer_start
*Each case checks transition conditions to determine next state
if(…) {state = …;}
UNIT–IV
RTOS BASED EMBEDDED SYSTEM DESIGN
PART B(C402.4)
1. Explain in detail the features and scheduling algorithm used in RTOS of μC/OS-II.
(May 2017)
RTOS
As the name suggests, there is a deadline associated with tasks and an RTOS adheres to
this deadline as missing a deadline can cause affects ranging from undesired to
catastrophic. The example we discussed in the beginning of this article is an example of
catastrophic affect of an RTOS missing a deadline.
As discussed above that the embedded systems are becoming more and more complex
today and with each passing generation their intrusion in our daily lives will become
deeper. This means they will bear more and more responsibilities on their shoulders to
solve real time problems to make our life easier. But, this requires more and more
complex real time applications that RTOS will have to manage effectively.
Classification of RTOS
RTOS can be classified into three types :
Hard RTOS : These type of RTOS strictly adhere to the deadline associated with the
tasks. Missing on a deadline can have catastrophic affects. The air-bag example we
discussed in the beginning of this article is example of a hard RTOS as missing a deadline
there could cause a life.

Firm RTOS : These type of RTOS are also required to adhere to the deadlines because
missing a deadline may not cause a catastrophic affect but could cause undesired affects,
like a huge reduction in quality of a product which is highly undesired.
Soft RTOS : In these type of RTOS, missing a deadline is acceptable. For example On-
line Databases.
Widely used RTOS:
LynxOS
OSE
QNX
RTLinux
VxWorks
Windows CE
The features of µC/OS-II include:
Preemptive multitasking real-time kernel
Delivered with complete, clean, consistent, 100% ANSI C source code with in-depth
documentation.
Mutual exclusion semaphores with built-in priority ceiling protocol to prevent priority
inversions
Timeouts on ‘pend’ calls to prevent deadlocks
Up to 254 application tasks (1 task per priority level), and unlimited number of kernel
objects
Highly scalable (6K to 24K bytes code space, 1K+ bytes data space)
Very Low Interrupt Disable Time
Third party certifiable
2. What is Data Share Problem? Give the procedure for avoiding this problem.
A similar situation applies to other kinds of shared resources - not just shared data.
Consider two or more threads that want to simultaneously send data to the same (shared)
disk, printer, network card, or serial port. If access is not arbitrated so that only one
thread uses the resource at a time, the data streams might get mixed together, producing
nonsense at the destination.
Non-preemptive system: Programmer has explicit control over where and when context
switch occurs.
Except for ISRs!
Preemptive system: Programmer has no control over the time and place of a context
switch.
Protection Options:
Disabling interrupts
Spin lock
mutex
semaphore

3. Explain the round robin with interrupt architecture with an example.

A scheduling policy defines how processes are selected for promotion from the ready
state to the running state.
Every multitasking OS implements some type of scheduling policy.
Choosing the right scheduling policy not only ensures that the system will meet all its
timing requirements, but it also has a profound influence on the CPU horsepower required
to implement the system’s functionality.
Schedulability means whether there exists a schedule of execution for the processes in a
system that satisfies all their timing requirements.
In general, we must construct a schedule to show schedulability, but in some cases we can
eliminate some sets of processes as unschedulable using some very simple tests.
Utilization is one of the key metrics in evaluating a scheduling policy. Our most basic
requirement is that CPU utilization be no more than 100% since we can’t use the CPU
more than 100% of the time.
 When we evaluate the utilization of the CPU, we generally do so over a
finite period that covers all possible combinations of process executions.
 For periodic processes, the length of time that must be considered is the
hyper period, which is the least-common multiple of the periods of all the
processes.
 The complete schedule for the least-common multiple of the periods is
sometimes called the unrolled schedule.
Some scheduling policies can deliver higher CPU utilizations than others, even for the
same timing requirements.
 One very simple scheduling policy is known as cyclostatic scheduling or
sometimes as TimeDivision Multiple Access scheduling.
 As illustrated in below diagram, a cyclostatic schedule is dividedinto
equal-sized time slots over an interval equal to the length of the
hyperperiodH. Processes always run in the same time slot.
Cyclostatic scheduling.

 Two factors affect utilization: the number of time slots used and the
fraction of each time slot that is used for useful work.
 Depending on the deadlines for some of the processes, we may need to
leave some time slots empty.
 And since the time slots are of equal size, some short processes may have
time left over in their time slot
 Another scheduling policy that is slightly more sophisticated is round
robin.
 It also evaluates the processes in order.
Round-robin scheduling.
 But unlike cyclostatic scheduling, if a process does not have any useful
work to do, the round-robin scheduler moves on to the next process in
order to fill the time slot with useful work.
 In this example, all three processes execute during the first hyper period,
but during the second one, P1 has no useful work and is skipped.
 The processes are always evaluated in the same order. The last time slot in
the hyper period is left empty; if we have occasional, non-periodic tasks
without deadlines.
 Round-robin scheduling is often used in hardware such as buses because it
is very simple to implement but it provides some amount of flexibility.
 In addition to utilization, we must also consider scheduling overhead—
the execution time required to choose the next execution process, which is
incurred in addition to any context switching overhead
 In general, the more sophisticated the scheduling policy, the more CPU
time it takes during system operation to implement it.
 Moreover, we generally achieve higher theoretical CPU utilization by
applying more complex scheduling policies with higher overheads.
 The final decision on a scheduling policy must take into account both
theoretical utilization and practical scheduling overhead.
4. Explain in detail about task, process and threads in RTOS based embedded system
design.
 Many (if not most) embedded computing systems do more than one thing
that is, the environment can cause mode changes that in turn cause the
embedded system to behave quite differently.
 For example, when designing a telephone answering machine, We can
define recording a phone call and operating the user’s control panel as
distinct tasks, because they perform logically distinct operations and they
must be performed at very different rates.
 These different tasks are part of the system’s functionality, but that
application-level organization of functionality is often reflected in the
structure of the program as well.
 A process is a single execution of a program. If we run the same program
two different times, we have created two different processes. Each process
has its own state that includes not only its registers but all of its memory.

 In some OSs, the memory management unit is used to keep each process in
a separate address space. In others, particularly lightweight RTOSs, the
processes run in the same address space. Processes that share the same
address space are often called threads.
 As shown in below figure this device is connected to serial ports on both
ends. The input to the box is an uncompressed stream of bytes.
 The box emits a compressed string of bits on the output serial line, based
on a predefined compression table. Such a box may be used, for example,
to compress data being sent to a modem.
 The program’s need to receive and send data at different rates for example,
the program may emit 2 bits for the first byte and then 7 bits for the second
byte will obviously find itself reflected in the structure of the code.
 It is easy to create irregular, ungainly code to solve this problem; a more
elegant solution is to create a queue of output bits, with those bits being
removed from the queue and sent to the serial port in 8-bit sets.
An on-the-fly compression box.

 But beyond the need to create a clean data structure that simplifies the
control structure of the code, we must also ensure that we process the
inputs and outputs at the proper rates
 The text compression box provides a simple example of rate control
problems. A control panel on a machine provides an example of a different
type of rate control problem, the asynchronousinput.
 The control panel of the compression box may, for example, include a
compression mode button that disables or enables compression, so that the
input text is passed through unchanged when compression is disabled.
Threads
Threads are defined by executable files while drivers are defined by dynamically-
linkedlibraries (DLLs). A process can run multiple threads. All the threads of a process
share thesame execution environment. Threads in different processes run in different
executionenvironments. Threads are scheduled directly by the operating system. Threads
maybe launched by a process or a device driver. A driver may be loaded into the
operatingsystem or a process. Drivers can create threads to handle interrupts.

Each thread is assigned an integer priority. Lower-valued priorities signify higherpriority:

0 is the highest priority and 255 is the lowest possible priority. Priorities 248through 255
are used for non-real-time threads while the higher priorities are used forvarious
categories of real-time execution. The operating system maintains a queueof ready
processes at each priority level. Execution is divided into time quanta. Each thread can
have a separate quantum, which can be changed using the API. If the runningprocess does
not go into the waiting state by the end of its time quantum, it issuspended and put back
into the queue. Execution of a thread can also be blocked bya higher-priority thread.
Interrupt handling is divided among three entities:
The interrupt service handler (ISH) is a kernel service that provides the firstresponse
to the interrupt.
The ISH selects an interrupt service routine (ISR) to handle the interrupt.The ISH runs
in the kernel with interrupts turned off; as a result, it should bedesigned to do as little
direct work as possible.
The ISR in turn calls an interrupt service thread (IST) which performs most ofthe work
required to handle the interrupt. The IST runs in the OAL and so canbe interrupted by a
higher-priority interrupt.
5. Explain the need for IPC functions and interprocess communications.(MAY 2018)
Inter processor communication in a multiprocessor system─ used to generate information
about certain sets of computations finishing on one processor and to let the other
processors waiting for finishing the computations take note of the information. Similarly,
there is inter process communication from a process (task or thread to another)
Need of Inter Process Communication
• Assume that there is need to send through the kernel an output data (a message of a
known size with or without a header or a flag to notify an event) for processing or taking
note of by another task
• Global variables problems ─ shared data and no encapsulation of the data or message
accessibility by other tasks
• Inter Process Communication (IPC) functions in the OS provide the solutions means
that a process (scheduler, task or ISR) generates some information by signal (for other
process start) or value (for example of semaphore) or generates an output so that it lets
another process take note or use it through the kernel functions for the IPCs
Inter Process Communication (IPC) in Multitasking System
Used to signal for other process to start or post a token or flag or generate message from
the certain sets of computations finishing on one task and to let the other tasks take note
of signal or get the message.
Inter Process Communication for print Inter Process Communication
print task can be shared among the multiple tasks, which use the mutex semaphore IPC in
their critical sections
• When the buffer becomes available for new data, an IPC from the print task is generated
and the kernel first takes note of it.
• Other tasks then take note of the IPC.
A task take note of IPC by OSSemPend ( ) function─ used at the beginning of the critical
section
• The task gets mutually exclusive access to the section to send messages into the print-
buffer by using the OSSemPost ( ) function of the kernel at the end of the section
6. Compare real time operating systemsVXWorks,MC/OS-II and RT Linux
VxWorks:
VxWorks is a real-time operating system (RTOS) developed as proprietary
software by Wind River Systems, an Intel subsidiary of Alameda, California, US. First
released in 1987, VxWorks is designed for use in embedded systems requiring real-time,
deterministic performance and, in many cases, safety and security certification, for industries,
such as aerospace and defense, medical devices, industrial equipment, robotics, energy,
transportation, network infrastructure, automotive, and consumer electronics.
VxWorks supports Intel architecture, POWER architecture, and ARM architectures. The
RTOS can be used in multicore asymmetric multiprocessing (AMP), symmetric
multiprocessing (SMP), and mixed modes] and multi-OS (via Type 1 hypervisor) designs
on 32- and 64-bit processors.
VxWorks comes with the kernel, middleware, board support packages, Wind River
Workbench development suite and complementary third-party software and hardware
technologies. In its latest release, VxWorks 7, the RTOS has been re-engineered for
modularity and upgradeability so the OS kernel is separate from middleware, applications
and other packages. Scalability, security, safety, connectivity, and graphics have been
improved to address Internet of Things (IoT) needs.
VxWorks supports Intel architecture, Power architecture, and ARM architectures. The RTOS
can be used in multi-core asymmetric multiprocessing (AMP), symmetric
multiprocessing (SMP), and mixed modes and multi-OS (via Type 1 hypervisor) designs on
32- and 64-bit processors.
The VxWorks consists of a set of runtime components and development tools. The run time
components are an operating system (UP and SMP; 32- and 64-bit), software for applications
support (file system, core network stack, USB stack and inter-process communications) and
hardware support (architecture adapter, processor support library, device driver library and
board support packages). VxWorks core development tools are compilers such as Diab,
GNU, and Intel C++ Compiler (ICC)) and its build and configuration tools. The system also
includes productivity tools such as its Workbench development suite and Intel tools and
development support tools for asset tracking and host support.
The platform is a modular, vendor-neutral, open system that supports a range of third-party
software and hardware. The OS kernel is separate from middleware, applications and other
packages, which enables easier bug fixes and testing of new features. An implementation of a
layered source build system allows multiple versions of any stack to be installed at the same
time so developers can select which version of any feature set should go into the VxWorks
kernel libraries.
Optional advanced technology for VxWorks provides add-on technology-related capabilities,
such as:
 Advanced security features to safeguard devices and data residing in and traveling
across the Internet of Things (IoT)
 Advanced safety partitioning to enable reliable application consolidation
 Real-time advanced visual edge analytics allowing autonomous responses on Vx-
Works-based devices in real time without latency
 Optimized embedded Java runtime engine enabling the deployment of Java applica-
tions
 Virtualization capability with a real-time embedded, Type 1 hypervisor
A list of some of the features of the OS are:
 Multitasking kernel with preemptive and round-robin scheduling and fast interrupt re-
sponse
 Native 64-bit operating system (only one 64-bit architecture supported: x86-64). Data
model: LP64.
 User-mode applications ("Real-Time Processes", or RTP) isolated from other user-
mode applications as well as the kernel via memory protection mechanisms.
 SMP, AMP and mixed mode multiprocessing support
 Error handling framework
 Bluetooth, USB, CAN protocols, Firewire IEEE 1394, BLE, L2CAP, Continua stack,
health device profile
 Binary, counting, and mutual exclusion semaphores with priority inheritance
 Local and distributed message queues
 POSIX PSE52 certified conformity in user-mode execution environment
 File systems: High Reliability File System (HRFS), FAT-based file system
(DOSFS), Network File System (NFS), and TFFS
 Dual-mode IPv6 networking stack with IPv6 Ready Logo certification
 Memory protection including real-time processes (RTPs), error detection and report-
ing, and IPC
 Multi-OS messaging using TIPC and Wind River multi-OS IPC
 Symbolic debugging
In March 2014, Wind River introduced VxWorks 7, which emphasizes scalability, security,
safety, connectivity, graphics, and virtualization. The following lists some of the release 7
updates. More information can be found on the Wind Rivers VxWorks website.
 Modular, componentized architecture using a layered build system with the ability to
update each layer of code independently
 VxWorks microkernel (a full RTOS that can be as small as 20 KB)
 Security features such as digitally-signed modules (X.509), encryption, password
management, ability to add/delete users at runtime
 SHA-256 hashing algorithm as the default password hashing algorithm
 Human machine interface with Vector Graphics, and Tilcon user interface (UI)
 Graphical user interface (GUI): OpenVG stack, Open GL, Tilcon UI, Frame Buffer
Driver, EV Dev Interface
 Updated configuration interfaces for VxWorks Source Build VSB projects and Vx-
Works Image Projects
 Single authentication control used for Telnet, SSH, FTP, and rlogin daemons
 Connectivity with Bluetooth and SocketCAN protocol stacks
 Inclusion of MIPC File System (MFS) and MIPC Network Device (MND)
 Networking features with 64-bit support including Wind River MACsec, Wind
River’s implementation of IEEE 802.1A, Point-to-Point Protocol (PPP) over L2TP, PPP
over virtual local area network (VLAN) and Diameter secure key storage
 New Wind River Workbench 4 for VxWorks 7 integrated development environment
with new system analysis tools
 Wind River Diab Compiler 5.9.4; Wind River GNU Compiler 4.8; Intel C++ Com-
piler 14 and Intel Integrated Performance Primitives (IPP) 8
RTLinux
RTLinux is a hard realtime RTOS microkernel that runs the entire Linux operating system as
a fully preemptiveprocess. The hard real-time property makes it possible to control robots,
data acquisition systems, manufacturing plants, and other time-sensitive instruments and
machines from RTLinux applications. Even with a similar name it is not related the "Real-
Time Linux" project of the Linux Foundation.
RTLinux was developed by Victor Yodaiken, Michael Barabanov, CortDougan and others at
the New Mexico Institute of Mining and Technology and then as a commercial product
at FSMLabs. Wind River Systems acquired FSMLabs embedded technology in February
2007 and made a version available as Wind River Real-Time Core for Wind River Linux. As
of August 2011, Wind River has discontinued the Wind River Real-Time Core product line,
effectively ending commercial support for the RTLinux product. RTLinux provides the
capability of running special real-time tasks and interrupt handlers on the same machine as
standard Linux. These tasks and handlers execute when they need to execute no matter what
Linux is doing. The worst case time between the moment a hardware interrupt is detected by
the processor and the moment an interrupt handler starts to execute is under 15 microseconds
on RTLinux running on a generic x86 (circa 2000). A RTLinux periodic task runs within 35
microseconds of its scheduled time on the same hardware. These times are hardware limited,
and as hardware improves RTLinux will also improve. Standard Linux has excellent average
performance and can even provide millisecond level scheduling precision for tasks using the
POSIX soft real-time capabilities. Standard Linux is not, however, designed to provide sub-
millisecond precision and reliable timing guarantees. RTLinux was based on a lightweight
virtual machine where the Linux "guest" was given a virtualized interrupt controller and
timer, and all other hardware access was direct. From the point of view of the real-time
"host", the Linux kernel is a thread. Interrupts needed for deterministic processing are
processed by the real-time core, while other interrupts are forwarded to Linux, which runs at
a lower priority than real-time threads. Linux drivers handled almost all I/O. First-In-First-
Out pipes (FIFOs) or shared memory can be used to share data between the operating system
and RTLinux.
The majority of RTLinux functionality is in a collection of loadable kernel modules that
provide optional services and levels of abstraction. These modules include:
1. rtlsched - a priority scheduler that supports both a "lite POSIX" interface described
below and the original V1 RTLinux API.
2. rtl time - which controls the processor clocks and exports an abstract interface for
connecting handlers to clocks.
3. rtlposixio - supports POSIX style read/write/open interface to device drivers.
4. rtlfifo - connects RT tasks and interrupt handlers to Linux processes through a device
layer so that Linux processes can read/write to RT components.
5. semaphore - a contributed package by Jerry Epplin which gives RT tasks blocking
semaphores.
6. POSIX mutex support is planned to be available in the next minor version update of
RTLinux.
7. mbuff is a contributed package written by Tomasz Motylewski for providing shared
memory between RT components and Linux processes.
RTLinuxrealtime tasks get implemented as kernel modules similar to the type of module that
Linux uses for drivers, file systems, and so on. Realtime tasks have direct access to the
hardware and do not use virtual memory. On initialization, a realtime task (module) informs
the RTLinux kernel of its deadline, period, and release-time constraints.
The key RTLinux design objective is that the system should be transparent, modular, and
extensible. Transparency means that there are no unopenable black boxes and the cost of any
operation should be determinable. Modularity means that it is possible to omit functionality
and the expense of that functionality if it is not needed. And extensibility means that
programmers should be able to add modules and tailor the system to their requirements. The
base RTLinux system supports high speed interrupt handling and no more. It has simple
priority scheduler that can be easily replaced by schedulers more suited to the needs of some
specific application. When developing RTLinux, it was designed to maximize the advantage
we get from having Linux and its powerful capabilities available. RTLinux is structured as a
small core component and a set of optional components. The core component permits
installation of very low latency interrupt handlers that cannot be delayed or preempted by
Linux itself and some low level synchronization and interrupt control routines. This core
component has been extended to support SMP and at the same time it has been simplified by
removing some functionality that can be provided outside the core.
µC/OS-II
Micro-Controller Operating Systems (MicroC/OS, stylized as µC/OS) is a real-time
operating system (RTOS) designed by embedded software developer, Jean J. Labrosse in
1991. It is a priority-based preemptive real-time kernel for microprocessors, written mostly in
the programming language C. It is intended for use in embedded systems.
MicroC/OS allows defining several functions in C, each of which can execute as an
independent thread or task. Each task runs at a different priority, and runs as if it owns
the central processing unit (CPU). Lower priority tasks can be preempted by higher priority
tasks at any time. Higher priority tasks use operating system (OS) services (such as a delay or
event) to allow lower priority tasks to execute. OS services are provided for managing tasks
and memory, communicating between tasks, and timing.
Based on the source code written for µC/OS, and introduced as a commercial product in 1998, µC/
OS-II is a portable, ROM-able, scalable, preemptive, real-time, deterministic, multitasking ker-
nel for microprocessors, and digital signal processors (DSPs). It manages up to 255 application tasks.
Its size can be scaled (between 5 and 24 Kbytes) to only contain the features needed for a given use.
Most of µC/OS-II is written in highly portable ANSI C, with target microprocessor-specific code
written in assembly language. Use of the latter is minimized to ease porting to other processors.
Uses in embedded systems
µC/OS-II was designed for embedded uses. If the producer has the proper tool chain (i.e., C compiler,
assembler, and linker-locator), µC/OS-II can be embedded as part of a product.
µC/OS-II is used in many embedded systems, including:
 Avionics
 Medical equipment and devices
 Data communications equipment
 White goods (appliances)
 Mobile phones, personal digital assistants (PDAs), MIDs
 Industrial controls
 Consumer electronics
 Automotive
Task states
µC/OS-II is a multitasking operating system. Each task is an infinite loop and can be in any one of the
following five states.
 Dormant
 Ready
 Running
 Waiting (for an event)
 Interrupted (interrupt service routine (ISR))

Further, it can manage up to 255 tasks. However, it is recommended that eight of these tasks be re -
served for µC/OS-II, leaving an application up to 247 tasks.
RT Linux:
RTLinux is a hard realtime RTOS microkernel that runs the entire Linux operating
system as a fully preemptive process. The hard real-time property makes it possible to
control robots, data acquisition systems, manufacturing plants, and other time-sensitive
instruments and machines from RTLinux applications.
7. Explain the types of semapores and their uses.(MAY 2018)
Semaphore is a technique for synchronizing two/more task competing for the same
resources. When a task wants to use a resource, it requests for the semaphore and will be
allocated if the semaphore is available. If the semaphore is not available then the
requesting task will go to blocked state till the semaphore becomes free. Consider a
situation where there are two persons who want to share a bike. At one time only one
person can use the bike. The one who has the bike key will get the chance to use it. And
when this person gives the key to the 2nd person, then the 2nd person can use the bike.
Semaphore is just like this Key and the bike is the shared resource. Whenever a task
wants access to the shared resource, it must acquire the semaphore first. The task should
release the semaphore after it is done with the shared resource. Until this time all other
tasks have to wait if they need access to shared resource as semaphore is not available.
Even if the task trying to acquire the semaphore is of higher priority than the task
acquiring the semaphore, it will be in the wait state until the semaphore is released by the
lower priority task.
Types of Semaphores:
There are 3-types of semaphores namely Binary, Counting and Mutex semaphore.
Binary Semaphore: Binary semaphore is used when there is only one shared resource.
Binary semaphore exists in two states ie.Acquired(Take), Released(Give). Binary
semaphores have no ownership and can be released by any task or ISR regardless of who
performed the last take operation. Because of this binary semaphores are often used to
synchronize tasks with external events implemented as ISRs, for example waiting for a
packet from a network or waiting for a button is pressed.
Counting Semaphore: To handle more than one shared resource of the same type,
counting semaphore is used. Counting semaphore will be initialized with the count(N)
and it will allocate the resource as long as count becomes zero after which the requesting
task will enter blocked state. • Mutex Semaphore: Mutex is very much similar to binary
semaphore and takes care of priority inversion, ownership, and recursion.
8. Give the details about handling of Task Scheduling, Latency, and Deadlines as
performance Metrics.
Assigning tasks
Tasks with the highest rate of execution are given the highest priority using rate-monotonic schedul-
ing. This scheduling algorithm is used in real-time operating systems (RTOS) with a static-priority
scheduling class.
Managing tasks
In computing, a task is a unit of execution. In some operating systems, a task is synonymous with
a process, in others with a thread. In batch processing computer systems, a task is a unit of execution
within a job. The system user of µC/OS-II is able to control the tasks by using the following features:
 Task feature
 Task creation
 Task stack & stack checking
 Task deletion
 Change a task’s priority
 Suspend and resume a task
 Get information about a task

Example ─ Automatic Chocolate Vending Machine:

 Software highly complex.
 RTOS schedules to run the application embedded software as consisting of the num-
ber of Tasks
 Number of functions, ISRs, interrupt service- threads, tasks, multiple physical and vir-
tual device drivers, and several program objects that must be concurrently processed
on a single processor
Exemplary tasks at the ACVM:

 Task User Keypad Input ─ keypad task to get the user input
 Task Read-Amount ─ for reading the inserted coins amount,
 Chocolate delivery task ─ delivers the chocolate and signals the machine for readying
for next input of the coins,
 Display Task,
 GUI_Task─for graphic user interfaces,
 Communication task ─ for provisioning the AVCM owner access the machine Infor-
mation and information.
Task States:
(i) Idle state [Not attached or not registered]
(ii) Ready State [Attached or registered]
(iii) Running state
(iv) Blocked (waiting) state
(v) Delayed for a preset period - Number of possible states depends on the RTOS.

Idle (created) state: The task has been created and memory allotted to its structure. However,
it is not ready and is not schedulable by kernel.
Ready (Active) State: The created task is ready and is schedulable by the kernel but not
running at present as another higher priority task is scheduled to run and gets the system
resources at this instance.
Running state: Executing the codes and getting the system resources
Deadlines:
Many real-time systems rely on static scheduling algorithms. This includes cyclic
scheduling, rate monotonic scheduling and fixed schedules created by off-line scheduling
techniques such as dynamic programming, heuristic search, and simulated annealing.
However, for many real-time systems, static scheduling algorithms are quite restrictive
and inflexible. For example, highly automated agile manufacturing, command, control
and communications, and distributed real-time multimedia applications all operate over
long lifetimes and in highly non-deterministic environments. Dynamic real-time
scheduling algorithms are more appropriate for these systems and are used in such
systems. Many of these algorithms are based on earliest deadline first (EDF) policies.
There exists a wealth of literature on EDF-based scheduling with many extensions to deal
with sophisticated issues such as precedence constraints, resource requirements, system
overload, multi-processors, and distributed systems.
Deadline Scheduling for Real-Time Systems: EDF and Related Algorithms aims at
collecting a significant body of knowledge on EDF scheduling for real-time systems, but
it does not try to be all-inclusive (the literature is too extensive). The book primarily
presents the algorithms and associated analysis, but guidelines, rules, and implementation
considerations are also discussed, especially for the more complicated situations where
mathematical analysis is difficult. In spite of the recent advances there are still gaps in the
solution space and there is a need to integrate the available solutions. For example, a list
of issues to consider includes:
 preemptive versus non-preemptive tasks,
 uni-processors versus multi-processors,
 using EDF at dispatch time versus EDF-based planning,
 precedence constraints among tasks,
 resource constraints,
 periodic versus aperiodic versus sporadic tasks,
 scheduling during overload,
 fault tolerance requirements, and
 providing guarantees and levels of guarantees (meeting quality of service
requirements).
In computing, interrupt latency is the time that elapses from when an interrupt is
generated to when the source of the interrupt is serviced. For many operating systems,
devices are serviced as soon as the device's interrupt handler is executed. Interrupt latency
may be affected by microprocessor design, interrupt controllers, interrupt masking, and
the operating system's (OS) interrupt handling methods.
9. Write notes on mutual exclusion, critical section, deadlock and paging.

Critical section = Is shared resource or part of program, not allowed to access by more
than one process at same time.
Deadlock = Deadlock is a situation in which process waiting for resource, which hold by
another process , which in turn waiting for resource hold by another process. in this way
all process waiting for resource form cycle, and no process can complete its execution.
this is called dead lock.
Mutual exclusion = Shared resource is not allowed to access by more than one process at
same time is called mutual exclusion
Paging=In computer operating systems, demand paging (as opposed to
anticipatorypaging) is a method of virtual memory management. ... It follows that a
process begins execution with none of its pages in physical memory, and many page
faults will occur until most of a process's working set of pages is located in physical
memory.
10. Explain how the interrupt routines are handled by RTOS and illustrate the features
of VxWorks.(May 2016)(Dec16)
VxWorks:
VxWorks is a real-time operating system (RTOS) developed as proprietary
software by Wind River Systems, an Intel subsidiary of Alameda, California, US. First
released in 1987, VxWorks is designed for use in embedded systems requiring real-time,
deterministic performance and, in many cases, safety and security certification, for industries,
such as aerospace and defense, medical devices, industrial equipment, robotics, energy,
transportation, network infrastructure, automotive, and consumer electronics.
VxWorks supports Intel architecture, POWER architecture, and ARM architectures. The
RTOS can be used in multicore asymmetric multiprocessing (AMP), symmetric
multiprocessing (SMP), and mixed modes] and multi-OS (via Type 1 hypervisor) designs
on 32- and 64-bit processors.
VxWorks comes with the kernel, middleware, board support packages, Wind River
Workbench development suite and complementary third-party software and hardware
technologies. In its latest release, VxWorks 7, the RTOS has been re-engineered for
modularity and upgradeability so the OS kernel is separate from middleware, applications
and other packages. Scalability, security, safety, connectivity, and graphics have been
improved to address Internet of Things (IoT) needs.
VxWorks supports Intel architecture, Power architecture, and ARM architectures. The RTOS
can be used in multi-core asymmetric multiprocessing (AMP), symmetric
multiprocessing (SMP), and mixed modes and multi-OS (via Type 1 hypervisor) designs on
32- and 64-bit processors.
The VxWorks consists of a set of runtime components and development tools. The run time
components are an operating system (UP and SMP; 32- and 64-bit), software for applications
support (file system, core network stack, USB stack and inter-process communications) and
hardware support (architecture adapter, processor support library, device driver library and
board support packages). VxWorks core development tools are compilers such as Diab,
GNU, and Intel C++ Compiler (ICC)) and its build and configuration tools. The system also
includes productivity tools such as its Workbench development suite and Intel tools and
development support tools for asset tracking and host support.
The platform is a modular, vendor-neutral, open system that supports a range of third-party
software and hardware. The OS kernel is separate from middleware, applications and other
packages, which enables easier bug fixes and testing of new features. An implementation of a
layered source build system allows multiple versions of any stack to be installed at the same
time so developers can select which version of any feature set should go into the VxWorks
kernel libraries.
Optional advanced technology for VxWorks provides add-on technology-related capabilities,
such as:
 Advanced security features to safeguard devices and data residing in and traveling
across the Internet of Things (IoT)
 Advanced safety partitioning to enable reliable application consolidation
 Real-time advanced visual edge analytics allowing autonomous responses on Vx-
Works-based devices in real time without latency
 Optimized embedded Java runtime engine enabling the deployment of Java applica-
tions
 Virtualization capability with a real-time embedded, Type 1 hypervisor

11. Explain the terminologies Semaphores, Mailbox, pipes and Shared memory in
RTOS.(May 2016)
Mailboxes
In general, mailboxes are much like queues. The typical RTOS has functions to create, to
write to, and to read from mailboxes, and perhaps functions to check whether the mailbox
contains any messages and to destroy the mailbox if it is no longer needed. The details of
mailboxes, however, are different in different RTOSs.
Here are some of the variations that you might see:
Although some RTOSs allow a certain number of messages in each mailbox, a number
that you can usually choose when you create the mailbox, others allow only one message
in a mailbox at a time. Once one message is written to a mailbox under these systems, the
mailbox is full; no other message can be written to the mailbox until the first one is read.
In some RTOSs, the number of messages in each mailbox is unlimited. There is a limit to
the total number of messages that can be in all of the mailboxes in the system, but these
messages will be distributed into the individual mailboxes as they are needed.
In some RTOSs, you can prioritize mailbox messages. Higher-priority messages will be
read before lower-priority messages, regardless of the order in which they are written into
the mailbox.
Pipes
Pipes are also much like queues. The RTOS can create them, write to them, read from
them, and so on. The details of pipes, however, like the details of mailboxes and queues,
vary from RTOS to RTOS. Some variations you might see include the following:
Some RTOSs allow you to write messages of varying lengths onto pipes (unlike
mailboxes and queues, in which the message length is typically fixed).
Pipes in some RTOSs are entirely byte-oriented: if Task A writes 11 bytes to the pipe and
then Task B writes 19 bytes to the pipe, then if Task C reads 14 bytes from the pipe, it
will get the 11 that Task A wrote plus the first 3 that Task B wrote. The other 16 that task
B wrote remain in the pipe for whatever task reads from it next.
Some RTOSs use the standard C library functions fread and fwrite to read from and write
to pipes.
Shared memory:
In computer programming, shared memory is a method by which program processes can
exchange data more quickly than by reading and writing using the regular operating
system services. For example, a client process may have data to pass to a server process
that the server process is to modify and return to the client. Ordinarily, this would require
the client writing to an output file (using the buffers of the operating system) and the
server then reading that file as input from the buffers to its own work space. Using a
designated area of shared memory, the data can be made directly accessible to both
processes without having to use the system services. To put the data in shared memory,
the client gets access to shared memory after checking a semaphore value, writes the data,
and then resets the semaphore to signal to the server (which periodically checks shared
memory for possible input) that data is waiting. In turn, the server process writes data
back to the shared memory area, using the semaphore to indicate that data is ready to be
read.
12. Discuss about inter process communication and context switching in detail.
(Dec16) (May 2017).
Intertask or interprocess communication in µC/OS-II occurs via: semaphores, message mailbox, mes-
sage queues, tasks, and interrupt service routines (ISRs). They can interact with each other when a
task or an ISR signals a task through a kernel object called an event control block (ECB). The signal
is considered to be an event.
MicroC/OS-III
µC/OS-III is the acronym for Micro-Controller Operating Systems Version 3, introduced in 2009 and
adding functionality to the µC/OS-II RTOS.
µC/OS-III offers all of the features and functions of µC/OS-II. The biggest difference is the number of
supported tasks. µC/OS-II allows only 1 task at each of 255 priority levels, for a maximum of 255
tasks. µC/OS-III allows any number of application tasks, priority levels, and tasks per level, limited
only by processor access to memory.
µC/OS-II and µC/OS-III are currently maintained by Micrium, Inc., a subsidiary of Silicon Labs, and
can be licensed per product or per product line.
Uses in embedded systems
The uses are the same as for µC/OS-II
Task states
µC/OS-III is a multitasking operating system. Each task is an infinite loop and can be in any one of
five states (dormant, ready, running, interrupted, or pending). Task priorities can range from 0
(highest priority) to a maximum of 255 (lowest possible priority).
Round robin scheduling
When two or more tasks have the same priority, the kernel allows one task to run for a predetermined
amount of time, named a quantum, and then selects another task. This process is termed round robin
scheduling or time slicing. The kernel gives control to the next task in line if:
 The current task has no work to do during its time slice, or

 The current task completes before the end of its time slice, or
 The time slice ends.
13. Explain Task, Process and Thread with their types and examples. (DEC 2017)
Many (if not most) embedded computing systems do more than one thing that is, the
environment can cause mode changes that in turn cause the embedded system to behave
quite differently.
For example, when designing a telephone answering machine, We can define recording a
phone call and operating the user’s control panel as distinct tasks, because they perform
logically distinct operations and they must be performed at very different rates.
These different tasks are part of the system’s functionality, but that application-level
organization of functionality is often reflected in the structure of the program as well.
A process is a single execution of a program. If we run the same program two different
times, we have created two different processes. Each process has its own state that
includes not only its registers but all of its memory.
In some OSs, the memory management unit is used to keep each process in a separate
address space. In others, particularly lightweight RTOSs, the processes run in the same
address space. Processes that share the same address space are often called threads.
As shown in below figure this device is connected to serial ports on both ends. The input
to the box is an uncompressed stream of bytes.
The box emits a compressed string of bits on the output serial line, based on a predefined
compression table. Such a box may be used, for example, to compress data being sent to a
modem.
The program’s need to receive and send data at different rates for example, the program
may emit 2 bits for the first byte and then 7 bits for the second byte will obviously find
itself reflected in the structure of the code.
It is easy to create irregular, ungainly code to solve this problem; a more elegant solution
is to create a queue of output bits, with those bits being removed from the queue and sent
to the serial port in 8-bit sets.

An on-the-fly compression box.

But beyond the need to create a clean data structure that simplifies the control structure of
the code, we must also ensure that we process the inputs and outputs at the proper rates
The text compression box provides a simple example of rate control problems. A control
panel on a machine provides an example of a different type of rate control problem, the
asynchronousinput.
The control panel of the compression box may, for example, include a compression mode
button that disables or enables compression, so that the input text is passed through
unchanged when compression is disabled.
Threads
Threads are defined by executable files while drivers are defined by dynamically-
linkedlibraries (DLLs). A process can run multiple threads. All the threads of a process
share thesame execution environment. Threads in different processes run in different
executionenvironments. Threads are scheduled directly by the operating system. Threads
maybe launched by a process or a device driver. A driver may be loaded into the
operatingsystem or a process. Drivers can create threads to handle interrupts.
Each thread is assigned an integer priority. Lower-valued priorities signify higherpriority:

0 is the highest priority and 255 is the lowest possible priority. Priorities 248through 255
are used for non-real-time threads while the higher priorities are used forvarious
categories of real-time execution. The operating system maintains a queueof ready
processes at each priority level. Execution is divided into time quanta. Each thread can
have a separate quantum, which can be changed using the API. If the runningprocess does
not go into the waiting state by the end of its time quantum, it issuspended and put back
into the queue. Execution of a thread can also be blocked bya higher-priority thread.
Interrupt handling is divided among three entities:
The interrupt service handler (ISH) is a kernel service that provides the firstresponse
to the interrupt.
The ISH selects an interrupt service routine (ISR) to handle the interrupt.The ISH runs
in the kernel with interrupts turned off; as a result, it should bedesigned to do as little
direct work as possible.
The ISR in turn calls an interrupt service thread (IST) which performs most ofthe work
required to handle the interrupt. The IST runs in the OAL and so canbe interrupted by a
higher-priority interrupt.
14. Describe rate monotonic scheduling with example. (DEC 2017)
In simple words, "the task with the shortest periodicity executes with the highest
priority."
Rate-monotonic is a priority based scheduling. The scheduling scheme is pre-emptive; it
ensures that a task is pre-empted if another task with a shorter period is expected to
run.This scheme is typically used in embedded systems where the nature of the
scheduling is deterministic. When implementing RMS scheduling in applications, the
rates should be designed/picked such that utilization of the system is high.
In other words the tasks period, execution time should be designed such that all tasks get
a fair chance to execute or at least get a chance to run when the tasks are expected to run,
because the nature of the scheduling always puts priority to tasks with shorter duration.
Consider two tasks with a rate 10 ms-task1, and 20 ms-task2. As per RMS, task1 should
always execute at the rate of 10 ms as it is the task with the shorter duration. Task2 will
execute at the rate of 20 ms if the task1 is not executing. Consider a case in which the
tasks are implemented such that execution time of task1 is 10 ms and task2 is also 10 ms.
In this scenario, the task2 will never execute as the task1 will always execute at every 10
ms. So the tasks need to be designed such that other tasks at least get a chance to execute.
In this case if task1 takes 8 msexecution time and task2 takes around 10 ms, then we can
be sure that task2 at least executes at around 100 ms as it gets 2 ms free every 20 ms.Both
execution time, and rates of the task must be perused before we implement a RMS
scheme for an application.
UNIT –V
EMBEDDED SYSTEM APPLICATION DEVELOPMENT
PART B (C402.5)
1.List and explain the hardware units that must be present in the embedded systems.
(Dec2017)
Embedded Systems Hardware Components
 Power Supply. The power supply is an essential part of any embedded systems cir-
cuits. ...
 Processor. A processor is the main brain inside any embedded systems. ...
 Memory. ...
 Timers-Counters. ...
 Communication Ports. ...
 Input and Output. ...
 Application Specific Circuits. ...
Embedded Systems Hardware Components

As we know embedded systems are the combination of hardware and software. There are dif-
ferent hardware components like power supply, processor, memory, timers and counters that
make the embedded hardware.
Power Supply
The power supply is an essential part of any embedded systems circuits. An embedded sys-
tem may need a supply of 5 volts or if it is low power then maybe 3.3 or 1.8v. The supply
may be provided with the help of battery or we can use any wall adapter. It will depend on
the application need.
The power supply circuit can be designed with the help some little knowledge of electronics.
For that, we need a bridge rectifier circuit, capacitor as a filter and a voltage regulator that
provides constant output supply.
You may find a different circuit on the internet or you may try below circuit.
It is a very common circuit that produces 5 Volt at the output. You can change the voltage
regulator to 7808,7812 depending upon the output required.
Characteristics of Good Power Supply

 Stable & Smooth Output
 Proper Output Current to Drive the Load
 Perfect Power Efficiency
 Stable in Different Temperature Range
 Proper Noise Filtering
 Proper Decoupling
 Line Regulation – Fluctuation in output while input changes
 Load Regulation – Fluctuation in output voltage when load current changes
 Efficiency
 Input/Output Ripple Voltage
 Transient Response
 Allowable Dissipation
Processor
A processor is the main brain inside any embedded systems. This is a major factor that affects
the performance of the system. There are different processors available in the market. An em-
bedded system may use microprocessor or microcontroller.
The processor comes in different architecture like 8-bit, 16-bit and 32-bit. The 8-bit processor
is generally used in a small application where we need some basic computation like input and
output no heavy processing.
For higher-end application where performance matters and need some graphical user inter-
face, we use 16 or 32-bit processor.
Criteria For Selecting The Processor:
 Speed
 Unit Price
 Packaging
 Performance
 Peripheral Set
 Timer on the Chip
 Operating Voltage
 Number of I/O Pins
 Power Consumption
 Amount of RAM and ROM
 Specialized Processing Units
 Architecture 8-bit, 16-bit, or 32-bit
 Availability of Supplier for a given core
 Easy to upgrade to higher or lower power consumption mode
 Availability of Software tools like assembler, debugger, compiler, emulator and tech-
nical support
Memory
If we are using a microcontroller like AT89s51, AT89s52 or ATmega. The memory is avail-
able on-chip. We generally talk about two types of memory in the embedded systems
 Read-Only memory(RAM)
 Random Access Memory(ROM)
 Electrically Erasable Programmable Read-Only Memory (EEPROM)
RAM memory is volatile memory and used for temporary storage of the data. And the selec-
tion of it depends on the user need and the application.
The ROM memory or Code Memory. This is used for the storage of the program. Once sys-
tem powered, the system fetches the code from the ROM memory.
The EEPROM is a unique memory. The content can be erased and reprogrammed by a high
voltage pulse input. This is used to store the data by the program itself. Suppose we have a
temperature data logger. And it needs to store the data every one hour. It means we need the
data at runtime after the system is started.
The system will read temperature and store in the EEPROM memory. And it will be perman-
ent. And you can retrieve the data later.
So an embedded system developer decide which memory to use for its application.
Timers-Counters
If you are working in embedded systems you must have heard about
 What are timer and counter
 Why we use timer and counter
 What is difference between timers and counter
In some application, we need to generate some delay. Like for blinking an LED, we need a
delay. For making square pulse we need a delay.
But there is some issue when we generate the delay from the normal coding style by making
any loop running for a particular time. Definitely, this will give you some delay but the code
after this loop remains in waiting for state and delayed.
So it is not the best approach to generate the delay. For such kind of application where we
need a delay for a specific time interval without affecting the normal code execution, we use
timer and counter.
By setting some register for timer and counter using the programming we get the desired
delay. The amount of delay depends on the system frequency and crystal oscillator.
Communication Ports
Embedded systems hardware has different types of communication ports to communicate
with the other embedded devices.
Different communication ports in embedded systems
 UART
 CAN
 SPI
 I2C
 USB
 Ethernet
 RS-232
 RS-423
 RS-485
But for a small level of embedded systems microcontroller has on-chip communication ports.
For example, popular Arduino UNO board has ATmega328 IC and it has following commu-
nication port:
 UART
 I2C
 SPI
For sending data from one board to other we can use these serial protocols. But for that, we
need to program it.
Input and Output
To interact with the embedded systems we need input. The input may be provided by the user
or by some sensor. Sometimes some systems need more input or output. So the processor se-
lection will be based on I/O.
These input and output are generally divided into ports like P0, P1, P2 and P3 in 8051micro-
controllersr. And PA, PB, PC and PD in ATmega series of the microcontroller.
The I/O need to be configured for input or output based on the provided register. And for
that, we need to refer the datasheet of the manufacturer.
Application Specific Circuits
Some hardware components are common while designing the embedded systems. But some
are different and depends on the application need. Like a temperature sensor need a temperat-
ure sensor for sensing the temperature. While others hand an alcohol detector has a sensor to
detect the alcohol level.
But the remaining hardware components might be the same like
 Power Supply
 Processor
 Display Device
 Buzzer for Alert
2.Explain the hardware and software requirement for automatic digital camera.
(May 2018)
DIGITAL STILL CAMERAS
The digital still camera bears some resemblance to the film camera but is fundamentally
different in many respects. The digital still camera not only captures images, italso performs a
substantial amount of image processing that formerly was done byphotofinishers.Digital
image processing allows us to fundamentally rethink the camera. A simpleexample is digital
zoom, which is used to extend or replace optical zoom.Many cell phones include digital
cameras,creating a hybrid imaging/communicationdevice.
Digital still cameras must perform many functions:
■ It must determine the proper exposure for the photo.
■ It must display a preview of the picture for framing.
■ It must capture the image from the image sensor.
■ It must transform the image into usable form.
■ It must convert the image into a usable format, such as JPEG, and store theimage in a file
system.A typical hardware architecture for a digital still camera is shown in Figure 7.23.Most
cameras use two processors. The controller sequences operations on the camera and performs
operations like file system management. The DSP concentrateson image processing. The
DSP may be either a programmable processor ora set of hardwired accelerators. Accelerators
are often used to minimize powerconsumption.
The picture taking process can be divided into three main phases: composition,capture, and
storage.We can better understand the variety of functions that mustbe performed by the
camera through a sequence diagram. Figure 7.24 shows a sequence diagram for taking a
picture using a point-and-shoot digital still camera.Aswe walk through this sequence
diagram,we can introduce some concepts in digitalphotography.
When the camera is turned on, it must start to display the image on the camera’sscreen.That
imagery comes from the camera’s image sensor.To provide a reasonableimage itmust adjust
the image exposure.The camera mechanism provides two basicexposure controls:shutter
speed and aperture.The camera also displays what is seenthrough the lens on the camera’s
display. In general, the display has fewer pixelsthan does the image sensor; the image
processor must generate a smaller version ofthe image.When the user depresses the shutter
button,a number of steps occur. Before theimage is captured,the final exposuremust be
determined. Exposure is computed by analyzing the image characteristics;histograms of the
distribution of pixel brightnessare often used to determine focus.The cameramust also
determine white balance.Different sources of light, such as sunlight and incandescent lamps,
provide light ofdifferent colors. The eye naturally compensates for the color of incident light;
thecameramust performcomparable processing to avoid giving the picture a color cast.White
balance algorithms generally use color histograms to determine the range ofcolors and re-
weigh colors to reduce casts.The image captured from the image sensor is not directly usable,
even afterexposure and white balance. Virtually all still cameras use a single image sensor
tocapture a color image. Color is captured using microscopic color filters, each thesize of a
pixel, over the image sensor. Since each pixel can capture only one color,the color filters
must be arranged in a pattern across the image sensor.A commonlyused pattern is the Bayer
pattern [Bay75] shown in Figure 7.25. This pattern usestwo greens for every red and blue
pixel since the human eye is most sensitive togreen. The camera must interpolate colors so
that every pixel has red, green, and blue values.
FIG.Architecture of a digital still camera.

FIG.Sequence diagram for taking a picture with a digital still camera.

After this image processing is complete, the image must be compressed and saved. Images
are often compressed in JPEG format, but other formats, such as GIF,may also be used.
FIG.The Bayer pattern for color image pixels.

Image compression need not be performed strictly in real time. However,manycameras
allowusers to take a burst of images,in which case the imagesmust be compressedquickly to
make room in the image processing pipeline for the next image. A buffer memory is used to
capture the image from the sensor and store it until it can be processed by the DSP
3. With suitable diagram explain in detail about the concept of Washing machine
application. (MAY 2016) (Dec 16)
Microcontroller-Based Washing-Machine Control
A washing machine is an electronic device that is designed to wash laundry like clothes,
sheets, towels and other bedding. A washing machine is built with two steel tubs which are
the inner tub and the outer tub whose main role is to prevent water from spilling to other parts
of the machine.
Control knobs in washing machine: • Load select knob • Water inlet select knob • Mode
select knob • Program select knob
Load select knob:- load Number of clothes low medium high Load select
Water inlet select knob:- hot cold both-mixed Water inlet
Mode select knob:- Save mode, Normal mode
Program select knob:- Heavy Clothes very dirty, Normal dirty clothes ,LIGHT For light
dirty clothes Delicate For silk clothes
Operations:- • Fill:- water will be filled by the pump as per the load knob selected. •
Agitate:- The wash basket will rotate in a clockwise direction for 10 revolutions, After that
basket will stop for 2 seconds, then rotate 10 revolutions in anticlockwise direction. The
process will be continued for specified minutes in cycle table.
LED ON After completion of washing cycle, buzzer sound will be generated. Drain:- After
agitation, the water and detergent are drained. Spin:- During spin, agitator will be stationary,
only the basket will rotate at high speed. Then the moisture of clothes is removed through
holes in the inner metallic basket. Indicator:- Machine ON
Circuit diagram: Washing machine control using 8051 microcontroller
Commands for washing machine control:

4.Explain the hardware and software requirements for Automotive application.

Automotive Application:
Automotive Embedded (Computing) Systems :
▶ A computer system that is embedded into an piece of equipment or a machine to control it.
▶ Embedded systems are applied to most electric/ electronic equipment, recently.
Automotive Embedded (Computing) System
▶ A computer system that is embedded into a car to control it.
▶ An embedded computer unit is called an ECU (Electronic Control Unit).
General Features of Automotive Embedded Systems

▶ Many (as many as 100) ECUs are used for the following purposes:
▶ energy saving & low emission
▶ safety (active & passive)
▶ comfortableness, convenience, entertainment
▶ cost & weight reduction
▶ ECUs are connected with several in-vehicle networks.
▶ High reliability and safety requirements
▶ Strict real-time property required
▶ Severe environmental conditions (temperature, EMC)
▶ Severe production cost restriction !
ECUs for different systems/services have different requirements and require different
technologies.
Classification of Automotive Embedded Systems
Powertrain and Chassis Control
▶ engine, automatic transmission, hybrid control,
▶ steering, brake, suspension, Body Electronics
▶ instrument panel, key, door, window, lighting,
▶ air bag, seat belt, Multimedia (Infortainment) Applications
▶ car audio, car navigation, traffic information,
▶ electronic toll collection (ETC), back guide monitor, Integrated Systems/Services
▶ electronic stability control, pre-crash safety,
▶ parking assistance, lane keeping assistance.
Example (1):‒ ABS (Anti-lock brake system):
Function of ABS
▶ The speed of the car and the rotational speed of the wheel are monitored, and a skid is
detected.
▶ When a skid is detected, hydraulic pressure to the brake is reduced to stop the skid.
▶ The system is relatively simple, but is becoming more complex, recently. Safety
Requirement (Example) and Fail-Safe Design
▶ Continuous reduction of hydraulic pressure causes non-braking.
▶ If some fault is detected, ABS stops functioning. Then, the brake works though a skid
cannot be avoided. fail-safe design Automotive Embedded Systems 14 ABS = Anti-lock
Breaking System Hiroaki Takada
Example (2) ‒ Airbag Control Function of Airbag Control
▶ Airbag control system monitors various sensors including accelerometers and detects a
collision.
▶ If a collision is detected, the ignition of a gas generator propellant is triggered to inflate a
bag. Real-Time Constraint
▶ The trigger must be within 10-20msec. after the collision. Safety Requirements
▶ Fail-safe design cannot be applied. ! even harder than ABS.
Specific Requirements on Example Systems:
Air Bag
▶ a kind of signal processing application
▶ short response time (10msec. order)
▶ very high reliability
5. Explain the components of hardware and software units for smart card. (May 2018)
Smart card System Application:
Smart Card: Smart card is an equipment that comprise of an embedded integrated circuit chip
also known as ICC. This ICC can either be a self-asserting micocontroller or matching
intelligence with inbuilt memory or just a memory chip lone. A smart card gets connected to
the reader only when its directly physically contacted or with the aid of a remote contactless
radio-frequency interlace. With an embedded microcontroller, smart card have the idiomatic
capability to accumulate huge amount of information or data. performing their individual on-
card operations such as- mutual authentication, encryption and interact cleverly with the
smart card reader. This smart card technology harmonize with the international market
standards (ISO/IEC 14443 & ISO/IEC 7816) and is existing in a large number of forms such
as- SIMs (subscriber identity modules) employed in GSM cell phones, plastic cards, USB
based tokens, fobs, etc.

Smart Card Technology:

There are basically two types of smart cards – contact smart card & contactless smart card.
Contact Smart Card: A contact smart card ought to be introduced within a smart card
reader with a direct physical union to a conductive contact tray noticed on the surface of the
smart card, in general the surface is gold plated. Over this substantial contact points
processing of commands, data, and card status takes place.
Contactless Smart Card: A Contactless smart card as the name suggests it only needs close
immediacy with the card reader. The card reader as well as the card has antennae, and both
devices communicate with the help of RF (radio frequency) above this contactless link. Some
contactless cards also generate power for the inbuilt chip from this electromagnetic field
produced. The range of the signals are generally one-half to maximum 3 inches for non-
battery powered smart cards, this is perfect for applications like- payment that necessitates an
extremely fast card interlace and entry in a building. There are two sub categories of the
smart card namely dual-interface cards & hybrid cards.
Hybrid Card: A hybrid card comprise of 2 chips, one of them is a contact interface whereas
the other is contactless interface chip. Both the chips are not connected to each other.
Dual Interface Card: On the other hand the dual interface card has a solo chip with both
contactless & contact interface. The chips employed in all these smart cards are divided into 2
main groups, namely- memory chips & microcontroller chips.
Memory Chip: Memory chip is somewhat like a floppy disk with elective protection.
Memory chips are economically priced in cont72ast to microcontroller chips. Smart cards
that brings into play memory chips relies on the protection of the card reader for progressing
and are just perfect for circumstances that need medium or low protection. On the other hand
a microcontroller chip can include, evade and otherwise make use of data in its memory. A
microcontroller is alike a small computer with a hard drive, an input/output port and an
operating system. Smart cards which have an embedded microcontroller have the exclusive
capability to accumulate big amount of information, performing their individual on card
operations and interact cleverly with a smart card reader.

The system consists of 4 main parts:

*A smart Card which is generally a contact memory smart card which contains the
information about the individual.
*A smart card reader which is generally a contact smart card reader and is used to read
information from the card.
*A controller which receives data from the smart card reader via the RS232 interface.
A load which is a relay in this case, used to drive a motor and connected to the controller via
the relay driver IC.
*The individual inserts his/her card in the card reader.
*The card reader sends the data to the MAX 232 IC through the DB9 connector.
*The Microcontroller receives the data from the MAX 232 and is accordingly programmed to
compare the obtained information with the stored information in the database.
*If the data matches, the Microcontroller develops logic high at its output pin, connected to
the input pin of the relay driver.
*The relay driver IC accordingly develops a low logic at its output and energizes the relay.
*The common contact of the relay is now connected to the normally open contact and the
motor connected in series with the relay contacts is rotated such that the door is opened.
*In case the data doesn’t matches, the microcontroller is programmed to develop logic low at
its output pin and the relay accordingly doesn’t get energized, keeping the door shut.
*The obtained output is accordingly displayed on the LCD which shows whether the data is
matched or not.
Smart Card Applications:

Some of the most common smart card applications are: Credit cards Satellite TV
Computer security systems Electronic cash Wireless communication Government
identification Loyalty systems (like regular consumer points) Banking Smart cards can
be employed with a smart card reader associated to a PC (personal computer) to verify a user.
6. Elucidate the selection of processor and memory for any one embedded applications
with suitable diagram in detail.(May 2016) (May 2017)
Mobile phones or Smart phones are the devices which uses Embedded systems. A
Smartphone is a mobile phone with highly advanced features. Smartphones do contain
several embedded systems, like the modem core and the single-chip WiFi+Blue Tooth+GPS
solutions.
Block diagram of Mobile phone:
Selection of Processor In Smart Phones:

A processor(CPU) executes what you want your smartphone to do. Smartphones, are portable
computers that happen to have telephone capabilities built in. Underneath that amazing
touchscreen display is a full-fledged computer, responsible for telling your apps how to func-
tion, your GPS how to get you home and you who to call on the telephone. The processor is
the brains of the operation.
Some of the most popular mobile processors used in smartphone.
1. Qualcomm Snapdragon
Qualcomm is now known for its Snapdragon brand which is responsible for releasing mobile
processors and LTE modems. It is known for its performance. The processor handles
multitasking very well and can handle heavy and intensive processing which is especially
good for gaming. The presence of inbuilt Adreno graphics match the performance of
processor. Snapdragon processors also produce less heat compared to other processors.
Generally Snapdragon processors are costlier than other processors.
2. Apple Mobile processors
Apple do not manufacture any microprocessors. Instead, they make contracts with processor
manufacturing companies mainly Samsung and TSMC.
Apple A10 Fusion is the latest processor which is used in iPhone 7 and iPhone 7 Plus. A10 is
a Quad Core built on 16 nm FinFET process capable of running at 2.4GHz speeds and a Hexa
Core PowerVR GPU. Compared to its predecessor A9, A10 is twice faster and improve
graphics processing by 50%. The processor is manufactured by TSMC.
3. Nvidia Tegra
Tegra processors are built on 64 bit ARM architecture. Nvidia Tegra is considered the best
when it comes to mobile gaming. The Graphics processing is among the best among all
mobile processors. For mobile gaming, Tegra is the best.
4. MediaTek
MediaTek processors are mostly popular with Chinese manufacturer. Xiaomi, Meizu, LeEco
Le, Yu etc use them on Smartphones. MediaTek produce less heat than Qualcomm and other
processors. MediaTek processors are cheaper and so is the best option for budget devices
with good performance.
5. Samsung Exynos
Exynos 8 Octa 8890 is the latest from Exynos. The processor is equipped with Octa Core on
64-bit ARM architecture with Mali GPU. The processor is capable of running at 2.3 GHz
speed with support for 3D gaming, 4K UHD resolution support.
Selection of Memory In Smart Phones:
The memory types that our smartphone use.
Initially there are two major types of memory
1. volatile memory.
2. non-volatile memory.
1. Volatile Memory
Volatile memory is memory which lose it's content when the device is powered off.
Mainly it comes in the form of RAM. RAM stands for Random Access Memory
(meaning that each memory location has a direct and unique address that can be read
or written to independently of any other location/address).
RAM is very fast to access, and it is used for primarily one thing: the run-time mem-
ory of software applications (including the device's operating system and any applica-
tions).
There is also a secondary use for RAM, where a part of it is allocated/reserved and
used as if it was a storage drive. This is known as a RAM disk. On smartphones this is
generally visible to some applications (such as file managers) as the D-drive. As it is
volatile memory, only small temporary items/files should be stored there as its con-
tents disappear when the device is powered off.
2. Non-Volatile memory
Non-volatile memory is memory that retains it's state even if the device is powered
off. In other words, what's in non-volatile memory survives a device reboot.
Basically there are two types or non-volatile memory. The first one is ROM and the
second one is Flash-RAM.
Most of you know this memory type by it's PC name, ROM. ROM stands for Read
Only Memory and it is usually based on a flash memory. Flash memory means we can
re-program this memory to hold new data. It usually stores the OS and some other ap-
plication related parts that we do not want to be erased.
On smartphones some applications will see/show the ROM as the Z-drive. It can be
viewed/read, but not written to. And on newer devices based on Symbian 9.1/S60 3rd
Edition, access to specific directories (or "folders", if you prefer that term) is also pro-
tected from unprivileged applications.
The second kind of non-volatile memory can be called "Flash RAM" as it is still
based on the same Flash memory technology, but it is also writable (hence "RAM", as
opposed to "ROM). This kind of memory is characterized as "user [storage] memory",
or sometimes "phone memory". This is visible as the C-drive.
The C-drive is initialized with files/data that the operating system needs for various
purposes (anything that needs a writable storage location that survives powering off
the device). This is also the memory where by default things such as contacts, mes-
sages or photos are saved, when they are saved to "phone memory". Same goes for
software applications (games or whatever) and their data files, when they are also in-
stalled to "phone memory".
Another writable storage solution that is also based on Flash memory technology, are
the memory cards.
Memory Cards
Memory cards are another type of memory. There are many different kinds of memory cards;
different sizes and shapes.
 MMC - stands for MultiMedia Card type cards.
 SD Cards - A related card type is the SD (Secure Digital) card. SD cards are physi-
cally very much like MMC cards (only slightly thicker and with some extra connec-
tors/leads). However, they can be very different in function (they support additional
security features, and can even be used for peripherals; so called, SDIO cards).
 RS-MMC - A "half-size" MMC card is known as RS-MMC (Reduced Size MMC).
The first RS-MMC's and devices that supported them operated at a voltage range of
approximately 3.3V (Volts). You could call these also high-voltage RS-MMC cards.
 MicroSD - A related causing to the full size SD card that is half it's size (roughly) and
with different power consumption.
 SIM - We can actually refer to the good old SIM (Subscriber Identity Module) card as
a memory card as well if we really want too.
7. Explain the various form of memories present in an embedded system. (Dec 2017)

Common Memory Types in Embedded System:
Types of RAM
The RAM family includes two important memory devices: static RAM (SRAM) and dynamic
RAM (DRAM). The primary difference between them is the lifetime of the data they store.
SRAM retains its contents as long as electrical power is applied to the chip. If the power is
turned off or lost temporarily, its contents will be lost forever. DRAM, on the other hand, has
an extremely short data lifetime-typically about four milliseconds. This is true even when
power is applied constantly.
In short, SRAM has all the properties of the memory you think of when you hear the word
RAM. Compared to that, DRAM seems kind of useless. By itself, it is. However, a simple
piece of hardware called a DRAM controller can be used to make DRAM behave more like
SRAM. The job of the DRAM controller is to periodically refresh the data stored in the
DRAM. By refreshing the data before it expires, the contents of memory can be kept alive for
as long as they are needed. So DRAM is as useful as SRAM after all.
When deciding which type of RAM to use, a system designer must consider access time and
cost. SRAM devices offer extremely fast access times (approximately four times faster than
DRAM) but are much more expensive to produce. Generally, SRAM is used only where ac-
cess speed is extremely important. A lower cost-per-byte makes DRAM attractive whenever
large amounts of RAM are required. Many embedded systems include both types: a small
block of SRAM (a few kilobytes) along a critical data path and a much larger block of
DRAM (perhaps even Megabytes) for everything else.
Types of ROM
Memories in the ROM family are distinguished by the methods used to write new data to
them (usually called programming), and the number of times they can be rewritten. This clas-
sification reflects the evolution of ROM devices from hardwired to programmable to eras-
able-and-programmable. A common feature of all these devices is their ability to retain data
and programs forever, even during a power failure.
The very first ROMs were hardwired devices that contained a preprogrammed set of data or
instructions. The contents of the ROM had to be specified before chip production, so the ac-
tual data could be used to arrange the transistors inside the chip. Hardwired memories are still
used, though they are now called "masked ROMs" to distinguish them from other types of
ROM. The primary advantage of a masked ROM is its low production cost. Unfortunately,
the cost is low only when large quantities of the same ROM are required.
One step up from the masked ROM is the PROM (programmable ROM), which is purchased
in an unprogrammed state. If you were to look at the contents of an unprogrammed PROM,
you would see that the data is made up entirely of 1's. The process of writing your data to the
PROM involves a special piece of equipment called a device programmer. The device pro-
grammer writes data to the device one word at a time by applying an electrical charge to the
input pins of the chip. Once a PROM has been programmed in this way, its contents can
never be changed. If the code or data stored in the PROM must be changed, the current
device must be discarded. As a result, PROMs are also known as one-time programmable
(OTP) devices.
An EPROM (erasable-and-programmable ROM) is programmed in exactly the same manner
as a PROM. However, EPROMs can be erased and reprogrammed repeatedly. To erase an
EPROM, you simply expose the device to a strong source of ultraviolet light. (A window in
the top of the device allows the light to reach the silicon.) By doing this, you essentially reset
the entire chip to its initial--unprogrammed--state. Though more expensive than PROMs,
their ability to be reprogrammed makes EPROMs an essential part of the software develop-
ment and testing process.
Hybrids
As memory technology has matured in recent years, the line between RAM and ROM has
blurred. Now, several types of memory combine features of both. These devices do not be-
long to either group and can be collectively referred to as hybrid memory devices. Hybrid
memories can be read and written as desired, like RAM, but maintain their contents without
electrical power, just like ROM. Two of the hybrid devices, EEPROM and flash, are descend-
ants of ROM devices. These are typically used to store code. The third hybrid, NVRAM, is a
modified version of SRAM. NVRAM usually holds persistent data.
EEPROMs are electrically-erasable-and-programmable. Internally, they are similar to
EPROMs, but the erase operation is accomplished electrically, rather than by exposure to ul-
traviolet light. Any byte within an EEPROM may be erased and rewritten. Once written, the
new data will remain in the device forever--or at least until it is electrically erased. The
primary tradeoff for this improved functionality is higher cost, though write cycles are also
significantly longer than writes to a RAM. So you wouldn't want to use an EEPROM for your
main system memory.
Flash memory combines the best features of the memory devices described thus far. Flash
memory devices are high density, low cost, nonvolatile, fast (to read, but not to write), and
electrically reprogrammable. These advantages are overwhelming and, as a direct result, the
use of flash memory has increased dramatically in embedded systems. From a software view-
point, flash and EEPROM technologies are very similar. The major difference is that flash
devices can only be erased one sector at a time, not byte-by-byte. Typical sector sizes are in
the range 256 bytes to 16KB. Despite this disadvantage, flash is much more popular than EE-
PROM and is rapidly displacing many of the ROM devices as well.
The third member of the hybrid memory class is NVRAM (non-volatile RAM). Nonvolatility
is also a characteristic of the ROM and hybrid memories discussed previously. However, an
NVRAM is physically very different from those devices. An NVRAM is usually just an
SRAM with a battery backup. When the power is turned on, the NVRAM operates just like
any other SRAM. When the power is turned off, the NVRAM draws just enough power from
the battery to retain its data. NVRAM is fairly common in embedded systems. However, it is
expensive--even more expensive than SRAM, because of the battery--so its applications are
typically limited to the storage of a few hundred bytes of system-critical information that
can't be stored in any better way.
Table 1. Characteristics of the various memory types
Erase Max Erase

Type Volatile? Writeable? Cost (per Byte) Speed
Size Cycles
SRAM Yes Yes Byte Unlimited Expensive Fast
DRAM Yes Yes Byte Unlimited Moderate Moderate
Masked
No No n/a n/a Inexpensive Fast
ROM
Once, with a de-
PROM No vice program- n/a n/a Moderate Fast
mer
Yes, with a de- Limited
Entire
EPROM No vice program- (consult Moderate Fast
Chip
mer datasheet)
Limited Fast to read,
EEPROM No Yes Byte (consult Expensive slow to
datasheet) erase/write
Limited Fast to read,
Flash No Yes Sector (consult Moderate slow to
datasheet) erase/write
Expensive
NVRAM No Yes Byte Unlimited (SRAM + bat- Fast
tery)
8. With suitable diagram explain in detail about the concepts of smart card applications
in embedded system?(Dec 16) (May 2017)
A smart card is a special type of card like device which contains an integrated circuit chip
embedded on it. The IC chip can be a microprocessor with memory or just simple memory
circuit. In simple layman’s words, a smart card is the card with which we can exchange the
data, store it and manipulate data.
Working of smart card:
A smart card is connected to the host computer or controller via a card reader which gets in-
formation from the smart card and accordingly passes the information to the host computer or
controller.
Basic Smart Card Working System
Smart Card Reader

A smart card reader is a device to which the smart card is connected either directly or indir-
ectly using RF communication. It interfaces with the PC or a microcontroller using USB port
or RS232 serial ports. It can be a contact or contactless reader.
5 Areas of Smart Card Applications:

 Telecommunications: The most prominent use of smart card technology is in the de-
velopment of SIM card or Subscriber Identity Module. A SIM card provides unique
identification to each subscriber and provides network access to each subscriber and man-
ages its authentication.
 Domestic: The most frequently used smart card in domestic field is the DTH smart
card. This card provides authorized access to the information coming from the satellites.
In simple words the card with which we can get access to the Direct to Home TV services
is nothing but a smart card. The information is encrypted and decrypted within a smart
card.
 Ecommerce and Retail: Smart card can be used to store information like a person’s
account details, the transaction details and can be used in purchasing goods online by
acting as a credit card. Some retailers can also use smart cards to store points for a
particular customer and provide necessary incentives to repeated customers.
 Banking Application: The most prominent use of smart card in banking application
is the replacement of the traditional magnetic stripe based credit or debit card. An ex-
ample is the MasterCard and VISA.
 Government Applications: Smart cards are being used by Government to issue iden-

tity cards to individual, which contains all the details of the individual. An example is the
recently started Adhar card scheme in India.

 Secured Physical access: Smart cards can be used by Organizations or differed pub-

lic areas to provide authorized access to the employees (members of the organization) or
other persons to the secured areas. The smart card generally contains identity details of the
individual which is scanned and checked.
9. Explain the synchronization model of smart card.

A smart card is a special type of card like device which contains an integrated circuit chip
embedded on it. The IC chip can be a microprocessor with memory or just simple memory
circuit. In simple layman’s words, a smart card is the card with which we can exchange the
data, store it and manipulate data.
Working of smart card:
A smart card is connected to the host computer or controller via a card reader which gets in-
formation from the smart card and accordingly passes the information to the host computer or
controller.
Basic Smart Card Working System
Smart Card Reader

A smart card reader is a device to which the smart card is connected either directly or indir-
ectly using RF communication. It interfaces with the PC or a microcontroller using USB port
or RS232 serial ports. It can be a contact or contactless reader.

Synchronization model of smart card
Software components needed for the smart card system are Boot-up, system initialization and
embedded system features. It needs a secure three layered file system called Smart card
secure file system. This Smart card secure file system is needed for storing the files.
Connection establishment and termination is provided by TCP/IP port connection. Then
cryptographic algorithm is used for the added features like host connection. OS is stored in
the protected part of the ROM. Host and card authentication are also needed for the smart
card. Optimum code size and multidimensional array are needed to save the data.
The following steps are executed in sequence,
1) On card insertion into a reader or when brought in proximity to the reader, extract charge
from the radiation to generate power supply for the card.
2) Executes codes for a boot up- Reset Task.
The OS is initiated, timer is started & three tasks – task_ReadPort, task_PW, task_ Appl
are created.
task_ReadPort requests the bank allotted PIN to the user. Another request for host PIN is
requested.
3) Upon request of the PIN ID, the same is encrypted & sent to the transceiver for
authentication.
4) task_ Appl runs afterauthentication and one of the following applications can take place,
i) modify password ii) print mini statement iii) cash withdrawal and so on.
10.Explain in detail about the hardware and software parts of chocolate vending
Machine. (May 2018).
Automatic Chocolate Vending Machine (ACVM)

The purpose of ACVM is to build a system from which children can automatically purchase
the chocolates, and the payment is by inserting the coins to the appropriate denomination
coin-slot.
Inputs
Coin slot to insert the coins of different denominations and the keypad to enter the user
commands.
Signals, events and Notifications
An interrupt is generated at each port after the coin is received in the coin slot. Each port
interrupt starts an Interrupt Service Routine (ISR), which increases value of amount collected
by corresponding rupees (1, 2, 5 or 10). A notification is generated for each selection in the
menu.
Outputs
The display is used to show the GUIs, time and date, advertisements, welcome and thanks
messages. Chocolate and signal (IPC) to the system that subtracts the cost from the value of
amount collected.
Functions of the system
A child (user) sends commands to the ACVM using a GUI (graphic user interface). GUI
consists of the LCD and keypad units. At first, in the Coin insertion slot, the child inserts the
coins ( Task_Collect through Port_Collect) for the cost of chocolate and the machine delivers
the chocolate in the delivery slot. If the coins are not inserted as per the cost of chocolate for
a reasonable amount of time, then all coins are refunded (Task_Refund through
Port_Refund). If the inserted coins amount is more than the cost of chocolate, the excess
amount is refunded along with chocolate (Task_ExcessRefund through Port_ExcessRefund).
If the chocolate is of different rupees, then the port is assigned to each rupee, and then the
interrupt is sent to the corresponding port (Task_ReadPorts through Port_Read). After that
chocolate is delivered through the delivery slot (Task_Deliver through Port_Deliver). The
coins for the chocolates purchased collect inside the machine in a collector channel
(Task_Collect), so that owner can get the money, again through appropriate commands using
the GUI (Task_Display). USB wireless modem enables communication through Internet to
the ACVM system owner.
ACVM Hardware
The heart of an ACVM is a Microcontroller or ASIP (Application Specific Instruction Set
Processor). The 8051 can be used as the microcontroller and MUCOS the RTOS used in the
ACVM. ACVM specific hardware is required to sort the coins of different denomination
using coin sorter and the main Power supply needed is 220V 50Hz or 110V 60Hz. Internal
circuits need a supply of 5V 50mA for electronics and 12V, 2A for mechanical systems. By
programming the 8051 timer, the 1s resolution timer is obtained. A RAM is used for storing
temporary variables and the stack, and a ROM for application codes, and the RTOS codes for
scheduling the tasks. It also has flash memory for storing user preferences, contact data, user
address, a user date of birth, user identification code and answers to frequently asked
questions (FAQs). Timer and Interrupt controller are also needed to control the process of
ACVM. It has a TCP/IP port (Internet broadband connection) to the ACVM for remote
control and for providing the system status reports to the owner. It also has an ACVM
specific hardware and a power supply.
ACVM Software
Software is required to handle the following:
Read input from keypad, display text/graphics, control coins reader, and control delivery port
(to deliver the chocolate). In addition to these, we also need the TCP/IP stack communication
for remote control, and an RTOS (say, MUCOS), to run the ACVM software.

Ee6602 Embedded Systems LT P C 3 0 0 3

Uploaded by

Copyright:

Available Formats

Ee6602 Embedded Systems LT P C 3 0 0 3

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Ee6602 Embedded Systems LT P C 3 0 0 3

Uploaded by

Copyright:

Available Formats

EE8691-Embedded Systems Department of EIE 2021-2022

EE6602 EMBEDDED SYSTEMS LT P C 3 0 0 3

Able to demarcate hardware and software fault of washing

On completion of this course, the students will be,

MAPPING OF CO AND PO WITH CORRELATION LEVEL1/2/3

As an example, consider the following problem:

Add 127, 29 and 40 and print the square root.

EMBEDDED PROCESSOR IN A SYSTEM

An embedded system processor chip or core can be one of the following.

St. Joseph’s College of Engineering 5

Table 1.1lists the important microprocessors used in the embedded

St. Joseph’s College of Engineering 7

Embedded System Design Process

St. Joseph’s College of Engineering 8

An embedded system has three main components:

(2) “An embedded system is a microcontroller-based, software-driven, reliable, real time

the major components of an embedded system hardware

An embedded system has three main components:

(2) “An embedded system is a microcontroller-based, software-driven, reliable, real time

the major components of an embedded system hardware

St. Joseph’s College of Engineering 13

6.(i)Explain an Embedded System on chip and in VLSI circuit.

6. (ii)Explain the details about exemplary Embedded System

7.ii) Explain the various types of Embedded Systems. (May 2018)

Types of embedded system

St. Joseph’s College of Engineering 15

Mobile embedded system:

 Personal digital assistants (PDA)

An embedded system is characterized by the following: (I) Real-time and mukirateoperaticns-

St. Joseph’s College of Engineering 17

ASSEMBLY AND LINKING

St. Joseph’s College of Engineering 18

St. Joseph’s College of Engineering 19

Processor selection for an embedded system

Now let us discuss each of them in detail.

St. Joseph’s College of Engineering 21

Digital Signal Processors

WATCH DOG TIMER

St. Joseph’s College of Engineering 25

St. Joseph’s College of Engineering 26

TARGET HARDWARE DEBUGGING:

RS485 SERIAL INTERFACE

Cabling Single ended Single ended multi-drop Multi-drop

No. of Devices 1 transmitter 1 transmitter 32

Communication Full duplex Full duplex, Full duplex,

St. Joseph’s College of Engineering 29

ii)How to transfer a byte of data using I2C protocol?

St. Joseph’s College of Engineering 31

o Sender listens while sending address.

St. Joseph’s College of Engineering 32

The CAN FD protocol allows payloads up to 64 byte. Additionally, it supports an optional

St. Joseph’s College of Engineering 33

CAN Data Frame

St. Joseph’s College of Engineering 34

Comparison between Serial and Parallel Transmission

St. Joseph’s College of Engineering 35

St. Joseph’s College of Engineering 36

St. Joseph’s College of Engineering 37