Non Isolated
Non Isolated
Non Isolated
References
– AT
– ATX/NLX
AT type SMPS
Front side power connector to SMPS
Efficiency :
Brownouts (Sag): The under voltage condition The high load items like air
conditioners, welding machine, motor etc draw to much current that the AC
voltage level drops.
power supply will fall out which resulting in intermittent system operation.
file may be lost or corrupted on the hard drive.
ATX/NLX type SMPS
Power Supply problems
Surge: small over voltage conditions that take place over relatively long
periods and regulate power to a desired level excess energy must be
switched (in SMPS).
4. You suffer chronic or frequent hard drive failures or file access problems.
becomes corrupted.
7. The PC behaves erratically when other high-energy devices are turned on.
2 actuator mechanism
3.Contacts:allow current
6 calibration screw:
Uninterrupted Power Supply (UPS)
An UPS provides a back up power supply when there is a power failure from
AC mains.
Uninterrupted Power Supply (UPS)
On-line UPS.
Outline (I)
40
Outline (II)
= (vOiO)/(vgig) RL vO
vg RL vO vg
iO ig
vE
vE
Av - vO/vg Av -
Feedback loop Vref Feedback loop Vref
ig Q iO S
ig iO
vg RL vO
vg RL vO
vE -
Av vE -
PWM Av
Feedback loop Vref
Feedback loop Vref
Linear
Switching (provisional)
Features:
vO_avg
vO 100% efficiency
vg
Undesirable output voltage
waveform
t
8/16/2022 MIT MANIPAL 47
Introducing the switching DC/DC conversion (I)
S vO
ig iO vO_avg
vg
vg RL vO t
The AC component must be
vE -
PWM Av removed!!
Feedback loop Vref
S
ig iO
S
ig iO
Filter
vg RL vO
vg RL vO
C filter
PWM Av -
C filter vE
Vg VO Feedback loop Vref
t
Basic switching DC/DC
It doesn’t work!!! converter (provisional)
8/16/2022 MIT MANIPAL 48
Introducing the switching DC/DC conversion (II)
S iL
ig iO S
ig iO
Filter L
vg RL vO LC filter
vg RL vO
C
PWM Av -
vE LC filter
S iL
ig iO
+ L + vD VO
vD RL vO Vg
vg iD C
D - -
t
LC filter
Basic switching DC/DC converter
8/16/2022 MIT MANIPAL 49
Introducing the switching DC/DC conversion (III)
iS iL
S iL iO
iO ig
ig
L
S + L C +
+ + vD vO
vD vO vg RL
vg iD RL iD D - -
D - C -
iS iL iL
ig iO iO
+ L C
S + L C + +
vD vO vD RL vO
vg RL -
iD D - -
LC filter
vD
vg vD vD_avg = vO
vO vg
t
t
dT The AC component is
T
d: “duty cycle” removed by the filter
Step 1: Main waveforms. Remember that the output voltage remains constant
during a switching cycle if the converter has been properly designed
ig vS iS iL iO
+ -
Driving signal
iD + L C +
S vD vO
vg RL t
D - -
iL
iL iO
L
t
S on, D C +
vO iS
off vg RL
-
t
During dT
iL iO iD
t
S off, D L C +
RL vO dT
on -
T
During (1-d)T
8/16/2022 MIT MANIPAL 52
Analysis for the Switch Closed iL iO
S on, D VL C +
RL vO
off vs -
Rearranging
During dT
The change in current while the switch is closed is
computed by modifying the preceding equation.
2
8/16/2022 MIT MANIPAL 53
iL iO
S off, D L C +
RL vO
on -
During (1-d)T
ig vS iS iL iO Summary
+ -
iD + L C + Driving signal
S vD vO
vg RL t
D - -
vD
vg
vO = d·vg (always vO < vg)
t
vSmax = vDmax = vg iL iO
iL_avg = iO = vo/RL t
iS
ig_avg = iS_avg = d·iO DiL
iD_avg = iL_avg - iS_avg = (1-d)·iO t
DiL = vO(1-d)T/L iD
t
iL_peak = iL_avg + DiL/2 = iO + vO(1-d)T/(2L) dT
iS_peak = iD_peak = iL_peak T
8/16/2022 MIT MANIPAL 61
8/16/2022 MIT MANIPAL 62
Introducing another analysis method (I)
ig L1 C1 iD D
+ -
iS iL2 R
+
Vg VO
L2 C2 -
S
The average voltage across an inductor is zero. Else, the net current
through the inductor always increases and, therefore, steady-state is not
achieved
The average current through a capacitor is zero. Else, the net voltage
across the capacitor always increases and, therefore, steady-state is not
achieved
+
L vL_avg = 0
Circuit in
Vg
-
steady-state
C iC_avg = 0
Kirchhoff’s current law (KCL) is not only satisfied for instantaneous current values, but
also for average current values
Kirchhoff’s voltage law (KVL) is not only satisfied for instantaneous voltage values, but
also for average voltage values
ig Input power:
iO
Pg = vgig_avg
Switching-mode +
vg RL vO Output power:
DC/DC converter -
PO = vOiO = vO2/RL
Power balance:
Therefore: vgig_avg = vO2/RL
Pg = PO
When the switch is closed, the diode is off, and the circuit is as shown in
Fig. The voltage across L1 for the interval DT is
S on, D off, t
L
during dT vg iD
t
i L + vL - iO dT
T
S off, D on, L C +
during (1-d)T vO
RL
- From Faraday’s law:
DiL = vgdT/L
8/16/2022 MIT MANIPAL 89
Steady-state analysis of the Boost converter in CCM (II)
ig + v L - i L - vD + iO Summary
L iC Driving signal
iS D iD +
vg
+ RL vO t
S vS C -
- vD
vO
iL+ dT
S off, D on, C - -
vL vO T
during (1-d)T + RL
L - +
From Faraday’s law:
Discharging stage DiL = vgdT/L
8/16/2022 MIT MANIPAL 92
Steady-state analysis of the Buck-Boost converter in CCM (II)
ig i
+ vS - S
i D + vD - iO Summary
iL Driving signal
+ D - -
S vO t
vL + RL +
vg L C
- vD
vO + vg
iD
iS_avg = ig_avg = d·iL_avg = d·vo/[RL(1-d)] iO
L + + Complementary
S vO
vg C - RL
D - switches + inductor
Buck
S D
L d 1-d
D + + + +
vO vO
vg - RL vg C - RL -
S C - L
Boost
D +
- vO Voltage source
S
vg L C + RL -
L ig_avg iO
+ +
S vO
vg C - RL
D - +
RL vO
Buck vg -
ig iO 1:N
DC Transformer
L D + +
vO
vg S C - RL -
Buck-Boost
8/16/2022 MIT MANIPAL 98
Comparing basic DC/DC converters (II)
Generalized study as DC transformer (II)
ig_avg iO
+
RL vO
vg -
1:N
DC Transformer
ig iS vS iO
+ -
iD + +
S vD RL vO
vg -
D -
DC/DC converter
4 A (avg) 2A
D vS_max = vD_max = 75 V
- -
S 50 V iS_avg = 4 A
25 V L C + RL +
iD_avg = 2 A
100 W Buck-Boost, 100% efficiency
iL_avg = 6 A
FOMVA_S = 300 VA
Higher electrical stress in the case of Buck- FOMVA_D = 150 VA
Boost converter
Therefore, lower actual efficiency
8/16/2022 MIT MANIPAL 102
Comparing basic DC/DC converters (VI)
6.12 A (avg) L 5A
vS_max = vD_max = 60 V
1.12 A D +
iS_avg = 1.12 A
+
(avg) 60 V iD_avg = 5 A
50 V S C - RL -
iL_avg = 6.12 A
300 W Boost, 98% efficiency
FOMVA_S = 67.2 VA
FOMVA_D = 300 VA
D
- -
S 60 V
L C + RL + vS_max = vD_max = 260 V
20 - 200 V
iS_avg_max = 20 A
300 W Buck-Boost, 75% efficiency
iD_avg_max = 5 A
Remember previous example: iL_avg = 25 A
FOMVA_S = 67.2 VA FOMVA_S_max = 5200 VA
FOMVA_D = 300 VA FOMVA_D = 1300 VA
L D + +
vg vO
S C - RL -
Boost
L idevice
S L
D MOSFET S1
Diode S2
L
S1
S2 vdevice
8/16/2022 MIT MANIPAL 107
Synchronous rectification (II)
In converters without a transformer, the control circuitry must provide
proper driving signals
In converters with a transformer, the driving signals can be obtained
from the transformer (self-driving synchronous rectification)
Nowadays, very common technique with low output-voltage Buck
converters
L
L S2 + +
S1 S1 vO
vg C - RL -
vO D
S2
Synchronous Buck
Q’ -
PWM Av
Q Vref
Feedback loop
ig iS vS
iRC
+ -
iD + + +
S vD v
vg C - RL - O
D -
t t
8/16/2022 MIT MANIPAL 109
Input current and current injected into the output RC cell (II)
ig iRC
ig iRC
L + +
S vO
vg C - RL
t D - t
Noisy Buck Low noise
ig iRC
ig L D +
iRC
+
vO
vg S C - RL -
t t
Low noise Boost Noisy
ig iRC
ig D
-
+
vO
iRC
S -
vg L C + RL
t t
Noisy Buck-Boost Noisy
8/16/2022 MIT MANIPAL 110
Input current and current injected into the output RC cell (III)
LF + L + +
S vO
vg CF - C - RL
D -
Filter Buck
ig iRC
L D LF
+ + +
vO
vg S CF - C - RL -
Boost Filter
ig iRC
LF D LF
+ - - -
CF S CF R vO
vg - + C + L +
L
Filter
Buck-Boost Filter
8/16/2022 MIT MANIPAL 111
Four-order converters (converters with integrated filters)
ig L1 C1 iD D Same vO/vg as Buck-Boost
-
iS
+
vC1 iL2
RL
Same stress as Buck-Boost
+
vO vC1 = vg
vg
S
L2 C2 -
Filtered input
SEPIC ig L1 C1 iL2 L2
+ Driving signal
S RL vO t
vg D -
dT
DC/DC converter
T
RL_1
iL
iL_avg
Decreasing load
t Operation in CCM
RL_2 > RL_1
iL
iL_avg
t
RL_crit > RL_2 Boundary between CCM
iL iL_avg
and DCM
t
It corresponds to RL = R L_crit
8/16/2022 MIT MANIPAL 114
DC/DC converters operating in DCM (III)
What happens when the load decreases below the critical value?
t
iL
After decreasing the
switching frequency
t
iL After decreasing the
load (increasing the
load resistance)
t
Vo D2
Vd 0.25I o
D2
I LB ,max
1 T DiL, pp Vo (1 D)
DQ
2 2 2 8 f sw2 L
DQ Vo (1 D)
Dvo , pp
C 8 f sw2 LC
Vo (1 D ) (5)(1 0.5)
DiL, pp 6
0.38 A
f sw L ( 2 10 )( 33 10 )
5
DQ Vo (1 D ) (5)(1 0.5)
Dvo , pp 6 6
24 mV
C 2
8 f sw LC 8( 2 10 ) (33 10 )(10 10 )
5 2
N=d 1 d
N= N=
1-d 1-d
2
M= d
4d2 M=
4k 1+ 1+
1+ 1+ 2 k k
d M=
2
kcrit = (1-d)2
kcrit = (1-d) kcrit = d(1-d)2
kcrit_max = 1
kcrit_max = 1 kcrit_max = 4/27
k = 2L/(RT)
8/16/2022 MIT MANIPAL 136
DC/DC converters operating in DCM (X)
CCM versus DCM
Driving signal Driving signal
t
vD t vD
dT t dT t
T T
When the switch is closed, the diode is off. The voltage across L1 for
the interval DT is
When the switch is open, the diode is on. Kirchhoff’s voltage law
around the outermost path gives
for the interval (1 D)T. Since the average voltage across an inductor is
zero for periodic operation,
Solving for average inductor current, which is also the average source
current,
For L2, the average current is determined from Kirchhoff’s current law at the
node where C1, L2, and the diode are connected.
The output stage consisting of the diode, C2, and the load resistor is the
same as in the boost converter, so the output ripple voltage is
The resistances in the inductors and the capacitors can also have large
effects on the converter efficiency and output ripple. Inductors with lower
series resistance allow less energy to be dissipated as heat, resulting in
greater efficiency (a larger portion of the input power being transferred to
the load).
Capacitors with low equivalent series resistance (ESR) should also be used
for C1 and C2 to minimize ripple and prevent heat build-up, especially in C1
where the current is changing direction frequently.
Like the buck–boost converter, the SEPIC has a pulsating output current.
The similar Ćuk converter does not have this disadvantage, but it can only
have negative output polarity, unless the isolated Ćuk converter is used.
•Since the SEPIC converter transfers all its energy via the series capacitor,
a capacitor with high capacitance and current handling capability is
required.
•The fourth-order nature of the converter also makes the SEPIC converter
difficult to control, making it only suitable for very slow varying
applications.