What are the files required for doing the scan insertion

Tessent Scan Inputs and Outputs

Tessent Scan uses the following inputs:

• Design (netlist) — A Verilog gate-level netlist needs to be provided as input.
• Circuit Setup (or Dofile or Tcl file) — This is the set of commands that gives the tool
information about the circuit and how to insert test structures. You can issue these commands
interactively in the tool session or place them in a dofile or Tcl file.
• Library — The Tessent Cell library contains descriptions of all the cells the design uses. The
library also includes information that the tool uses to map non-scan cells to scan cells and to
select components for added test logic circuitry.
• Input TCD File — If there are pre-existing scan segments that are described in a *.tcd_scan
file, then you need to provide them as input to Scan Insertion. You can read them in using the
set_design_sources command. The full syntax of tcd_scan file is found in Scan section of the
Tessent Shell Reference Manual. Also, if there are CTL models for pre-existing scan segments,
these can be converted using stil2mgc and then read in.
• Test Procedure File — This file defines the stimulus for shifting scan data through the defined
scan chains. This input is only necessary on designs containing pre-existing scan circuitry or
requiring initialization for test mode (test setup).
Tessent Scan produces the following outputs:
• Design (Netlist) — This netlist contains the original design modified with the inserted test
structures. The output netlist format is gate-level Verilog.
• TCD (Tessent Core Description) — This file contains all the Scan modes that were specified
during scan insertion. This file is used by ATPG tool to generate patterns. If any .tcd files from a
previous insertion pass or from a lower level core are read in, then the scan modes are appended
to the input *.tcd file and written out into the tsdb_outdir directory.

Scan Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Chain Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unwrapped Cores Versus Wrapped Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-Existing Scan Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-Existing Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The cell library file describes library cells to be used during RTL generation or test logic insertion, and also for test
and simulation.

SETUP> set_context dft –scan

# SETUP
# Set the context
>set_context dft -scan
# Read the verilog
>read_verilog ../design/cpu.v
# Read the library
>read_cell_library ../library/adk.tcelllib
>read_cell_library ../library/ram.lib
>set_current_design cpu
# Add clocks in the design
>add_clock 0 clk1
>add_clock 0 clk2
>add_clock 0 clk3
>add_clock 0 clk4
>add_clock 0 ramclk
//RUN DRC
>set_system_mode analysis
# Specify constraints to stitch up scan chains
>set_scan_insertion_options -chain_count 100
>analyze_scan_chains
>report_scan_chains
>insert_test_logic -write_in_tsdb On
>report_scan_chains
With Tessent Scan, you can analyze the design, allocate new scan chains based on design and user constraints, and
introspect the scan chain distribution and balancing before performing the actual scan insertion on the design.

set_cell_model_mapping
set_test_logic.
Scan Insertion:

1).Explain scan insertion steps?

2).what are the basic things that needs to taken care for Scan Insertion?

3).what are the DRC Violations that u have faced during Scan Insertion and how did you fix
those ?

4).what is test point Insertion? Can you tell and explain one TestPoint Insertion scenario?

5).Some Questions on design complexity like what was the gate and flops count of yours recent
project?

6).Explain Decompression logic?

7).what is sdc file and what does it contains?

8).what is the use of clock gaters in design?

9).Draw the internal diagram of clock gating cell?

10).what is use of latch in clock gating cell?

11).How glitches can be remove through latch?

12).Draw the muxed flip flop and explain?

13).Take three scan flop and stitch it and explain the scan operation?

14).How you will decide the number of scan chains for your core?

15).what is lockup latch and why we use it?

16).what are Manufactured defects?

17).what is clock latency?

18).will latency effect data shifting in scan chain?

19).consider two flop of .2sec and 0.3 sec latency how do you connect the flops in scan chain?

20).write the RTL coding for an asynchronous and a synchronous Flip-flop?

21).Implement a 2 by 1 Mux through gates?

22).How you will decide the compression ratio for the core?

23).what all information you will ask from designer for smooth scan insertion?

24).what all ctls you read while scan insertion?

25).Draw and explain the Structure of the compressor and decompressor circuit?

26).why we don't go for higher compression ratio like 90-100%?

27).How many scan clocks you had for your core?

28).which one is better having single or multiple scan clock?

29).what all things you need to take care while/before inserting on chip clock controller circuit?

30).In which path we insert the lockkup latch, data or clock path?

31).How you will resolve the combinational feedback loop issue in design if present?

32).why we don't connect the capture flop's clock to the lockup latch?

33).why we use flop trays in design?

34).what is the purpose of DFT?

35).why we need scan? or why we convert normal D flip flops to scan flops in design?

36).what work around you can do if you don't have scan equivalent for some flops in design
while scan insertion?

ATPG:

37).Did you worked on Coverage Analysis? How did you improved your Coverage?

38).what are the ATPG Untestable faults?

39).How much test coverage you got in your last project?

40).what are the input files required for scan insertion and ATPG and what all output files we get
after completing scan insertion and ATPG?

41).what is Stuck at fault?

42).How many faults sites are there for a 2 input AND Gate?
43).what is the difference between transition and path delay fault model?

44).what the SPF/test procedure file contains?

45).what are the different types of fault classes?

46).what is fault collapsing?

47).For a given fault coverage the number of patterns for TFT is more than the patterns
generated for Stuck-at-faults. Why so?

48).How the 2 pulses are generated for transition faults?

49).can you draw the on chip clock controller structure diagram?

50).what all DRCs you faced during ATPG?

51).what is the difference between launch on capture(LOC) and launch on shift(LOS)?

52).which one is widely used in industry? which one is better LOS or LOC?

53).How you will improve transition faults test coverage?

54).why we do IDDQ testing?

55).what is pseudorandom pattern and why it called pseudorandom?

56).Have you ever seen condition statements in spf and how they work?

57).If we have cover all transition faults along a path(critical) already then should we check the
path delay also for that path?

58).what is the test coverage and fault coverage?

59).what is redundant fault explain with example?

60).what are parallel patterns how they work explain with the help of a scan chain?

61).what are the DRCs that can result in low test coverage?

2).what are blocked and unused faults?

63).How the test data valume and tester time reduction happens with compression?

64).what are advantages of modular atpg?

65).How DFT vectors are different from Functional vectors?

66).why we measure PO(primary output) before capture clock?

67).How the IDDQ test vectors is different from stuck at test vectors?

68).How increasing sequential depth helps in improving test coverage?

Simulation:

69).How you will timing simulation debugging for uncompessed and compressed chains?

70).Suppose if you get hold violation how you fix that?

71).Have you ever opened sdf and seen?

72).what is setup and hold?

73).what violation will occur if step and hold time not maintain properly?

74).write the setup slack equation?

75).have you ever done post silicon debug?

6).if scan chain is broken then how you will debug?

77).if the clock skew is more than half clock cycle then how you will avoid the hold violation?

Miscellaneous:

78).why we do MBIST Insertion and verification? Which tool you are using?

79).what is P1500 how it works and useful?

80).How wrapper cell works draw its structure?

81).How you do extest using P1500 and tell what happens in its wrapper cell?

82).Do you know MBIST and how it works?

83).what are typical memory faults?

84).what is neighborhood and coupling faults how these faults are different from each other?

85).which tool did you use for MBIST insertion?

86).what checks(rules) ET checker do?

87).Draw Boundary scan cell and explain its functionality?

89).Explain Sample and Preload operation?

90).what is JTAG? why it is used? How I/O testing happens with JTAG?

91).what are the manadatory instructions in JTAG?

92).what are the default values of JTAG signals(tms,trstn,tdi,tdo,tck)?

93).For an INOUT port how many boundary scan cells you require?

94).Draw and explain the TAP state machine with tms values?

95).why we give tdo value at negedge in JTAG?

96).which instruction is having fix opcode in JTAG?

97).what is the significance of 'pause' state of TAP state machine?

98).How the 'mode' signal(for boundary scan cell) gets generated in JTAG?

99).Explain 8051 microcontroller?

100).How many Timers and memory size of 8051?

SDC ?

SDC stands for Synopsys Design Constraints as it was a format that was pioneered by
Synopsys for specifying timing requirements for the synthesis tool “design compiler “ and
later extended to its own and other industrial tools as well in order to have consistency.

Purpose of SDC ?

Primarily when we talk about timing in most cases its a simple question of answering what is
the minimum and maximum arrival time permitted to a data with respect to a trigger
(clock,reset).
SDCs in particular , are used to specify this timing intent for a design that when validated
against a timing tool provide the user with paths/sections of design that do not comply or
are failing.

 People in STA/Synthesis often elaborate setup, hold, recovery, removal, clock

gating, data2data checks etc. but at the basic level all these checks are nothing but
min/max arrival checks with a difference arising in variation of phase of the trigger
signal. This definition is a bit difficult but more comprehensive.
Parts/Class of SDC Statements?

Strictly speaking there are just 2 classes in SDC:

1. Quantitative Classes : Which specify a constraining number and a variable.

a. create_clock/generated_clock → for period and latency (float)
b. set input/output/min/max → delay/transition (float)
c. set multicycle path → valid periodic phase change (integer)
d. set source/network latency → valid aperiodic phase change (float)
e. set clock uncertainty → Margin (often jitter margin + extra) (float)
f. set output load/set input transition → Interface modeling (float)
g. set clock gating setup/hold → for clock clipping checks (float)
2. Qualitative Classes : Which generally specify exceptions independent of any
qualitative class variable and its value. These will always remove some timing paths
if applied.
a. set case analysis (boolean)
b. set false path
c. disable timing arcs
d. stop clock propagation
e. set clock group
Qualitative Class + multi-cycle path definitions constitute the exception statements in SDC.

Use of SDC ? Yes it is different from the actual purpose !

Primary purpose of SDC is to provide common format of timing validation model. However,
often SDCs are used to exploit the timing information in order to perform power and area
optimizations.

Synthesis, placement and routing are the best example of this use case. Once a timing is
met at a node , then recovery of power and area can be initiated at that node provided
timing remains met as per SDC intent. A good analogy would be comparing timing intent as
your room temperature and your AC, a synthesis tool like DC or Genus. Once the desired
temperature is met , you can reduce your power consumption by simply stopping the AC for
some time.
A secondary use of SDC also happens to be at DFT (design for testing) and DRC checks like
IR drop and EM. Basically they use the timing intent from the SDC to import the paths,
clocks and model switching/transition estimates. This is also one of the reasons that DFT
often asks you to put multicycle paths instead of false paths as not only optimization but
DFT coverage is also dependent on the SDC specification.

 So the industry moved to a design for test (DFT) approach where the design was
modified to make it easier to test. The approach that ended up dominating IC test is
called structural, or “scan,” test because it involves scanning test patterns into internal
circuits within the device under test (DUT). The design’s flip-flops are modified to allow
them to function as stimulus and observation points, or “scan cells” during test, while
performing their intended functional role during normal operation.

What is synthesis RTL?

In computer engineering, logic synthesis is a process by which an abstract specification

of desired circuit behavior, typically at register transfer level (RTL), is turned into a
design implementation in terms of logic gates, typically by a computer program called a
synthesis tool.

Lock-up Latches play an important role in fixing timing problems especially for hold timing
closure. A lock-up latch is a transparent latch used to avoid large clock skew and mitigate
the problem in closing hold timing due to large uncommon clock path. Lock-up latches are
used in between the two scan flops having large hold failure probability due to uncommon
clock path so that there is no issue in closing timing in a scan chain across domains in scan-
shift mode.

From timing perspective lock-up latches can be the best solution to avoid large uncommon
path between the clocks of two flops. But Lock-up latches are not always help; they can be
 the cause for congestion issue after scan stitching in designs containing both EDT and
LBIST.

Lock-up Latch insertion during scan stitching:

1- Concatenation of Scan Chains of Different Clock Domains: When there is need of
concatenation of scan chains of different clock domains Lock-up latch is inserted in order to
mitigate large clock skew and uncommon path.

Fig.1: Lock-up Latch connecting two different Scan chains

2- Flops within same domain but are far apart to each other: When flops are sitting
far apart but within the same clock domain, so to avoid large clock skew and uncommon
path lock-up latch is inserted in between.

Fig.2 Lock-up Latch connecting far apart flops within same clock domain
Issues due to Lock-up Latch insertion:

 Lock-up latches on the scan path act as “break points” across which flops cannot be
reordered.
 Due to lock-up latch on scan path, tool is not able to improve the chain length by reordering
in an efficient manner.

 Whenever there is a lock-up latch in the chain, the scan chain is broken into two smaller
segments. These segments in turn have their own start-end points which are fixed and
cannot be reordered. This results in longer scan chain wire length.

 Poor Scan reordering substantially increases the length of scan chain and hence the
congestion which unnecessary increases the capacitance of scan flops outputs i.e.more
loading of Q pin which leads to more chip power dissipation.

All these issues give rise to one major issue that is Congestion.
Role of Lock-up Latches in Congestion:

Lock-up latches inserted on scan paths limit the reordering capability, so the chains which
are supposed to get short in terms of scan chain wire length get restricted due to these
“break points”. Lock-up latches between two flops which are far apart within the same scan
chain and same clock domain breaks the chain in two smaller segments. These break points
don’t allow scan reordering and efficient chain length improvement, hence the long wire
length and criss-crossing of chains results in congestion.

When there is stitching of flops with memories, tool inserts the lock-up latches in such a
way that the chain gets stitched in haphazard manner with long scan chain wire length
causing congestion issue in the design.

When there is a lock-up latch just before the last element in the chain, it breaks the chain in
two and the information for last flop doesn’t get dumped in Scan def. When scan def is read
in EDA tool just because lack of information for the last flop, reordering of scan chains
doesn’t happen correctly and Lock-up latch sits anywhere in the design.

In LBIST we keep many but small scan chains normally with scan chain length in the range
of ~50.This is to reduce the runtime of LBIST on-field run. As these many small chains are
spread apart, it may happen that these chains get stitched with flops from different clock
domains resulting in a large number of lock-up latches getting inserted. These chains are
connected to the LBIST controller whose placement is influenced by the connections it
makes to these chains. Due to lock-up latch insertion, reordering of scan chains doesn’t
happen and the start and stop elements of a chain are not allowed to sit together resulting
 in sub-optimal placement of LBIST controller which in turn aggravates the design
Congestion.

Fig3. Criss-Crossing due to Lock-up latch insertion in scan chain

Approaches to avoid large number of lock-up latch insertion:

 Use max chain limit for scan stitching in such a way that the need of stitching any extra flop
from other clock domain to ensure the max limit requirement should not get raised.

 For the reason stated above, designs using multibit flops should ensure not to use an odd
number of maximum chain length limit.

 Connect scan chains with physical information so that the flops sitting far apart to each
other should not get stitched.

After using above mentioned approaches there will be no inter and intra Criss-
crossing of scan chains
 Fig4.: No Criss-crossing due to absence of lock-up latches “break-points”
Conclusion:

1. Lock-up latches can be the savior in hold timing closure, but can play pivotal role in
congestion issues.

2. Congestion issue can be reduced by using physical aware scan stitching techniques and
redefining the max chain limit for scan chains.

Clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock
circuit or source or clock definition point) arrives at different components at different times.
due to

 wire-interconnect length
 temperature variations
 capacitive coupling
 material imperfections and
 differences in input capacitance on the clock inputs 

these factor became more critical for high frequency

there are two types of clock skew

 Negative skew
 positive skew

Positive skew occurs when the transmitting register receives the clock tick earlier than the receiving
register.
Negative skew is occurs when the receiving register gets the clock tick earlier than the sending reg.

Zero clock skew refers to the arrival of the clock tick simultaneously at transmitting and receiving reg

Skew can be caused two types of violation

 Setup violation 
 Hold violation

When the clock travels slower than the path form the one reg to another allowing data to penetrate
two registers in the same clock tick, or maybe destroying the integrity of the latched data. this is
called hold violation because the previous data is not held long enough at the destination flop to be
properly clocked though.

if the destination flop receives the clock tick earlier than the source flop- the data signal has that
much less time to reach the destination flop before the next clock tick, if it is fails to do so,a setup
violation occurs, so called new data was not set up and stable before the next clock tick arrived.
Useful Skew
clock skew can also benefit a circuit by decreasing the clock period locally at which the circuit will
operate correctly, it means skew add more margin to meet setup. that is called useful skew

for each source register and destination register connected by a path. so, following setup and hold
inequalities must be obeyed.

for setup,
               T(clock period)  > = T(reg) + Path dealy(max) + J(jitter) + S(setup time) - Skew
for Hold,
               Skew <= T(reg) + Path delay(min) - J(jitter) - H(hold time)

Positive skews are good for fixing setup violation, but can cause hold violation
Negative skew can help hold violation, but can cause setup violation

Figure :1

Figure 1 show a situation where clock skew can benefit a synchronous circuit
In the zero skew circuit, a long path goes form FF1 to FF2, and short path, from FF2 to FF3,

here, Path FF2 -> FF3 path is close to having a hold violation: if small amount of extra clock delay
occurs at FF3, this could destroy the data at D input of FF3 before clock arrives.
Figure 2
Figure 2 shows how the problem can be fixed
for clock skew.
A small amount of extra delay is added before FF2's clock input. with the care the extra delay relaxes
the setup constraint for the FF1->FF2
here, for FF1->FF2 operates less than what required for zero skew.
so, some intentional skew helps in proper functioning of circuit,

NOTE: in above example, circuit is closer to malfunctioning- a small amount of positive clock skew for
the FF2-> FF3 pair will cause hold violation, whereas the intentional skew(useful skew) circuit helps to
meet the setup and hold constraints

General Rules Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Procedure Rules Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Bus Mutual Exclusivity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Scan Chain Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Shadow Latch Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Data Rules Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Transparent Latch Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Clock Rules Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

RAM Rules Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Bus Keeper Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Extra Rules Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Scannability Rules Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Constrained/Forbidden/Block Value Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ATPG Violations:-
Error: No load_unload procedure in group procedure file. (P36-1)
// Error: Rules checking unsuccessful, cannot exit SETUP mode.

What is the purpose of scan testing?

Ans:-Scan testing is done in order to detect any manufacturing fault in the

combinatorial logic block. In order to do so, the ATPG tool try to excite each and
every node within the combinatorial logic block by applying input vectors at the flops of
the scan chain.

What is scan insertion steps?

To enable a scan test for a chip design, additional test logic must be inserted; this is
called “scan insertion”.
Scan insertion consists of two steps:
1. Replace plain memory cells like flipflops or latches by scan cells. 
2. Connect these together forming one or more chains.

Why do we need scan in DFT?

Scan is the first step for inserting DFT(design for testability) architecture in any chip.
Thus scan insertion improves the controllability and observability of the
sequentially flops.

What is clock mixing in DFT?

Majorly, in DFT, we avoid mixing different clocks in the same chain, but if there is a
constraint to I/O ports we have to stitch scan flops driven by two different clocks in one
chain