Active-HDL Student Edition

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Active-HDL Student Edition

Copyright 2022 ALDEC, Inc. Henderson, NV USA
All Rights Reserved.
ALDEC, Inc. homepage http://www.aldec.com
 Contents
1 Table of Contents
2 tutorialVHDL............................................................................................................................................................1
2.1 Contador_4b.vhd...............................................................................................................................................1
2.2 comp_and.vhd...................................................................................................................................................2
2.3 cont_bcd.bde.....................................................................................................................................................3
2.3.1 cont_bcd.vhd...............................................................................................................................................3
2.4 hex2led.vhd........................................................................................................................................................6
2.4.1 Controller.vhd..............................................................................................................................................7
2.5 frec_top2.bde...................................................................................................................................................10
2.5.1 frec_top2.vhd............................................................................................................................................10
Active-HDL Student Edition
2 tutorialVHDL

2.1 Contador_4b.vhd

--
--
-- Title : e_cont4b
-- Design : tutorialVHDL
-- Author : carlos garcia
-- Company : instituto tecnologico cuidad guzman
--
--
--
-- File : c:\VHDL\tutorial\tutorialVHDL\src\Contador_4b.vhd
-- Generated : Wed Oct 12 20:51:50 2022
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
--
--
-- Description :
--
--

--{{ Section below this comment is automatically maintained

-- and may be overwritten
--{entity {e_cont4b} architecture {a_cont4b}}
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity e_cont4b is
port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
FULL : out STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end e_cont4b;
--}} End of automatically maintained section
architecture a_cont4b of e_cont4b is

signal QINT: STD_LOGIC_VECTOR(3 DOWNTO 0);

begin
-- enter your statements here --
process (CLK,RESET)
begin
if RESET= '1' then
Qint<=(others=>'0');
elsif CLK='1' and CLK' event then
if ENABLE ='1' then
if Qint=9 then
Qint<= (others=> '0');
else

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Qint<= Qint + 1;
end if;
end if;
end if;
end process;
Q<= Qint;
FULL <= '1' when (Qint=9) else '0';
end a_cont4b;

2.2 comp_and.vhd

--
--
-- Title : e_compand
-- Design : tutorialVHDL
-- Author : carlos garcia
-- Company : instituto tecnologico cuidad guzman
--
--
--
-- File : c:\VHDL\tutorial\tutorialVHDL\src\comp_and.vhd
-- Generated : Wed Oct 12 21:15:07 2022
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
--
--
-- Description :
--
--

--{{ Section below this comment is automatically maintained

-- and may be overwritten
--{entity {e_compand} architecture {a_compand}}
library IEEE;
use IEEE.std_logic_1164.all;
entity e_compand is
port(
a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
Y : out STD_LOGIC
);
end e_compand;
--}} End of automatically maintained section

architecture a_compand of e_compand is

begin

-- enter your statements here --

Y <= a0 and a1;

end a_compand;

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2.3 cont_bcd.bde

2.3.1 cont_bcd.vhd

--
--
-- Title :
-- Design : tutorialVHDL
-- Author :
-- Company :
--
--
--
-- File : c:\VHDL\tutorial\tutorialVHDL\compile\cont_bcd.vhd
-- Generated : Thu Oct 13 11:48:38 2022
-- From : c:\VHDL\tutorial\tutorialVHDL\..\src\cont_bcd.bde
-- By : Bde2Vhdl ver. 2.6
--
--

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--
-- Description :
--
--
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
entity e_bcd is
port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
GATE : in STD_LOGIC;
bcd_a : out STD_LOGIC_VECTOR(3 downto 0);
bcd_b : out STD_LOGIC_VECTOR(3 downto 0);
bcd_c : out STD_LOGIC_VECTOR(3 downto 0);
bcd_d : out STD_LOGIC_VECTOR(3 downto 0)
);
end e_bcd;
architecture a_bcd of e_bcd is

---- Component declarations -----

component e_compand
port(
a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
Y : out STD_LOGIC
);
end component;
component e_cont4b
port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
FULL : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
---- Constants -----
constant DANGLING_INPUT_CONSTANT : STD_LOGIC := 'Z';
---- Signal declarations used on the diagram ----

signal Global2 : STD_LOGIC;

signal Global3 : STD_LOGIC;
signal NET705 : STD_LOGIC;
signal NET731 : STD_LOGIC;
signal NET734 : STD_LOGIC;
signal NET758 : STD_LOGIC;
signal NET761 : STD_LOGIC;
signal NET773 : STD_LOGIC;
signal BUS642 : STD_LOGIC_VECTOR(7 downto 0);
signal BUS684 : STD_LOGIC_VECTOR(7 downto 0);

---- Declaration for Dangling input ----

signal Dangling_Input_Signal : STD_LOGIC;

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begin

---- Component instantiations ----

U1 : e_cont4b
port map(
CLK => Dangling_Input_Signal,
RESET => Dangling_Input_Signal,
ENABLE => GATE,
FULL => NET705,
Q(3) => BUS642(7),
Q(2) => BUS642(6),
Q(1) => BUS642(5),
Q(0) => BUS642(4)
);
U2 : e_cont4b
port map(
CLK => Dangling_Input_Signal,
RESET => Dangling_Input_Signal,
ENABLE => NET731,
FULL => NET734,
Q => bcd_c
);

U3 : e_cont4b
port map(
CLK => Dangling_Input_Signal,
RESET => Dangling_Input_Signal,
ENABLE => NET758,
FULL => NET761,
Q => bcd_b
);

U4 : e_cont4b
port map(
CLK => Dangling_Input_Signal,
RESET => Dangling_Input_Signal,
ENABLE => NET773,
Q(3) => BUS684(7),
Q(2) => BUS684(6),
Q(1) => BUS684(5),
Q(0) => BUS684(4)
);
U5 : e_compand
port map(
a0 =>
NET705, a1
=> GATE, Y
=> NET731
);
U6 : e_compand
port map(
a0 => NET734,
a1 => NET731,
Y => NET758
);
U7 : e_compand
port map(
a0 => NET761,
a1 => NET758,

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Y => NET773
);

---- Terminal assignment ----

-- Output\buffer terminals
bcd_a(0) <= BUS684(4);
bcd_a(1) <= BUS684(5);
bcd_a(2) <= BUS684(6);
bcd_a(3) <= BUS684(7);
bcd_d(0) <= BUS642(4);
bcd_d(1) <= BUS642(5);
bcd_d(2) <= BUS642(6);
bcd_d(3) <= BUS642(7);

---- Dangling input signal assignment ----

Dangling_Input_Signal <= DANGLING_INPUT_CONSTANT;

end a_bcd;

2.4 hex2led.vhd

--HEX-to-seven-segment decoder
-- HEX: in STD_LOGIC_VECTOR (3 downto 0);
-- LED: out STD_LOGIC_VECTOR (6 downto 0);
--
-- segment encoding
-- 0
-- ---
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- ---
-- 3

--
-- Title : e_hex2led
-- Design : tutorialVHDL
-- Author : carlos garcia
-- Company : instituto tecnologico cuidad guzman
--
--
--
-- File : c:\VHDL\tutorial\tutorialVHDL\src\hex2led.vhd
-- Generated : Wed Oct 12 22:11:06 2022
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
--
--
-- Description :
--

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--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {e_hex2led} architecture {a_hex2led}}
library IEEE;
use IEEE.std_logic_1164.all;
entity e_hex2led is
port(
hex : in STD_LOGIC_VECTOR(3 downto 0);
led : out STD_LOGIC_VECTOR(6 downto 0)
);
end e_hex2led;
--}} End of automatically maintained section

architecture a_hex2led of e_hex2led is

begin

with HEX select

LED<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0------------------------------------------

end a_hex2led;

2.4.1 Controller.vhd

--
--
-- Title : No Title
-- Design :
-- Author : carlos garcia
-- Company : instituto tecnologico cuidad guzman
--
--
--
-- File : c:/VHDL/tutorial/tutorialVHDL/compile/Controller.vhd
-- Generated : Thu Oct 13 08:33:17 2022
-- From : c:/VHDL/tutorial/tutorialVHDL/src/Controller.asf
-- By : Active-HDL Student Edition FSM Code Generator ver. 6.0
--
--
-

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-- Description :
--
--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_signed.all;

entity Controller is
port (
f_pattern: in STD_LOGIC;
reset: in STD_LOGIC;
start: in STD_LOGIC;
gate: out STD_LOGIC;
end_reset: out STD_LOGIC
);
end Controller;
architecture Controller_arch of Controller is

-- BINARY ENCODED state machine: Sreg0

attribute ENUM_ENCODING: string;
type Sreg0_type is (
idle, open_gate, end_cycle
);
attribute ENUM_ENCODING of Sreg0_type: type is
"00 " & -- idle
"01 " & -- open_gate
"10" ; -- end_cycle
signal Sreg0, NextState_Sreg0: Sreg0_type;

begin

-- FSM coverage pragmas

-- Aldec enum Machine_Sreg0 CURRENT=Sreg0
-- Aldec enum Machine_Sreg0 NEXT=NextState_Sreg0
-- Aldec enum Machine_Sreg0 INITIAL_STATE=idle
-- Aldec enum Machine_Sreg0 STATES=end_cycle,open_gate
-- Aldec enum Machine_Sreg0 TRANS=end_cycle->end_cycle,end_cycle->idle,idle->
idle,idle->open_gate
-- Aldec enum Machine_Sreg0 TRANS=open_gate->end_cycle
-- User statements

-- Diagram ACTION

-- Machine: Sreg0

-- Next State Logic (combinatorial)

Sreg0_NextState: process (start, Sreg0)
begin
NextState_Sreg0 <= Sreg0;
-- Set default values for outputs and signals
gate <= '0';
end_reset <= '1';
case Sreg0 is

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when idle =>
gate <='0';
end_reset<='1';
case start is
when '1' =>
NextState_Sreg0 <= open_gate;
when '0' =>
NextState_Sreg0 <= idle;
when others =>
null;
end case;
when open_gate =>
gate <='1';
end_reset<='0';
NextState_Sreg0 <= end_cycle;
when end_cycle =>
gate<='0';
end_reset<='0';
case start is
when '0' =>
NextState_Sreg0 <= idle;
when '1' =>
NextState_Sreg0 <= end_cycle;
when others =>
null;
end case;
--vhdl_cover_off
when others =>
null;
--vhdl_cover_on
end case;
end process;

-- Current State Logic (sequential)

Sreg0_CurrentState: process (f_pattern)
begin
if f_pattern'event and f_pattern = '1' then
if reset='1' then
Sreg0 <= idle;
else
Sreg0 <= NextState_Sreg0;
end if;
end if;
end process;

end Controller_arch;

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2.5 frec_top2.bde

2.5.1 frec_top2.vhd

--
--
-- Title :
-- Design : tutorialVHDL
-- Author :
-- Company :
--
--
--
-- File : c:\VHDL\tutorial\tutorialVHDL\compile\frec_top2.vhd
-- Generated : Thu Oct 13 12:41:15 2022
-- From : c:\VHDL\tutorial\tutorialVHDL\src\frec_top2.bde
-- By : Bde2Vhdl ver. 2.6
--
--
--
-- Description :

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--
--
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
-- Included from components --
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_signed.all;

entity e_frec is
port(
f_input : in STD_LOGIC;
f_pattern : in STD_LOGIC;
Reset : in STD_LOGIC;
Start : in STD_LOGIC;
led_d : out STD_LOGIC_VECTOR(6 downto 0);
led_c : out STD_LOGIC_VECTOR(6 downto 0);
led_b : out STD_LOGIC_VECTOR(6 downto 0);
led_a : out STD_LOGIC_VECTOR(6 downto 0)
);
end e_frec;
architecture a_frec of e_frec is

---- Component declarations -----

component controller
port(
f_pattern : in std_logic;
reset : in std_logic;
start : in std_logic;
gate : out std_logic;
end_reset : out std_logic
);
end component;
component e_bcd
port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
GATE : in STD_LOGIC;
bcd_a : out STD_LOGIC_VECTOR(3 downto 0);
bcd_b : out STD_LOGIC_VECTOR(3 downto 0);
bcd_c : out STD_LOGIC_VECTOR(3 downto 0);
bcd_d : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
component e_hex2led
port(
hex : in STD_LOGIC_VECTOR(3 downto 0);
led : out STD_LOGIC_VECTOR(6 downto 0)
);
end component;
---- Signal declarations used on the diagram ----

signal NET1041 : std_logic;

signal NET1049 : std_logic;
signal BUS1004 : STD_LOGIC_VECTOR(3 downto 0);
signal BUS1017 : STD_LOGIC_VECTOR(3 downto 0);
signal BUS1025 : STD_LOGIC_VECTOR(3 downto 0);

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signal BUS1033 : STD_LOGIC_VECTOR(3 downto 0);

begin

---- Component instantiations ----

U1 : controller
port map(
f_pattern => f_pattern,
reset => Reset,
start => Start,
gate => NET1041,
end_reset => NET1049
);

U4 : e_bcd
port map(
CLK => f_input,
RESET => NET1041,
GATE => NET1049,
bcd_a => BUS1033,
bcd_b => BUS1025,
bcd_c => BUS1017,
bcd_d => BUS1004
);
U5 : e_hex2led
port map(
hex => BUS1033,
led => led_d
);

U6 : e_hex2led
port map(
hex => BUS1025,
led => led_c
);

U7 : e_hex2led
port map(
hex => BUS1017,
led => led_b
);

U8 : e_hex2led
port map(
hex => BUS1004,
led => led_a
);

end a_frec;

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