Department of Computer Science & Engineering

CSE-311 Computer Organization

Instructor: Dr. Bassem Mokhtar
Lectures prepared by Prof. Mostafa Soliman

Fall 2022
 GENERAL INFORMATION

CSE 311 –Computer Organization

Level Under-Graduate
Pre-requisites ECE 221 Digital Logic Design

Course web-page Blackboard/Google Classroom

Schedule Tuesday 9:00 – 10:30 am, Location: B9 Theater

Office Hours: TBD, Office Location: B7 F2.16
Attendance Policy A minimum of 75% attendance is expected.

Instructor contact [email protected]

Grading Scheme Final Exam - 40 %

Mid Term Exam - 30 %
Quizzes - 15 % Assignments – 15%
 GENERAL INFORMATION

CSE 311 –Computer Organization

Course Overview This course covers the basics of computer organization. It emphasizes on
understanding the interaction between computer hardware and software at
various levels. The students will learn the following concepts after
overviewing digital logic and digital systems:
• machine level representation of data;
• assembly level machine organization;
• memory system organization and architecture;
• interfacing and communication;
• functional organization;
• multiprocessing and alternative architectures; and
• performance enhancements.
 GENERAL INFORMATION

CSE 311 –Computer Organization

Expected Outcome 1. Interpret the functional architecture of computing systems.
• Classify and compute the performance of machines.
• Understand how to implement main and cache memories.

2. Identify, compare and assess issues related to instruction set

architecture (ISA), memory, and control.
• Estimate the performance of various classes of machines,
memories, pipelined architectures.
• Compare CPU implementations.

3. Design and analyze solutions in the area of computer organization.

• Design an instruction encoding scheme for an ISA.
• Build memory hierarchy (multi-level) for better performance.
• Write machine/assembly codes for RISC machines.
 GENERAL INFORMATION

CSE 311 –Computer Organization

Recommended 1- M. Mano, “Computer System Architecture,” Pearson Publisher, 3rd
Edition, 1992.
References 2- D. Patterson and J. Hennessy, “Computer Organization and Design: the
Hardware/Software Interface,” Morgan Kaufmann, 5th Edition, 2014.
Disclaimer Slides throughout the course are based on the textbooks above and
some slides will be modified from the slides made available by the
above mentioned textbook publishers & authors
GENERAL INFORMATION
 CSE 311
Computer Organization

Lecture 1
Introduction

Mostafa I. Soliman
Professor of Computer Engineering
(Computer Architecture and Parallel Processing)
CSE Department
[email protected]
[email protected]
7
 CSE 311: Computer Organization
• Level 5
• Course Code CSE 311 (Computer Organization)
• Credits 3
• Lecture 2
• Tutorial 0
• Lab 2
• Contact Hrs. 4
• SWL 135 (Student Workload Load)
• Pre/ Corequisites ECE 221 (Digital Logic Design)
• Grading System
– Class 0.3 ꟷ Mid Term 0.3
– Lab ꟷ Oral
– Final 0.4
• Exam Duration 3
8
CSE 311: Computer Organization
• Overview of Digital Logic and Digital Systems

• Machine Level Representation of Data

• Assembly Level Machine Organization

• Memory System Organization and Architecture

• Interfacing and Communication

• Functional Organization

• Multiprocessing and Alternative Architectures

• Performance Enhancements

9
 Computer Organization
• Computer organization is concerned with
the way the hardware components operate and
the way they are connected together to form
the computer system

10
 Overview of Digital Logic
• Logic Gates

• Boolean Algebra

• Map Specification

• Combinational Circuits

• Flip-Flops

• Sequential Circuits

• Memory Components

• Integrated Circuits

11
Combinational Gates
Name Symbol Function Truth Table
A B X
A X=A•B 0 0 0
AND B
X or
X = AB
0
1
1
0
0
0
1 1 1
A B X
A 0 0 0
OR X X=A+B 0 1 1
B 1 0 1
1 1 1
A X
I A X X = A’ 0
1
1
0
A X
Buffer A X X=A 0 0
1 1
A B X
A 0 0 1
NAND X X = (AB)’ 0
1
1
0
1
1
B 1 1 0
A B X
A 0 0 1
NOR X X = (A + B)’ 0
1
1
0
0
0
B 1 1 0
A B X
A X=AB
XOR X or 0 0 0
Exclusive OR 0 1 1
B X = A’B + AB’ 1 0 1
1 1 0
A B X
XNOR A X = (A  B)’ 0 0 1
Exclusive NOR X or 0 1 0
or Equivalence B X = A’B’+ AB 1 0 0
1 1 1
12
 Logic Circuit Design
x y z F
0 0 0 0
Truth 0 0 1 1
Table 0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Boolean F = x + y’z
Function

x
F
Logic y
Diagram
z
13
Basic Identities of Boolean Algebra
[1] x + 0 = x [2] x • 0 = 0
[3] x + 1 = 1 [4] x • 1 = x
[5] x + x = x [6] x • x = x
[7] x + x’ = 1 [8] x • X’ = 0
[9] x + y = y + x [10] xy = yx
[11] x + (y + z) = (x + y) + z [12] x(yz) = (xy)z
[13] x(y + z) = xy +xz [14] x + yz = (x + y)(x + z)
[15] (x + y)’ = x’y’ [16] (xy)’ = x’ + y’
[17] (x’)’ = x
[15] and [16] : De Morgan’s Theorem
Usefulness of this Table
- Simplification of the Boolean function
- Derivation of equivalent Boolean functions
to obtain logic diagrams utilizing different logic gates
-- Ordinarily ANDs, ORs, and Inverters
-- But a certain different form of Boolean function may be convenient
to obtain circuits with NANDs or NORs
→ Applications of De Morgans Theorem

x’y’ = (x + y)’ x’+ y’= (xy)’

I, AND → NOR I, OR → NAND

14
 Equivalent Circuits
Many different logic diagrams are possible for a given Function
F = ABC + ABC’ + A’C .......…… (1)
= AB(C + C’) + A’C [13] ..…. (2)
= AB • 1 + A’C [7]
= AB + A’C [4] ...…. (3)
A
B
(1) C
F

(2) A
B

C F

(3) A
B
F
C

15
 Simplification
Truth Boolean
Table Function
Unique Many different expressions exist
Simplification from Boolean function

- Finding an equivalent expression that is least expensive to implement

- For a simple function, it is possible to obtain
a simple expression for low cost implementation
- But, with complex functions, it is a very difficult task

Karnaugh Map (K-map) is a simple procedure for

simplifying Boolean expressions.
Truth
Table
Simplified
Karnaugh Boolean
Map Function
Boolean
function

16
 Combinational Logic Circuits
y y
Half Adder x y c s x
0 0 0 0 0 0 0 1 c
y
0 1 0 1 x 0 1 x 1 0
1 0 0 1 c = xy s = xy’ + x’y s
1 1 1 0 =x  y
Full Adder
y y
x y cn-1 cn s
0 0 0 0 0 0 0 0 1
0 0 1 0 1 0 1 cn-1 1 0 cn-1
0 1 0 0 1 x 1 1 x 0 1
0 1 1 1 0 0 1 1 0
1 0 0 0 1 cn s
1 0 1 1 0 cn = xy + xcn-1+ ycn-1
1 1 0 1 0 = xy + (x  y)cn-1
1 1 1 1 1 s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
Other Combinational Circuits = x  y  cn-1 = (x  y)  cn-1
Multiplexer x
Encoder y S
Decoder
Parity Checker cn-1
Parity Generator cn
etc.
17
 Multiplexer
4-to-1 Multiplexer
Select Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

I0

I1
Y
I2

I3

S0
S1

18
 Encoder / Decoder
Octal-to-Binary Encoder
D1 A0
D2
D3 A1
D4
D5 A2
D6
D7

2-to-4 Decoder
D0

E A1 A0 D0 D1 D2 D3 A0 D1
0 0 0 0 1 1 1
0 0 1 1 0 1 1 D2
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 d d 1 1 1 1 A1 D3
E

19
 3x8 Decoder
A2 D0
D1
A1
D2
A0
3x8 D3

Decoder D4
D5

E D6
D7

20
 4x1 Multiplexer
I0

I1 4x1
Multiplexer Y
I2

I3

S0 S1

21
 Sequential Circuits
Characteristics
- 2 stable states
- Memory capability
- Operation is specified by a Characteristic Table
1 0 0 1

0 1 1 0
0-state 1-state
In order to be used in the computer circuits, state of the flip flop should
have input terminals and output terminals so that it can be set to a certain
state, and its state can be read externally.

R S R Q(t+1)
Q 0 0 Q(t)
0 1 0
1 0 1
S Q’ 1 1 indeterminate
(forbidden)

22
RS-Latch with Preset and Clear Inputs
P(preset)
R Q
c
(En)
S Q’

clr(clear)

S P Q S P Q
En En
R clr Q’ R clr Q’

S P Q S P Q
En En
R clr Q’ R clr Q’
23
 D-Latch
D-Latch
Forbidden input values are forced not to occur
by using an inverter between the inputs

D Q
Q

E
(enable) E Q’

Q’ D Q
D(data)

D Q(t+1) E Q’
0 0
1 1

24
 Edge-Triggered Flip Flops
Characteristics
- State transition occurs at the rising edge or
falling edge of the clock pulse

Latches

respond to the input only during these periods

Edge-triggered Flip Flops (positive)

respond to the input only at this time

25
 Positive Edge-Triggered
D-Flip Flop
D S1 Q1 S2 Q2 Q D Q
SR1 SR2
C1 C2 D-FF
R1 Q1' R2 Q2' Q' C Q'
C

SR1 inactive
SR2 active
SR2 inactive SR2 inactive
SR1 active SR1 active
JK-Flip Flop

J S1 Q1 S2 Q2 Q J Q
SR1 SR2
C1 C2 C
K R1 Q1' Q' K Q'
R2 Q2'
C

T-Flip Flop: JK-Flip Flop whose J and K inputs are tied together to make
T input. Toggles whenever there is a pulse on T input.
26
 Clock Period
Clock period determines how fast the digital circuit operates.
How can we determine the clock period ?
Usually, digital circuits are sequential circuits which has some flip flops

FF FF ... FF
C
Combinational
. .
Logic .
. Circuit
. .

Combinational
FF Logic FF
Hold Time: the Circuit Setup Time: the
FF Setup Time amount of time
amount of time the FF Delay Combinational logic Delay FF Hold Time the data at the
data at the
synchronous input td synchronous
(D) must be stable ts,th input (D) must
after the active edge clock period T = td + ts + th be stable before
of clock. the active edge
of clock.

27
 Design Example
Design Procedure:
Specification  State Diagram  State Table 
Excitation Table  Karnaugh Map  Circuit Diagram
Example: 2-bit Counter -> 2 FF's
x=0 current next
state input state FF inputs
00 A B x A B Ja Ka Jb Kb
x=1 x=1 0 0 0 0 0 0 d 0 d
0 0 1 0 1 0 d 1 d
x=0 01 11 x=0 0 1 0 0 1 0 d d 0
0 1 1 1 0 1 d d 1
x=1 1 0 0 1 0 d 0 0 d
x=1 1 0 1 1 1 d 0 1 d
10 1 1 0 1 1 d 0 d 0
x=0 1 1 1 0 0 d 1 d 1

B B B B
d d d d
1 x d dx 1 d x d 1 x
d d 1 x
A 1 d B
d 1 J Q A J Q
A A A C C
d d d d
K Q' K Q'
Ja Ka Jb Kb
Clock
Ja = Bx Ka = Bx Jb = x Kb = x
28
 Sequential Circuits - Registers
A0 A1 A2 A3
Q Q Q Q
DC DC DC D C
Clock
I0 I1 I2 I3
Shift Registers
Serial Serial
D Q D Q D Q D Q
Input Output
C C C C
Clock

Bidirectional Shift Register with Parallel Load

A0 A1 A2 A3

Q Q Q Q
D C D C D C D C

4x1 4x1 4x1 4x1

MUX MUX MUX MUX

Clock S0S1 SeriaI I0 I1 I2 Serial I3

Input Input
29
Sequential Circuits - Counters

A0 A1 A2 A3

Q Q Q Q
J K J K J K J K
Clock

Counter
Enable

Output
Carry

30
 Memory Components
0
Logical Organization

words
(byte, or n bytes)

N-1
Random Access Memory

- Each word has a unique address

- Access to a word requires the same time
independent of the location of the word
- Organization
n data input lines

k address lines
2k Words
Read (n bits/word)

Write

n data output lines

31
 Read Only Memory (ROM)
Characteristics
- Perform read operation only, write operation is not possible
- Information stored in a ROM is made permanent
during production, and cannot be changed
- Organization k address input lines

m x n ROM
(m=2k)

n data output lines

Information on the data output line depends only
on the information on the address input lines.
--> Combinational Logic Circuit address Output
X0=A’B’ + B’C ABC X0 X1 X2 X3 X4
X1=A’B’C + A’BC’ 000 1 0 0 0 0
X2=BC + AB’C’
X3=A’BC’ + AB’
001 1 1 0 0 0
X4=AB 010 0 1 0 1 0
011 0 0 1 0 0
X0=A’B’C’ + A’B’C + AB’C 100 0 0 1 1 0
X1=A’B’C + A’BC’ 101 1 0 0 1 0
X2=A’BC + AB’C’ + ABC 110 0 0 0 0 1
X3=A’BC’ + AB’C’ + AB’C 111 0 0 1 0 1
Canonical minterms X4=ABC’ + ABC
32
 Memory
• There are two types of memories that are used in
digital systems:
– Random-access memory (RAM): perform both the write and
read operations
– Read-only memory (ROM): perform only the read operation.

• The read-only memory is a programmable logic

device.
– Other such units are
» the programmable logic array (PLA),
» the programmable array logic (PAL), and
» the field-programmable gate array (FPGA).
33
 RAM: Random-Access Memory
• A memory unit stores binary information in groups of
bits called words.
1 byte = 8 bits
1 word = 2 bytes
• The communication between a memory and its
environment is achieved through data input and
output lines, address selection lines, and control
lines that specify the direction of transfer.

34
 Content of a Memory
• Each word in memory is
assigned an identification
number, called an
address, starting from 0
up to 2k-1, where k is the
number of address lines.
• The number of words in a
memory with one of the
letters K = 210, M = 220, or
G = 230.
64K = 216 2M = 221
4G = 232
35
 Memory Cell
• Memory cell is a binary cell that stores one bit of
information.
– input data to S-R latch: Read/Write = 0, select = 1,
– output data from S-R latch: Read/Write = 1, select = 1,

36
 4x4 RAM
• There is a need for decoding circuits to select the
memory word specified by the input address.

• During the read operation, the four bits of the selected

word go through
OR gates to the output
terminals.

• During the write operation,

the data available in the
input lines are transferred
into the four binary cells
of the selected word.

37
 ROM
• A block diagram of a ROM consists of k address
inputs and n data outputs.

• The number of words in a ROM is determined from

the fact that k address input lines are needed to
specify 2k words.
• Each output of the
decoder represents a
memory address.
• Each OR gate must
be considered as
having 32 inputs.
• A 2k X n ROM will
have an internal
k X 2k decoder and n OR gates.
38
 Truth Table of ROM
• A programmable connection between to lines is
logically equivalent to a switch that can be altered to
either be close or open.
• Intersection between two lines is sometimes called a
cross-point.
• X : means connection
• Address 3 = 10110010 is permanent storage using
fuse link

39
 Types of ROMs
• The required paths in a ROM may be programmed
in four different ways.

1. Mask programming: fabrication process

2. Read-only memory or PROM: blown fuse /fuse

intact

3. Erasable PROM or EPROM: placed under a special

ultraviolet light for a given period of time will
erase the pattern in ROM.

4. Electrically-erasable PROM(EEPROM): erased with

an electrical signal instead of ultraviolet light.

40
 References

• M. Mano, “Digital Design: With an Introduction to the

Verilog HDL, VHDL, and SystemVerilog,” Pearson
Publisher, 6th Edition, 2017.

41
42
 Sheet 1
• Using block diagrams, construct a 5x32 decoder with four 3x8
decoders with enable and one 2x4 decoder.

• Using block diagrams, construct a 16x1 multiplexer with two 8x1

multiplexers and one 2x1 multiplexer.

• Draw the block diagram of a dual 4x1 multiplexers and explain its
operation by means of a function table.

• The content of a 4-bit register is initially 1101 . The register is shifted

six times to the right with the serial input being 101101. What is the
content of the register after each shift?

• Draw a 4-bit bidirectional shift register with parallel load. Draw the
block diagram of its IC showing all inputs and outputs. Draw a block
diagram using two ICs to produce an 8-bit bidirectional shift register
with parallel load.
43
 Sheet 1
• How many flip-flops will be complemented in a 10-bit binary counter
to reach the next count after (a) 1001100111; (b) 0011111111?

• Show the connections between four 4-bit binary counters with

parallel load to produce a 16-bit binary counter with parallel load.
Use a block diagram for each 4-bit counter.

• The following memory units are specified by the number of words

times the number of bits per word. How many address lines and
input-output data lines are needed in each case? (a) 2Kx16; (b)
64Kx8; (c) 16Mx32; (d) 4Gx64. Specify the number of bytes that can
be stored in each memory.

• How many 128x8 memory chips are needed to provide a memory

capacity of 4096x16?

• Given a 32x8 ROM chip with an enable input, show the external
connections necessary to construct a 128x8 ROM with four chips
and a decoder. 44