IC 555 Timer
IC 555 Timer
Next are the two comparators. A comparator is a circuit element that compares two
Analog input voltages at its positive (non-inverting) and negative (inverting) input
terminal. If the input voltage at the positive terminal is higher than the input voltage at
the negative terminal the comparator will output 1. Vice versa, if the voltage at the
negative input terminal is higher than the voltage at the positive terminal, the
comparator will output 0.
The Q-bar output of the flip-
flip goes to the output stage or
the output drivers which can
either source or sink a current
of 200mA to the load. The
output of the flip-flip is also
connected to a transistor that
connects the “Discharge” pin
to ground.
Multivibrator
• It is the electronic circuit which is used to
implement two state devices like oscillator,
timer and flip-flop
555 Timer – Monostable Mode
Next, let’s see how the 555 Timer works in a monostable mode.
Here’s an example circuit.
The trigger input is held High by connecting it to VCC through a
resistor. That means that the trigger comparator will output 0 to the S
input of the flip-flop. On the other hand, the Threshold pin is Low and
that makes the Threshold comparator out 0 as well. The Threshold pin
is actually Low because the Q-bar output of the flip-flop is High,
which keeps the discharge transistor active, so the voltage coming
from the source is going to ground through that transistor.
In order to change the 555 Timer output state to High we need to press the pushbutton
on trigger pin. That will ground the trigger pin, or the input state will be 0, thus the
comparator will output 1 to the S input of the flip-flip. This will cause the Q-bar output
to go Low and the 555 Timer output High. At the same time, we can notice that the
discharge transistor is turned off, so now the capacitor C1 will start charging through
the resistor R1.
The 555 Timer will remain in this state until the voltage across the capacitor reaches 2/3
of the supplied voltage. In that case, the Threshold input voltage will be higher and the
comparator will output 1 to the R input of the flip-flip. This will bring the circuit into
the initial state. The Q-bar output will become High, which will activate the discharge
transistor as well as make the IC output Low again.
So we can notice that the amount of time the output of the 555 Timer is High, depends
on how much time the capacitor needs to charge to 2/3 of the supplied voltage, and that
depends on the values of both the capacitor C1 and the resistor R1. We can actually
calculate this time with the following formula, T=1.1*C1*R1.
Summary of Monostable operation
Initial stage
Output Low Vcc becomes 2/3 Vcc
Makes R=1, Q=Low makes
Q=low, Qbar=High Qbar= High, Qd OFF
Qd ON, C discharge S=1, R=0, Q=High,
Output High Qbar=low
C charge to Vcc Output Low,
Through trigger become Zero Qd ON, C discharge to 0
R=0, S=0 so no change in output through Qd
Vcc
0
Sine wave of sufficient amplitude (> Vcc/6 = 2/3 Vcc – Vcc/2)
PLL
• A phase-locked loop (PLL) is an electronic circuit
with a voltage or voltage-driven oscillator that
constantly adjusts to match the frequency of an input
signal. PLLs are used to generate, stabilize, modulate,
demodulate, filter or recover a signal from a "noisy"
communications channel where data has been
interrupted.
• Phase-locked loops are widely employed in radio,
telecommunications, computers and other
electronic applications.
• The reason why we use PLL is because the input
frequency is fixed which limits the application to that
certain frequency only. Thus, with the use of PLL, we
can derive different frequencies based from the input
frequency.
• A phase locked loop is basically a closed loop system
designed to lock the output frequency and phase to the
frequency and phase of an input signal. It is commonly
abbreviated as Basics of PLL.
• PLLs are available as inexpensive monolithic ICs.
• They are used in applications such as frequency
synthesis, frequency modulation/demodulation, AM
detection, tracking filters, FSK demodulator, tone
detector etc.
• The phase detector compares the input frequency fs
with the feedback frequency fo and generates an
output signal which is a function of the difference
between the phases of the two input signals.
• The output signal of the phase detector is a dc voltage.
The output of phase detector is applied to low-pass
filter to remove high frequency noise from the DC
voltage.
• The output of low pass filter without high frequency
noise is often referred to as error voltage or control
voltage for VCO. When control voltage is zero, VCO is
in free running mode and its output frequency is called
as centre frequency fo.
• The non-zero control voltage results in a shift in the
VCO frequency from its free-running frequency, fo to a
frequency f, given by
f = fo + Kv Vc
where Kv is the voltage to frequency transfer coefficient of the
VCO.
The error or control voltage applied as an – input to the VCO, forces
the VCO to change its output frequency in the direction that reduces
the difference between the input frequency and the output frequency of
VCO.
This action, commonly known as capturing, continues till the
output frequency of VCO is same as the input signal frequency.
Once the two frequencies are same, the circuit is said to be locked.
In locked condition, phase detector generates a constant DC level
which is required to shift the output frequency of VCO from
centre frequency to the input frequency.
Once locked, PLL tracks the frequency changes of the input signal.
Thus, a PLL goes through three states. : free running, capture and
phase lock.
Monolithic PLL
• PLL but its availability in the form of a low-cost,
self- contained monolithic circuit package.
• The PLL IC 565 is usable over the frequency
range 0.1 Hz to 500 kHz. It has highly stable
centre frequency and is able to achieve a very
linear FM detection. The output of VCO is capable
of producing TTL compatible square wave. The
dual supply is in the range of ±6V to ±12V. The IC
can also be operated from single supply in the
range 12V to 24V.
• The following figure shows the pin-out and the
internal block schematic of PLL IC LM 565
• It is a 14 pin IC, operated from a dual power supply
+V (at pin no. 10) and –V (at pin no. 1).
Pin no 2 & 3 -> Signal input for phase detector.
Pin no 4 ->VCO output is available
Pin no 4 & 5 are shorted externally so that VCO
output is applied for phase detection. In some
applications PLL loop is broken and some circuit is
to be connected between pin no 4 and 5.
Pin no 6-> reference dc voltage is available.
Pin no 7 -> demodulated output. If input signal
between pin no 2 and 3 is FM signal then at pin no 7
we get FM demodulation output.
Pin no 8 and 9 -> external R1 and C1 for VCO
(determines free running frequency of VCO) Internal
resistance R2 and external capacitor C2 forms a LPF.
The value of internal resistance R2 is 3.6kΩ.
R1 = 2 to 20Kohm
Features of IC 565:
1) Extreme stability of center frequency typically 200ppm.
2) Wide range of operating voltage ±6V to ±12V.
3) Very high linearity of demodulated output typically 0.2%
4) Centre frequency of VCO is programmable by means of resistor,
capacitor or voltage.
5) TTL compatible square wave output.
6) Highly linear triangular wave output available at pin no.9
7) Loop can be broken between pin no.4 and 5 and external circuit can be
added.
Design Equations:
1. Centre Frequency (Free running freq./ output freq./oscillator
freq.)
fo=0.3/(R1 C1 )
2. Lock range
fL=±(8fo)/V
where V=|+V|+|-V|……..(addition of two power supplies)
3. Capture range
fc=±[fL/ (2π)(3.6)(103)(C2)]1/2
Phase Detector
• A phase detector or phase comparator is a
frequency mixer, analog multiplier or logic
circuit that generates a voltage signal which
represents the difference in phase between
two signal inputs. It is an essential element of
the phase-locked loop (PLL)
Frequency Multiplier
• A frequency multiplier can be designed using a PLL and
a 'divided by N' counter. The frequency divider is
inserted between the VCO output (PIN 4) and phase
detector/comparator input (PIN 5) of PLL circuit.
• Therefore one input of the phase comparator is the input
signal and the other is the output of 'divided by N'
counter. when the lock is established the input
frequency fin equals the output of the counter fn.
hence fin=fn= (fout )/N ,where fout-is the vco output
frequency, therefore fout =N*fin.
• Thus when the system is in lock, the vco is actually
running at the multiple of input frequency .The desired
amount of multiplication can be obtained by selecting a
proper divide by N network, where N is an integer.
Block Diagram