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GM/ID METHODOLOGY USING EVOLUTIONARY ALGORITHMS AND

ELECTRICAL SIMULATION FOR INTEGRATED CMOS OTA DESIGN
AUTOMATION

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Lucas Compassi Severo Alessandro Girardi

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 GM/ID METHODOLOGY USING EVOLUTIONARY ALGORITHMS AND
ELECTRICAL SIMULATION FOR INTEGRATED CMOS OTA DESIGN
AUTOMATION

Lucas Compassi Severo, Alessandro Girardi

Federal University of Pampa – UNIPAMPA

Alegrete – RS – Brazil

ABSTRACT numeric analysis. Some previous works have been done

in this theme describing the development of tools for
The goal of this paper is to analyze the gm/ID analog design automation (ADA). The goal is always the
methodology for automatic sizing of analog integrated automation of time-consuming tasks and complex
amplifiers. This methodology exploits the analytical searches in highly non-linear design spaces [2][3][4].
gm/ID methodology, in which the inversion level of the Different automatic design strategies have been proposed,
transistors are free variables and gate width and length are using different meta-heuristics and algorithms [5][6].
defined in terms of the technology independent gm/ID Basically all of them can be categorized as equation-
versus ID/(W/L) curve. Genetic Algorithms was used as based or simulation-based automatic designs. In the
optimization heuristic together with a Spice simulator for equation-based design strategy, analytical equations are
implementing a power-constrained design of a two-stage used for modeling device electrical characteristics, such
Miller operational transconductance amplifier for as drain current, inversion level or small-signal
different gain-bandwidth requirements. parameters. These models are often simplified or
manipulated in order to fit certain limitations imposed by
optimization heuristics. The simulation-based strategy is
1. INTRODUCTION based on the result of the electrical simulation of the
circuit to extract device parameters and design
The design automation of analog integrated circuits is characteristics. The simulation can be automated and
a demanding task in microelectronics industry, because of performed several times until reaching the design
the crescent necessity for low-power design and reduced objective.
time-to-market. Nowadays, most analog sizing designs The goal of this paper is to analyze a technique for
are done manually – with some aid of simulation tools automatic sizing of analog integrated amplifiers that
and equation-based models - and the quality of the exploits the analytical gm/ID methodology, in which the
resulting circuit is dependent on the expertise of the transconductance (gm) to drain current (ID) ratio of the
designer. For example, a system-on-chip (SOC) design transistors are free variables and gate width and length are
can have analog and digital parts, each one designed with defined in terms of the technology independent gm/ID
different methodology and tools. The analog design time versus ID/(W/L) curve. We used in this work an
must be compatible with the highly automated digital evolutionary heuristic for finding a close to optimum
design time, which employs advanced design automation solution. Circuit specifications are evaluated using an
tools [1]. Also, in general the entire design space external electrical simulator.
exploration is rarely executed, mainly in weak and As design example we show the sizing procedure of a
moderate inversion regions, which are the most power-constrained design of a two-stage Miller
appropriated for power-constrained applications. operational transconductance amplifier for different gain-
The design of analog integrated circuits can be bandwidth requirements.
divided in 3 steps: topology selection, transistor sizing
and layout generation. This paper will focus on the
second step, which is critical for achieving the desired 2. EVOLUTIONARY HEURISTICS
circuit performance under a set of constraints.
In this implementation, it was used an evolutionary
The design space for the automatic synthesis of an
heuristic named Genetic Algorithms (GA) for generating
analog CMOS integrated amplifiers is highly nonlinear.
the optimized sizes for the transistors of an analog circuit.
There are about ten free variables in a typical operational
Evolutionary heuristics are very useful in non-linear
transconductance amplifier design, related to gate
optimizations and large design space exploration. They
dimensions (W and L), bias currents or inversion levels.
start from a random initial solution and the optimization
As the relation between transistor sizes and circuit
process is performed with several solutions in parallel
specifications (design objectives) is nonlinear and
(population).
sometimes conflicting, the problem of finding an
In GA, there are two main parameters: the
optimum solution point is difficult to be exactly solvable
chromosome (a solution candidate for the problem) and
and it usually must be approximated by analytical or
the population (a set of chromosomes).
 New solutions are generated using the solutions
present in the population and the generation of new
solutions is implemented using the Crossover and
Mutation parameters.
An important choice in an optimization using GA is
the number of individuals in the population, because the
GA deals with several solutions simultaneously. A large
population increases the diversity of solutions but also
increases the optimization time. Then, the number of
population individuals must be chosen according to
criteria of assuring solution diversity but maintaining a
practical optimization time.
In this paper we used the implementation GAOT Figure 1: gm/ID x ID/(W/L) curve for NMOS and PMOS, 0.35µm
(Genetic Algorithms Optimization Toolbox) for Matlab
CMOS technology.
[7].

3. GM/ID METHODOLOGY

In the design procedure herein proposed, a methodology

called gm/ID is used for the circuit performance
evaluation. This methodology considers the relationship
between the ratio of the transconductance gm over DC
drain current ID and the normalized drain current In =
ID/(W/L) as a fundamental design parameter [8], such as
the curve shown in Figure 1. The gm/ID characteristic is
directly related to the performance of the transistors,
gives a clear indication of the device operation region and
provides a way for straightforward estimation of
transistors dimensions.
The main advantage of this method is that the gm/ID x
In curve is unique for a given technology, reducing the Figure 2: Design flow for the gm/ID design methodology
number of electrical parameters related to the fabrication
process. Additionally, its analytical form covers all
transistor operation regimes, from weak to moderate to 4. DESIGN EXAMPLE AND ANALYSIS OF
strong inversion. The gm/ID x In curve can be OPTIMIZATION RESULTS
automatically evaluated by electrical simulation or by
measurement data. As a design example using the design methodology
Figure 2 shows the proposed optimization design flow described in this paper, we used a two-stage CMOS
using Genetic Algorithms. The user enters the design Miller operational transconductance amplifier (OTA).
specifications, technology parameters and configures the The circuit schematic of this amplifier is shown in Figure
cost function according to the required design objectives 3. The Miller OTA is composed by an input differential
and specifications. pair and a current mirror with active load in the first
The optimization loop performs a random stage. The second stage is composed by an inverter
perturbation on the design variables, defined by the amplifier. Between the first and second stages is
genetic algorithms. These variables are defined by the connected a compensation capacitor for stability
user, and are always related to the transistor geometry, purposes.
large and small-signal parameters, such as W, L, ID, gm The main specifications of this circuit are low
and gm/ID. So using the gm/ID x IN curve and the frequency gain (Av), slew rate (SR), margin phase, input
specifications required for circuit the transistor sizes are common-mode range (IMCR), power consumption and
find. If the circuit is feasible, i.e., transistor sizes are gate area [9].
within an allowed range, the circuit specifications can be The optimization strategy relies on minimizing a cost
evaluated using the electrical simulations and the solution function, given as
is evaluated using the cost function. While the stop n m
conditions are not satisfied are generated new solutions.  
fc i
pi X j
cj X (1)
In GA are typical stop conditions: the maximum i 1 j 1
number of generations and the minimum variation in the where αi is the weighting coefficient for performance
cost function. 
parameter p i , which is a normalized function of the
vector of independent design parameters X (free
variables). This function allows the designer to set the [µW]
relative importance of competing performance Gate area [µm²] minimize 740.80
parameters, such as, for example, a weighted relation
 Tab. 2: Specifications and reached values for the design 2.
between power and area. The parameter c j X is a
Parameter Spec. gm/ID M.
constraint normalized function, which limits the design Av0 [dB] ≥ 70 70.10
space to feasible solutions of design specifications. GBW [MHz] ≥1 1.0
Phase margin [º] ≥ 60.0 60.8
The coefficient j indicates how closely the Slew rate [V/µs] 1 0.99
 ICMR+ [V] 0.7 1.35
specification must be pursued. If c j X is inside a ICMR- [V] -0.7 -1.60
given specification, i.e. the value is major that the Power consumption minimize 58.20
minimum and smaller than a percentage of minimum [µW]
Gate area [µm²] minimize 502.46
value, it is set to zero.
The cost function is computed at every iteration in the Tab. 3: Specifications and reached values for the design 3.
optimization loop. The correct design space exploration is
Parameter Spec. gm/ID M.
directly related to the cost function formulation [7][8].
Av0 [dB] ≥ 70 76.00
GBW [MHz] ≥ 10 10.00
Phase margin [º] ≥ 60.0 98.1
Slew rate [V/µs] 10 9.9
ICMR+ [V] 0.7 1.31
ICMR- [V] -0.7 -1.64
Power consumption minimize 296.01
[µW]
Gate area [µm²] minimize 6678,26

Figure 3: Schematics of a two-stage Miller operational

transconductance amplifier

For this design example we implemented three

different designs specifications with the goal to minimize
the gate area and the power consumption of the circuit.
For the Genetic Algorithm configurations we used a
population of 1000 individuals. The results of the three
designs are shown in Tables 1, 2 and 3.
Analyzing the optimization results we observe that all
specifications are reached in the three designs. We can
Fig. 4: Cost function value of the best solution during the
notice that the major part of the specifications values are
kept in a maximum o ten percent of the minimum values optimization of design 1.
of the specifications. In the first design the power
consumption is very low as expected, due to the unity
frequency and slew-rate requirements.
Figures 4, 5 and 6 show the cost function value of the
best solution during the optimization. In this figure we
can see that the values of this function start from a high
value and finish in a lower value, showing the
optimization path in the cost function value.

Tab. 1: Specifications and reached values for the design 1.

Parameter Spec. gm/ID M.
Av0 [dB] ≥ 70 73.50
GBW [MHz] ≥ 0.1 0.1
Phase margin [º] ≥ 60.0 63
Slew rate [V/µs] 0.1 0.1
ICMR+ [V] 0.7 1.3
Figure 5: Cost function value of the best solution during the
ICMR- [V] -0.7 -1.64
Power consumption minimize 3.52 optimization of design 2.
 Computer-Aided Design of Integrated Circuits and Systems,
vol. 28, 2009, pp. 623-637.
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Space Boundary Exploration and Model Generation for Analog
and RF IC Design," IEEE Transactions on Computer-Aided
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213-224.
[6] M.D. Hershenson, S.P. Boyd, and T.H. Lee, "Optimal
Design of a CMOS Op-Amp Via Geometric Programming,"
IEEE Transactions on Computer-Aided Design of Integrated
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G. Kay, “A Genetic Algorithm for Function Optimization: A
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and Its Application to the Synthesis of a Silicon-on-Insulator
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Circuit Design. Oxford University Press, 2002.
6. CONCLUSION

In this paper an automatic gm/ID methodology using

genetic algorithms and electrical simulation was
implemented.
As design example a two-stage Miller OTA is
automatic designed, for three different specifications. In
these designs all specifications are reached and the power
consumption and gate area were optimized. In this
optimization maximum value of specifications
reached are limited in ten percent of the minimum value
required.
As future work we intend to make a comparison between
other methodologies, insert the analysis of parameter
variation, and expand the methodology for other analog
circuits.

7. ACKNOWLEDGMENTS
The authors would like to thank FAPERGS research
agency for supporting this work.

8. REFERENCES

[1] G.G. Gielen and R.A. Rutenbar, "Computer-Aided

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