Chapter Four Lecture 1 Computer Architecture
Chapter Four Lecture 1 Computer Architecture
Lecture 1
Second class
Computer Architecture I
2021-2022
Al-Farabi University College Computer Architecture
Chapter Four
Register transfer and micro operations
4.1 Register Transfer Language
The internal hardware organization of a digital computer is best defined
by specifying:
1. The set of registers it contains and their function.
2. The sequence of microoperation performed on the binary information
stored in the register.
3. The control that initiates the sequence of microoperation.
It is more convenient to adopt a suitable symbolic language to describe the
sequence of transfers between registers and the various arithmetic and logic
microoperation associated with the transfers, rather than using explaining
every operation in words.
Register Transfer Language can be defined as, the symbolic notation used
to describe the microoperation transfers among registers. The term Register
Transfer implies the availability of hardware logic circuits that can perform
a stated microoperation and transfer the result of the operation to the same
or another register. The word language is borrowed from programmers, who
apply this term to programming languages.
Programming language is a procedure for writing symbols to specify a
given computational process. In the same manner, a natural language such
as Arabic is a system for writing symbols and combining them into words
and sentences for the purpose of communication between people. A
Register Transfer Language is a system for expressing the microoperation
sequences among the registers of a digital module in symbolic form. It can
be used to facilitate the design process of digital systems.
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To insure that no more than one control input is active at any given time, a
2*4 decoder is used as shown in the diagram. When the enable input of the
decoder is 0, all of its four outputs are 0, and the bus line is in a high-
impedance state because all four buffers are disabled. When the enable input
is active, one of the three-state buffers will be active, depending on the
binary value in the select inputs of the decoder. Circuit shown in figure 4.5
can replace one multiplexer in figure 4.3.
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For example, to construct a common bus for 4 registers of 4 bits each using
three-state buffers, we need 4 circuits with 4 buffers in each as shown in
figure above. Each group of 4 buffers receives one significant bit from the
4 registers. Each common output produces one of the lines for the common
bus for a total of 4 lines. Only one decoder is needed to select between the
four registers.
Memory Transfer
There are two main operations concerning memory transfers, these are:
1. Read Operation which means transfer of information from a memory
word to the outside environment.
In symbolic form, the Read Operation (transfer of information into Data
Register (DR) from the memory word M selected by the address in the
Address Register (AR)) can be stated as follows:
DR ← M [AR]
Where: AR stands for Address Register, from which the memory
receives the address.
DR stands for Data Register that receives data from the specified
memory word.
M stands for the memory word.
2. Write Operation which means transfer of information from the
outside environment into a specified memory word.
In symbolic form, the Write Operation (transfer of information from
Data Register (DR) into the memory word M selected by the address in
the Address Register (AR)) can be stated as follows:
M [AR] ← DR
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Table 4.3 shows the basic arithmetic microoperations except the shift
microoperation, which will be explained later in conjunction with the shift
microoperations.
The arithmetic Multiply and Divide operations are not included in the table
above since in most computers, the multiplication operation is implemented
with a sequence of add and shift microoperations, while the division
operation is implemented with a sequence of subtract and shift
microoperations.
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Binary Adder
Figure 4.6 shows a 4-bit binary adder. This adder is constructed with 4 full-
adders connected in cascade, with the output carry from one full-adder
connected to the input carry of the next full-adder. The corresponding
augend bits of A and the addend bits of B are the two inputs to the successive
full-adders. The input carry to the binary adder is C0 and the output carry is
C4. The S outputs of the full-adders generate the required sum bits.
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